JPS63250785A - Arithmetic processing circuit - Google Patents

Abstract

PURPOSE:To improve the throughput of the titled circuit by providing the said circuit with an intersecting point calculating circuit combined by plural stages and having pipeline structure as a whole, a selector, etc., and adding an index signal indicating its order to input data. CONSTITUTION:The intersecting point calculating circuit 1 has 4 pipeline stages (1)-(4) as the pipeline structure. In case of supplying an input Vi to the initial stage (1) of the circuit 1 through the selector 2, an index signal IX indicating the order of the input Vi is added to the input Vi and supplied to the circuit 1 together with the signal Vi through the selector 2. Respective processings including the signal IX are executed in respective stages of the circuit 1 and a calculated result Vo having the signal IX is outputted from the stage (4). When intersecting point calculation of the output Vo is required twice or more, the selector 2 is switched, based on the output of the stage (4) and the output Vo is circularly supplied to the stages (1)-(4) again together with the signal IX through the selector 2. Consequently, the throughput can be improved.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to an arithmetic processing circuit.

[Summary of the invention]

The present invention enables appropriate ripping processing to be performed while improving circuit throughput by performing vibe line processing and index processing in a clipping circuit in a graphics system, for example.

[Latest technology]

In a graphics system, when clipping a two-dimensional vector, as shown in Figure 4 A-D, each side of the clipping window is extended to form a straight line A-D. Line segment P to be formed and drawn
Intersection U of Q (drawing vector PQ) and straight line A-1),
-By finding V.

However, in Figures A and B, there are two intersections U,
When V exists, C in the same figure shows when there is no intersection, and the same figure shows when one intersection U exists.

However, when finding the intersection U, ■, line segment PQ and straight line A
Find the intersection with, for example, if there is no intersection,
Next, find the intersection of line segment PQ and straight line B, and so on.
If we were to find the intersection of straight lines A, B, C, and D with the straight line j [A - D in the order of Intersection point calculation In the case of C in the same figure... Four intersection point calculations In the same figure... One intersection point calculation is required. Therefore, it is not possible to know how many times the intersection point calculation is required for one line segment PQ until the clipping process is completed, and in the worst case, four times the intersection point calculation is required.

When determining an intersection point, five calculation processes (or determination processes) from 1 to 2 are required for one intersection calculation, as shown in FIG.

Literature: [Graphic processing optics using computer displays] Published by Nikkan Kogyo Shimbun [Problems to be solved by the invention] Now, for example, as shown in FIG. 6, the 18th input Vi1
Intersection calculation C process 3 times for (drawing vector PQ) 1.
Ct2. By performing C13, the output Vot(
The intersection point U, V) is obtained, the output point 02 is obtained by one intersection calculation C21 for the second input Viz, and the output point 02 is obtained by three intersection calculations C3t to C33 for the third input Vi3. It is assumed that an output VO3 can be obtained.

If all the intersection point calculations are performed sequentially by one intersection point calculation circuit, the output timing will be as shown in FIG. 7, and the throughput will be low.

Therefore, as shown in FIG. 8, the intersection calculation circuit is configured with four pipeline stages [1] to [4] corresponding to the calculation processes ■, ■, ■ and ■, ■, and the inputs Vix to Vi
3 may be pipelined to obtain outputs VOI to VO3.

However, although this pipeline processing improves the throughput, since the intersection point calculations are performed in the flow shown in the same figure, the difference in the number of intersection point calculations for the inputs Vir to Vi3 causes the inputs Vix to Vi3 to The order of outputs o1 to VO3 may be reversed, which is inconvenient for subsequent processing.

This invention attempts to eliminate the above-mentioned problems.

[Means for solving problems]

A plurality of stages that perform individual arithmetic processing are combined to form a pipeline structure, and an index signal indicating the order of the input data is added to the input data, and the input data having this index signal is passed through the pipeline. The data is cyclically supplied to each stage of the structure to perform the desired processing, and the data resulting from this processing is written to a buffer memory using the above index signal as a write address signal, and the data is written to this buffer memory. This is an arithmetic processing circuit in which data is read out and output in the order of the index signals.

(Operation) Throughput is improved and intersection outputs can be obtained in the correct order.

〔Example〕

In Fig. 1, (1) shows the intersection calculation circuit, which has a pipeline configuration, and processes ψ, ■, ■
It has four pipeline stages [1] to [4] corresponding to , , , , , and . In addition, (2) is an input selector, (3) is a dual-port buffer memory, and (4) is an input selector.
) is a read control circuit.

Then, the input Vi passes through the selector (2) to the calculation circuit 1.
1, and as shown in FIG. 2A, an index signal IX indicating the order of the input Vi, for example, in ascending order, is added to the input Vi, and this signal IX is integrated with the input Vi. calculation circuit 11 through selector (2)
).

Then, the calculation circuit (in 11, each stage [1]
In stages [4], the respective processes (1) to (2) are performed while holding the index signal IX, and the calculation result Vo having the index signal IX is output from stage [4] as shown in FIG.

Then, for this output vO, for example, the above-mentioned input Vi
When it is necessary to calculate the intersection point twice or more as in case t, the selector (2) is switched based on the output of stage [4], and the output time is changed to the selector (2) along with the index signal IX.
2) and is again supplied to stage [1].

In this way, the intersection point calculations are performed as many times as necessary (up to four intersection point calculations) for one input card i.

For example, when input Vis, calculation C1t, Cx2+
C10, only calculation C21 is performed when input Vi2. Note that the index signal IX is applied to stages [1] to [4].
].

Further, the intersection point calculation at this time is performed by pipeline processing as shown in FIG.

In this way, the calculation circuit (1) takes out the output 0 for which the intersection point calculation has been performed as many times as necessary. However, at this time, the output Vo is usually in a different order from the input Vi, as shown in FIGS. 8 and 3, due to the difference in the number of intersection point calculations.

However, at this time, the output Vo has the index signal IX added to the input i as it is, and this index signal IX indicates the order of the input Vi.

Therefore, the output vO is supplied to the memory (3) as a data input DI, and the index signal ! × is supplied to the memory (31) as a write address signal -A, and the output vO is written to the address indicated by the signal IX.

At this time, read address signals RA are supplied from the control circuit (4) to the memory (3) in ascending order, that is, in the order indicated by the index signal IX, and therefore, the output Vo from the memory (3) is supplied to the memory (3). Read out in order.

Thus, according to the present invention, the index signal IX is added to the input Vi, and the output Vo is sent to the buffer memory (3) using the index signal tX as a write address.
In addition to writing to , use this as an index signal! Since the data are read in the order of X, the output Vo can be obtained in the same order as the data i. Therefore, even if the number of intersection point calculations for the human corner i is different, the calculation circuit (1) can be used in a cyclic manner to execute pipeline processing, thereby improving throughput.

In addition, in the above, the index signal IX is
), the value of signal IX may be given an offset when provided as a write address signal in FIG.
When there is no intersection, as in the case of , a skip command for subsequent processing may be written in the memory (3). Furthermore, the present invention can also be applied to calculation processing and arithmetic processing such as Newton's method.

〔Effect of the invention〕

According to this invention, the index signal 1x is added to the input Vi, and the output vO is written into the buffer memory (3) using this index signal IX as a write address, and it is read out in the order of the index signal IX. , the output vO can be obtained in the same order as the input Vi. Therefore, even if the number of intersection point calculations for the input Vi is different, the calculation circuit (L) can be used in a cyclic manner to execute pipeline processing, thereby improving throughput.

[Brief explanation of the drawing]

FIG. 1 is a system diagram of an example of the present invention, and FIGS. 2 to 8 are diagrams for explaining the same. (1) is an intersection calculation circuit, (2) is a selector, and (3) is a buffer memory.

Claims (1)

[Claims] A plurality of stages that perform individual arithmetic processing are combined to form a pipeline structure, and an index signal indicating the order of the input data is added to the input data, and an input having this index signal is provided. Data is cyclically supplied to each stage of the pipeline structure to perform the desired processing, and the resulting data is written to the buffer memory using the index signal as a write address signal. An arithmetic processing circuit that reads and outputs written data in the order of the index signal.