JPS63248253A - Data transmission system - Google Patents

Abstract

PURPOSE:To improve the processing performance of a transmission side transmission equipment and to simplify an interface part by executing the flow control only with the internal processing of a reception side transmission equipment without informing the transmission side transmission equipment of the possibility and impossibility condition of the reception side transmission equipment. CONSTITUTION:When a transmission equipment 11 receives the data from a transmission equipment 12, the transmission equipment 12 synchronizes to a clock ST sent from the transmission equipment 11 by a timing signal line 13 and by a reception data line 14, data RD are transmitted at a prescribed information quantity unit, for example, at a bit unit. When a buffer busy occurs while the transmission equipment 11 receives the data RD, the sending of the clock ST to a timing signal line 13 for transmission data of the transmission equipment 12 is stopped. Thus, the transmission equipment 12, while the clock ST for transmitting is stopped, stops the data transmission to the transmission equipment 11. Since when the buffer busy of the transmission equipment 11 is released, the transmission equipment 11 starts to send the clock ST to the timing signal line 13 again, the transmission equipment 12 restarts the data transmission to the transmission equipment 11. Consequently, only with the internal processing of the transmission equipment 11, a flow control is executed.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a data transmission system using a synchronous transmission method, and in particular, the present invention relates to a data transmission system using a synchronous transmission method. A data transmission system that realizes flow control that allows data transmission from a sending transmission device to be stopped or restarted using only the internal processing of the receiving transmission device, without notifying the sending transmission device whether it is ready or not to receive data. Regarding.

[Conventional technology]

In the conventional data transmission system,
No. 49, Japanese Patent Application Laid-Open No. 61-63141, etc., the receiving transmission device notifies the sending transmission device of whether reception is possible or not using a busy signal, and the sending transmission device transmits this busy signal. Flow control was performed by monitoring and canceling the next transmission process if a state where reception was not possible was detected.

[Problem that the invention seeks to solve]

In the above conventional technology, the transmitting side transmission device is required to constantly monitor the busy signal from the receiving side transmission equipment during data transmission and cancel the next data transmission process when a busy signal occurs. There is a problem in that the processing performance of the transmission device is unnecessarily reduced. In addition, the receiving transmission device requires a busy signal transmission circuit, and the transmitting transmission device requires a busy signal processing circuit to stop the next data transmission when a busy event occurs, and the hardware configuration of the interface section is also complicated. It had become.

An object of the present invention is to realize flow control using only the internal processing of the receiving side transmission device without notifying the sending side transmission device of the receiving side transmission device's receivable/unreceivable state.
It is an object of the present invention to provide a data transmission system that can improve the processing performance of a transmitting side transmission device and simplify the interface section.

[Means for solving problems]

The above purpose is configured by connecting two transmission devices via a transmission path including a data line and a timing signal line, and has the function of transmitting data from at least the first transmission device to the second transmission device, and the function of transmitting data. Synchronization having a function of sending a timing signal to cause a second transmission device that receives data to transmit data from the first transmission device to a first transmission device that transmits data in units of a predetermined amount of information. In a data transmission system using a transmission method, the second transmission device.

This is achieved by providing timing signal control means that determines whether the self-equipped device is receivable or not, prohibits the sending of the timing signal in the unreceivable state, and cancels the prohibition of sending the timing signal in the receivable state. Ru.

[Effect]

The timing signal control means detects this state when the own transmission device is unable to receive data due to buffer busy etc. while receiving data from the other party's transmission device, and transmits data from the own transmission device to the other party's transmission device. Temporarily stops sending out the timing signal for data transmission. The other party's transmission device, whose supply of the timing signal for data transmission is stopped, is no longer able to transmit data and stops the data transmission process. When the buffer busy state is released and the own transmission device returns to a receivable state, the timing signal control means detects this state and causes the other party's transmission device to resume sending out the timing signal for data transmission. Upon receiving the data transmission timing signal, data transmission processing is performed again. In other words,
The destination transmission device operates as if the pulse interval of the data transmission timing signal had been temporarily lengthened when reception busy occurs, without monitoring whether the transmission destination is enabled or disabled. Thereby, flow control can be realized only by the internal processing of the transmission device itself, without reducing the processing performance of the other transmission device.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 shows the form of transmission between transmission devices in a data transmission system using a synchronous serial transmission method. 11 receive data lines 14. Timing signal line 1 for data transmission of transmission device 11
5 and a transmission data line 16 of the transmission device 11. In this figure, for convenience, the transmission device 12 is shown to correspond to the first transmission device, and the transmission device 11 is shown to correspond to the second transmission device.

When the transmission device 11 transmits data to the transmission device 12, a data transmission timing signal (hereinafter abbreviated as clock) S is sent via the timing signal line 15.
In synchronization with the clock SC, the data SD is transmitted in a predetermined information amount unit (for example, bit unit) using the transmission data "!llAl6. In this case, the transmission device 12 receives the data SD in synchronization with the clock SC. , when the transmission device 11 receives data from the transmission device 12, the transmission device 12
transmits the data RD in a predetermined information amount unit (eg, bit unit) through the reception data line 14 in synchronization with the clock ST sent from the transmission bag C1l through the timing signal line 13. In this case, the transmission device 11 receives the data RD in synchronization with the clock ST.

In the above transmission mode, when the transmission device 11 uses up the entire reception buffer while receiving the transmission data RD from the transmission device 12 and becomes unable to receive the next data, in the prior art, A special data pattern is sent to indicate that the buffer is busy, and the transmission device 12 decodes the data pattern and temporarily stops sending data to the transmission device 11. Flow control is performed by adding a special signal line to notify the transmission device 11, and when the transmission device 12 detects that the buffer of the transmission device 11 is busy through the signal line, it temporarily stops sending data to the transmission device 11. These methods require the transmission device 12 to constantly monitor the buffer status of the transmission device 11.

In contrast, in the present invention, the transmission device 11 in which the buffer busy has occurred stops sending the clock ST to the data transmission timing signal line 13 of the transmission device 12. Then, the transmission device 12 stops transmitting data to the transmission device 11 while the transmission clock ST is stopped. When the buffer busy state of the transmission device 11 is released, the transmission device 11 again uses the data transmission timing signal line 13 of the transmission device 12.
Since the transmission device 12 starts sending the tarok ST to the transmission device 11, the transmission device 12 resumes data transmission to the transmission device 11. Therefore, there is no need to monitor the buffer status of the transmission device 11 on the transmission device 12 side, and flow control can be realized only by the internal processing of the transmission device 11.

Next, the specific configuration of this embodiment is shown in FIGS. 1 and 3.

This will be explained in detail using FIG.

FIG. 1 shows the internal configuration of the transmission device 11. As shown in FIG. That is, the transmission device 11 includes a microcomputer (MPU) 21 . Buffer memory 22. Transmission circuit 25
．． Receiving circuit 23. Clock generation circuit 24. It consists of a decoder 26 that decodes an instruction as to whether or not to inhibit clock transmission from the MPU 21 to the clock generation circuit 24, and the above-mentioned parts are connected by a bus 270. Also MPU2
1 is a reception request interrupt 271.1 from the reception circuit 23. A transmission request interrupt 272 from the transmission circuit 25 is input. In addition,
The processing flow of the MPU 21 includes a function to determine whether reception is possible or not according to the reception buffer busy state of the transmission device 11, internal processing capacity, priority, etc.

FIG. 3 shows the internal configuration of the transmission device 12. That is, the transmission device 12 includes a microcomputer (MPU) 31 . Buffer memory 32. Receiving circuit 33
．． It consists of a transmitting circuit 34, and the above-mentioned parts are connected by a bus 350, and a receiving request interrupt 351 is sent from the receiving circuit 33, and a sending request interrupt 352 is sent from the sending a circuit 34 to the MPU.
31.

The transmission device 11 and the transmission device 12 are connected via the four signal lines 13 to 16 described in FIG. 2.

FIG. 4 shows the internal configuration of the clock generation circuit 24 in FIG. 1. In other words, the tarlock generation circuit 24 uses the oscillator 40
．． D flip-flop41. Inverter 42. It consists of an AND gate 43, and the D input of the D flip-flop 41 has a busy signal (BSY) 273, which is the output signal of the decoder 26 shown in FIG. The output of the inverter 42 (CLK) 441. Power supply voltage V is applied to the S input.
A reset signal from the MPU 21 is input to the cc and C inputs, and the AND gate 43 receives the sum of the output clock 440 of the oscillator 40 and the D flip-flop 41 ((
BSY-FF) 442 is input. The and gate 4
The output of No. 3 is connected to the data transmission timing signal line 13 of the transmission device 12.

The normal transmission and reception operations of the transmission device configured as described above will be explained using the timing chart of FIG.

First, when the transmission device 11 receives data from the transmission device 12, in the transmission device 11 of FIG. 1, a clock transmission permission command is sent from the MPU 21 to the decoder 26 via the bus 270. Then, the busy signal (BSY) 273, which is the output signal of the decoder 26, becomes the "L11 level."In the clock generation circuit 24 of FIG. Output signal of flip-flop 41 (BSY-FF
) 442 is at the 11H" level, the AND gate 4 is connected to the data transmission timing signal line 13 of the transmission device 12.
The output clock 440 of the oscillator 40, which is the output signal of the oscillator 40, is sent out. Transmission device shown in Figure 3! 112 is.

The clock (ST) 440 is received by the transmitting circuit 34 via the data transmitting timing signal line 13.

MPU 3 receives transmission request interrupt 352 from transmission circuit 34
1 transfers the transmission data in the memory 32 to the transmission circuit 34 via the bus 350, and the transmission circuit 34 receives the transmission data (RD) as n, n+1 . n+2.・・・
The data is transmitted onto the reception data line 14 in synchronization with the clock (ST) 440 as shown in FIG. When the transmission device 11 in FIG. 1 receives transmission data (RD) from the transmission device 12 in the reception circuit 23, a reception request interrupt 271 occurs. Upon receiving the reception request interrupt 271 , the MPU 21 takes in the received data from the reception circuit 23 via the bus 270 and stores it in the buffer memory 22 .

The same applies when transmitting data from the transmission device 11 to the transmission device 12, and the transmission request interrupt 272 from the transmission circuit 25
The MPU 21 receives the memory 22 via the bus 270.
The transmission data within is transferred to the transmission circuit 25. Transmission circuit 2
5 transmits the received transmission data (SD) onto the transmission data line 16 in synchronization with the clock (SC) sent from the clock generation circuit 24 to the data transmission timing signal line 15. In the transmission device 12 that has received the data (SD), the MPU 31 receives a reception request interrupt 351 from the reception circuit 33.
and the receiving circuit 33 receives the received data via the bus 350.
and stores it in the memory 32.

Next, the operation when a buffer busy occurs while the transmission bag [11 is receiving data from the transmission device 12] will be described.

In the transmission device 11 shown in FIG. 1, the MPU 21 detecting the buffer busy sends a clock transmission prohibition command to the decoder 26 via the bus 270. The busy signal (BSY) 273, which is the output signal of the power and Tecoder 26, is 'H'.
Therefore, at the rising edge of the output signal (CLK) 441 of the inverter 42 in the clock generation circuit 24 (point a in FIG.
Y/FF) 442 becomes the izLyt level, and therefore the clock transmission from the AND gate 43 to the timing signal line 13 for data transmission stops, and the transmission clock (S
T) remains at the riL" level. Then.

The transmission device 12 is no longer able to transmit data, and the (n+3i)th data (RD) is held on the reception data line 14. When the buffer busy status of the transmission device 11 is released, the MPU 21 sends a clock transmission permission command to the decoder 26 via the bus 270. Then, the busy signal (BS
'Y) 273 goes to the 'L' level again, so the output signal (BSY-FF) 442 of the D flip-flop 41 goes to the 'H' level at the point shown in FIG.
At the point, the transmission device 11 has a timing signal line 1 for data transmission.
The transmission device 12 starts sending the transmission clock (ST) again to the transmission clock (ST) on
4. n+5. The transmission of data (RD) to the reception data line 14 is restarted as follows.

In other words, the transmission device 12 can receive the transmission bag ff1ll.

Without monitoring the disabled state, it operates as if the pulse interval of the clock (ST) on the transmission timing signal line 13 had been temporarily lengthened.

FIG. 6 shows an example of application of the present invention. In this example, the computer (first
transmission device) 62 to the printer (second transmission device) 61
This is a case where data is sent to the printer 6 and printed.
1 and the computer 62 are connected via a data transmission timing signal line 13 of the computer 62 and a reception data line 14 from the computer 62. Here, the printer 61 can print only at a certain processing speed, and if data is received in excess of the processing speed, a buffer busy condition occurs. According to the present invention, when a buffer busy occurs, as described above, by stopping the transmission of the transmission clock (ST) from the printer 61 to the data transmission timing signal line 13, Transmission of data (RD) can be temporarily stopped.

〔Effect of the invention〕

According to the present invention, when a reception-disabled state such as buffer busy occurs in a transmission device, a special data pattern is sent to the other transmission device in order to temporarily stop data transmission from the other transmission device, and the transmission device There is no need to install a special signal line between the transmission devices to notify them of the unreceivable state. Flow control can be achieved. In other words.

Since the sending transmission device can transmit data without monitoring whether the receiving transmission device is ready or not, the processing performance of the sending transmission device is completely synchronized with the processing capacity of the receiving transmission device. Unnecessary performance deterioration can be prevented. In addition, the busy signal transmission circuit of the receiving side transmission device,
Since the busy signal processing circuit of the transmission device on the transmitting side is not required, there is an effect that the cost of the interface section can be lowered and the reliability can be increased.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a transmission device having a timing signal control means showing an embodiment of the present invention, FIG. 2 is a connection diagram between transmission devices, FIG. 3 is a block diagram of a partner transmission device, and FIG. 4 is a detailed circuit diagram of the tarlock generation circuit in FIG. 1, FIG. 5 is a timing chart of flow control according to this embodiment, and FIG.
The figure is a connection diagram between a computer and a printer, which is an application example of the present invention. DESCRIPTION OF SYMBOLS 11... Second transmission device, 12... First transmission device, 13... Timing signal line for data transmission of the first transmission device, 14... Received data of the second transmission device line, 1
5... Timing signal line for data transmission of the second transmission device, 16... Transmission data line of the second transmission device, 22.
32...Buffer memory, 23.33...Reception circuit, 25.34...Transmission circuit, 24...Tarlock generation circuit, 21, 26, 4.0, 41, 42.43...Timing (No. 3 control means... (21... microcomputer, 26... decoder, 40... oscillator,
41...D flip-flop, 42...Inverter, 43...AND gate), 61...Printer (second transmission device), 62...Computer (first transmission device)
.

Claims (1)

[Claims] It is configured by connecting one or two transmission devices via a transmission line including a data line and a timing signal line, and has a function of transmitting data from at least the first transmission device to the second transmission device;
A function for sending a timing signal from a second transmission device that receives data to a first transmission device that transmits data to cause the first transmission device to transmit data in units of a predetermined amount of information. In a data transmission system using a synchronous transmission method, the second transmission device determines whether its own device is in a receivable state or not, and in a receivable state, prohibits the transmission of the timing signal, and in a receivable state, transmits the timing signal. 1. A data transmission system comprising timing signal control means for canceling a prohibition on transmission of a data transmission system.