JPS63248170A - Semiconductor device - Google Patents

Abstract

PURPOSE:To inhibit the injection of hot electrons into a gate oxide film by an applied surge by forming a section between an input terminal and a gate electrode for a parasitic MOS transistor with a resistance material. CONSTITUTION:A resistor R3 is shaped between a gate electrode 7a on a channel region existing between the regions of mutually opposed source 5b and drain 5a in a parasitic MOS transistor TR1 and an input terminal IN. When surge voltage is applied at the terminal IN, gate voltage generates a voltage drop because there is the resistance load R3 in a gate section for the Tr TR1, thus preventing the generation of electrons on the interface between a field oxide film 3 and an Si substrate 1 in the channel region in the Tr TR1, then obviating the flow of channel currents. Accordingly, the injection of hot electrons to the film 3 is difficult to be generated, and the leakage currents of the terminal IN are hardly generated.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention includes an input protection circuit for protecting a device from external surges such as static electricity applied to an input terminal, and is particularly applicable to a semiconductor substrate of a -conductivity type. The present invention relates to a MOS semiconductor device having a resistor and a parasitic MOS transistor manufactured from an impurity layer of opposite conductivity type.

[Conventional technology]

A general example of the above input protection circuit is shown in Part 2), and a mask pattern is shown in Part (b). Normally, the input terminal IN is At
(aluminum), etc., and a resistor (second
R1 and R2 in the figure (al) and 5a in (b) are formed of an impurity diffusion layer or a polycrystalline silicon layer.

Therefore, the operating principle of this input protection circuit will be explained.

In FIG. 2 (al), when a surge voltage is applied to the input terminal IN, the surge voltage is relaxed by the resistor R, and is applied to the drain node of the parasitic MOS transistor TR,
The potential at the node (2) is discharged to the ground potential (OV) by the parasitic transistor (A108) transistor TR, which is already in a conductive state.

Here, the resistor R2 is connected to the input transistor TR due to an increase in the potential of the node 0 due to the input surge voltage.

By delaying the gate voltage of the parasitic MOS (parasitic MOS transistor) by a time constant R2C5t from the switching speed of the transistor transistor 1, the potential of the node (2) is quickly discharged to the ground potential, which has the effect of protecting the gate oxide film of the input transistor TRo.

[Problem that the invention seeks to solve]

As shown in FIG. 2(a), hot electrons are generated in the vicinity of the drain of the parasitic MOS transistor TR1 due to the high potential of the node ■ due to the input surge voltage, and Electrons are injected into the gate oxide film (3 in FIG. 2C) by the following process.

3(a) and 3(b) are enlarged views of FIG. 2(1). As shown in FIG. 3(al), when a positive surge is applied to the input terminal 7a, the parasitic MOS transistor T Rt
Electrons are induced into the silicon substrate 1 directly under the gate oxide film (particularly the field oxide film) 3. Since the drain 5a of the parasitic MOS transistor TR has a high positive potential, the induced electrons flow from the source 5b to the drain 5a, causing a channel current i to flow.

Electrons flowing from the source 5b to the drain 5a turn into hot electrons in order to obtain maximum energy near the drain. These hot electrons are originally attracted to the drain 5a, but some of them are scattered and their direction becomes random. Therefore, there is a probability that it will arrive at the interface between the P-type silicon substrate (P-8i) and the gate oxide film (Si02) of the parasitic MOS transistor. If it has enough energy to jump over the SiO2 barrier to electrons, it will enter 5iOz.

Therefore, as shown in FIG. 3(b), electrons are injected into the gate oxide film near the drain of the parasitic MOS transistor, particularly into the field oxide film 3 in contact with the P-type silicon substrate 1, by applying the input surge voltage. High-density positive charges are induced in the silicon substrate 1 between the drain 5a and the field oxide film 3 by the electrons injected into the field oxide film 3. When the device is normally operated in this state, when a bias is applied to the multiple input terminal 7a, the depletion layer 9 formed under the impurity density layer 5a connected to the input terminal 7a is formed between the drain 5a and the field oxide film 3. becomes very narrow. Therefore, the breakdown voltage between the impurity density layer 5a and the silicon substrate 1 is low, and when a bias is applied to the input terminal 7a, a leakage current iT is generated.

As mentioned above, by applying input surge voltage, parasitic MO
A channel is generated directly under the S transistor, and electrons, which are carriers, flow within the channel and are injected into the 8 iCh. As a result, 5i
There was a problem in that positive charges were generated by the electrons injected into the device, lowering the withstand voltage of the impurity density layer connected to the input terminal, and causing leakage current during device operation.

Therefore, an object of the present invention is to solve the above problems, suppress the injection of hot electrons into the gate oxide film due to the surge applied to the input terminal, and improve the
An object of the present invention is to provide an OS type semiconductor device.

[Means for solving problems]

A semiconductor device of the present invention includes a resistor and a parasitic MOS transistor comprising a -conductivity type semiconductor substrate and an opposite conductivity type impurity layer, which are included in an input protection circuit of the semiconductor device.
In an OS type semiconductor device, an input terminal and the parasitic MOS
) The transistor is characterized in that the space between the gate electrodes is formed of a resistive material. [Example] Next, an example of the present invention will be described with reference to the drawings. FIG. 1(a) shows a circuit diagram of the present invention, and FIG. 2(a) shows a circuit diagram of the present invention.
FIG. 1(b) shows a mask pattern diagram of an embodiment of the present invention, and corresponds to FIG. 2(b).

This embodiment differs from the conventional example in that in FIG. 1(a) there is a resistance at the gate of the parasitic MOS transistor TR1, and in FIG. 1(b), the opposing sources 5b of the parasitic MOS transistor , there is a resistance (poly resistance, diffused resistance, etc.) between the input terminal and the gate electrode 7a on the channel region existing between the regions of the drain 5a. When a surge voltage is applied to the input terminal 9a, the parasitic MO
S) Since there is a resistive load on the gate of transistor TR1, the gate voltage drops and electrons are generated at the field oxide film 3-silicon substrate 1 interface in the channel region of parasitic MOS) transistor TRt. ＜＜, the channel current is difficult to flow. Therefore, the phenomenon of hot electron injection into the field oxide film 3 is less likely to occur, and leakage current at the input terminal 9a is less likely to occur.

〔Effect of the invention〕

As explained above, the present invention makes it difficult for electrons to be generated directly under the field oxide film in the channel region by applying a resistive load to the gate electrode on the channel in a parasitic MOS transistor, and prevents hot electrons from entering the oxide film. It has the effect of suppressing the injection phenomenon.

[Brief explanation of drawings]

FIG. 1(a) is an equivalent circuit diagram of the present invention, FIG. 1(b) is an example of the mask pattern, and FIG. 1(C) is a cross-sectional view of FIG. 1(b). FIG. 2(a) shows a conventional input protection circuit, FIG. 2(b) shows an example of the mask pattern of FIG. 2(a), and FIG. 2(C) shows a conventional input protection circuit. ) is shown. FIGS. 3(a) and 3(b) show enlarged views of (1) in FIG. 2(C). IN...Input terminal, 1. R2, 几3...
...Resistance, TR, ...MOS) transistor,
IIIR, o... Input transistor, Cat.
... Stray capacitance. Agent: Susumu Uchihara, patent attorney. Bud /T! ! l? b

Claims (1)

[Claims] Resistance and protection M comprised of a conductive type semiconductor substrate and an opposite conductive type impurity layer, provided in an input protection circuit of a semiconductor device
1. A MOS semiconductor device having an OS transistor, characterized in that an input terminal and a gate electrode of the protection MOS transistor are connected by a resistor.