JPS63246854A - Package structure of electronic part - Google Patents
Package structure of electronic partInfo
- Publication number
- JPS63246854A JPS63246854A JP8161787A JP8161787A JPS63246854A JP S63246854 A JPS63246854 A JP S63246854A JP 8161787 A JP8161787 A JP 8161787A JP 8161787 A JP8161787 A JP 8161787A JP S63246854 A JPS63246854 A JP S63246854A
- Authority
- JP
- Japan
- Prior art keywords
- projections
- package
- semiconductor elements
- board
- contact
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000011347 resin Substances 0.000 claims abstract description 9
- 229920005989 resin Polymers 0.000 claims abstract description 9
- 238000007789 sealing Methods 0.000 claims description 5
- 239000004065 semiconductor Substances 0.000 abstract description 29
- 238000004806 packaging method and process Methods 0.000 abstract description 4
- 230000007547 defect Effects 0.000 abstract description 3
- 238000009413 insulation Methods 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 2
- 239000000969 carrier Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明はpIIcc (プラスチック・リーデツド・
チップ・キャリヤ)等で代表される表面実装型の電子部
品のパッケージ構造に関するものである。[Detailed Description of the Invention] [Industrial Application Field] This invention relates to pIIcc (Plastic Leaded
This relates to the package structure of surface-mounted electronic components such as chip carriers.
半導体素子のパッケージ構造の平面を示す。図において
(1)は半導体素子でリードフレームに半導体チップを
接続したのち樹脂封止しリード部(粉を内側に折り曲げ
たものである。(■は封止樹脂である。1 shows a plan view of a package structure of a semiconductor device. In the figure, (1) is a semiconductor element in which a semiconductor chip is connected to a lead frame and then sealed with resin and the lead part (powder is bent inward. (■ is the sealing resin).
また第4図は上記半導体素子(1)をpo(プリント書
サーキット)ボード等の配線基板に表面実装した状態を
示す。第5図はその側面図である。Further, FIG. 4 shows a state in which the semiconductor element (1) is surface-mounted on a wiring board such as a PO (print circuit) board. FIG. 5 is a side view thereof.
図において(5はPCボード等の配線基板でハンダ(7
)により上記半導体素子(1)を接続したものである。In the figure (5 is a wiring board such as a PC board, solder (7)
) in which the semiconductor elements (1) are connected.
第4図のようにpaボード等の配線基板(5)に前述の
半導体素子(1)を実装したときに近年の高密度実装化
に伴ってとなり合う半導体素子間のすき間(6)が小さ
くなる傾向になってきている。このような傾向の中で従
来の半導体素子のパッケージ構造にあっては絶縁を保つ
ための空間が必ず必要であり、高密度実装のさまたげと
なっている。また、絶縁を保つための空間を設けてぃる
場合でも、半導体素子の加工精度や配線基板(Sへの半
導体素子の搭載精度等の影響によりすき間(0がなくな
り、となり合う半導体素子間でリードの接触により短絡
を生ずるなどの問題点があった。As shown in Figure 4, when the aforementioned semiconductor element (1) is mounted on a wiring board (5) such as a PA board, the gap (6) between semiconductor elements next to each other becomes smaller due to the recent trend towards high-density packaging. This is becoming a trend. Amid this trend, conventional semiconductor device package structures always require a space to maintain insulation, which hinders high-density packaging. In addition, even if a space is provided to maintain insulation, the gap (0) may disappear due to the processing accuracy of the semiconductor element, the accuracy of mounting the semiconductor element on the wiring board (S), and the leads between adjacent semiconductor elements may be removed. There were problems such as short circuits caused by contact between the two.
この発明は、上記のような問題点を解消するためになさ
れたもので、実装に際してとなり合う半導体素子間で、
リードの接触により短絡不良を生じない電子部品のパッ
ケージ構造を得ることを目的とする。This invention was made to solve the above-mentioned problems, and when semiconductor elements are mounted next to each other,
The purpose of the present invention is to obtain a package structure for electronic components that does not cause short-circuit defects due to lead contact.
この発明に係る電子部品のパッケージ構造はパッケージ
側面に突起を設けたものである。The electronic component package structure according to the present invention has a protrusion on the side surface of the package.
この発明におけるパッケージは側面部に突起が形成され
ているので、PCボード等の配線基板に複数個実装した
際に半導体素子の加工精度や配線基板への半導体素子の
搭載精度等の影響によっても、となり合う半導体素子間
でリードが接触することなく絶縁性が保持できる。Since the package according to the present invention has a protrusion formed on the side surface, when a plurality of semiconductor elements are mounted on a wiring board such as a PC board, the processing accuracy of the semiconductor element and the mounting accuracy of the semiconductor element on the wiring board may be affected. Insulation can be maintained between adjacent semiconductor elements without the leads coming into contact with each other.
〔実施例〕
第1図はこの発明の一実施例による電子パッケージの平
面を示す。図において(1)〜(Jは第3図乃至第5図
の従来例と同一ないし相当部分を示す。(→は封止樹脂
(■の側面部に設けた本発明の特徴とする突起である。[Embodiment] FIG. 1 shows a plan view of an electronic package according to an embodiment of the present invention. In the figures, (1) to (J indicate the same or equivalent parts as in the conventional example shown in Figs. 3 to 5. .
この突起(4はほぼ四角形のパッケージの各側面の両端
に設けられており、その突出量は少なくともリード部よ
りも多くしである。These protrusions (4) are provided at both ends of each side of the approximately square package, and their protrusion amount is at least greater than the lead portion.
この実施例における突起物(→は封止樹脂(3)の、側
面に形成されているので、PCボード等の配線基板に半
導体素子(1)が複数個隣り合って実装されたときにと
なり合う半導体素子間でリード(渇が接触し短絡する不
良を防止することができる。In this example, the protrusions (→ are formed on the side surfaces of the sealing resin (3), so when multiple semiconductor elements (1) are mounted next to each other on a wiring board such as a PC board, they will sit next to each other. It is possible to prevent defects such as short circuits caused by contact between leads between semiconductor elements.
なお、これら突起はパッケージの側面の両端に形成され
なければならないということはなく、パッケージが隣接
配置されたとき、リード部よりも先に突起が対接するよ
うにしたものであればよい。Note that these protrusions do not have to be formed at both ends of the side surface of the package, but it is sufficient that the protrusions come into contact with each other before the lead parts do when the packages are placed adjacent to each other.
以上のようにこの発明によれば、封止樹脂部の側面部に
突起を設けたので、POボード等の配線基板に複数個実
装した際にとなり合う半導体素子間でリードの接触を防
止することができる。As described above, according to the present invention, since the protrusion is provided on the side surface of the sealing resin part, it is possible to prevent leads from coming into contact between neighboring semiconductor elements when a plurality of semiconductor elements are mounted on a wiring board such as a PO board. Can be done.
第1図はこの発明の一実施例による半導体素子のパッケ
ージ構造を示す上面図。第2図は第1図に示した半導体
素子をpcボード等の配線基板に複数個実装したときの
上面図。第3図は従来の半導体素子のパッケージ構造を
示す上面図。
第4図は第3図に示した半導体素子をPCボード等の配
線基板に複数個実装したときの上面図、第5図はその側
面図である。
図において(1)は半導体素子、(りはリード部、(印
は封止樹脂、(4)は突起、(5)はPOボード等の配
線基板、(6)はとなり合う半導体素子のリード間のす
き間、(?)はハンダである。
なお、各図中同一符号は同一または相当部を示す。
代理人 弁理士 大 岩 増 雄第1図
第2図
第3図FIG. 1 is a top view showing a package structure of a semiconductor device according to an embodiment of the present invention. FIG. 2 is a top view when a plurality of semiconductor elements shown in FIG. 1 are mounted on a wiring board such as a PC board. FIG. 3 is a top view showing a conventional semiconductor device package structure. FIG. 4 is a top view when a plurality of the semiconductor elements shown in FIG. 3 are mounted on a wiring board such as a PC board, and FIG. 5 is a side view thereof. In the figure, (1) is the semiconductor element, ((ri) is the lead part, (mark is the sealing resin, (4) is the protrusion, (5) is the wiring board such as a PO board, and (6) is between the leads of adjacent semiconductor elements. The gap (?) is solder. The same reference numerals in each figure indicate the same or corresponding parts. Agent: Masuo Oiwa, Patent Attorney Figure 1, Figure 2, Figure 3
Claims (3)
電子部品のパツケージ構造。(1) A package structure for electronic components characterized by a protrusion provided on the side surface of the package.
端に突起が設けられている特許請求の範囲第1項記載の
パツケージ構造。(2) The package structure according to claim 1, wherein the package cage has a substantially rectangular shape, and projections are provided at both ends of each side surface.
で形成されている特許請求の範囲第1項または第2項記
載のパツケージ構造。(3) The package structure according to claim 1 or 2, wherein the package is made of resin sealing, and the protrusion is formed of the resin.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8161787A JPS63246854A (en) | 1987-04-01 | 1987-04-01 | Package structure of electronic part |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8161787A JPS63246854A (en) | 1987-04-01 | 1987-04-01 | Package structure of electronic part |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS63246854A true JPS63246854A (en) | 1988-10-13 |
Family
ID=13751282
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8161787A Pending JPS63246854A (en) | 1987-04-01 | 1987-04-01 | Package structure of electronic part |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63246854A (en) |
-
1987
- 1987-04-01 JP JP8161787A patent/JPS63246854A/en active Pending
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