JPS63244269A - Vector arithmetic processor with mask - Google Patents

Abstract

PURPOSE:To efficiently operate a vector with mask by constituting the titled processor so that the operation is not achieved but avoided when the operation is masked by means of a mask bit. CONSTITUTION:An output from a shift register 4 holding an operational mask bit string is transmitted to an arithmetic control part 2, as well through a microinstruction bus MI so that the operation is not executed at a time when the operation is masked, and at the same time, a sequential transmission from stage to stage through an arithmetic pipeline is not executed always after waiting for the end of arithmetic operation but even one machine cycle is enough during the masking of the operation. Accordingly, in order to facilitate the control of a microprogram, a queuing logic signal (e) for a microinstruction is outputted at the time of executing the arithmetic operation, and the operation is executed within one instruction step. Therefore, in an arithmetic pipeline stage where the operation is masked, the processing can be completed in only one machine cycle, hence the processing time can be shortened to one several number-th when the masking of operation consecutively repeats.

Description

[Detailed Description of the Invention] [Effects of the Invention] (Industrial Application Field) The present invention provides an array operand vector operation that includes mask information for controlling whether or not to execute the operation. , relates to a masked vector arithmetic processing device that performs arithmetic vibe line processing.

(Prior art) In vector operations that process a large amount of array operand data, all array data is read out continuously from the main memory, and operations are performed on each operand data according to the tiIJ control pit row. However, there is arithmetic processing that switches between storing the result and masking the calculation, that is, outputting and storing the operand data as is.

FIG. 3 shows a schematic block diagram of a processing device as an example of a conventional calculation.

This example has two calculation pipeline stages,
It has input data buses A and B, an output data bus S1, and a microinstruction bus Ml for outputting microinstructions from the microprograms i and lJ 111 section 1. 2
is an arithmetic control unit which includes a buffer register 21 for storing operand data received from the data bus A1B, a performance circuit 22, 24, a pipeline register 23, a performance W y+
It includes a w circuit 29 and an output driver circuit 25 for outputting it to the bus S.

Further, 3 is a vector control section with a mask, which includes a buffer 7 register 31, a shift register 37, a vibe line register 32, an output driver circuit 33, and a mask control circuit 3.
It is composed of 8.

To explain the operation of FIG. 3, microinstructions from the microprogram υ control section 1 are outputted via the bus MI to the arithmetic control section 2 and the control sections 29 and 38 of the masked vector 1ull ti11 section, and the respective controls are performed. It is done.

First, a mask bit string is taken into the shift register 37 via the data bus B. Next, the operation tJJII unit 2 and the masked vector 1i11111 unit 3 are simultaneously activated by the microinstruction. The arithmetic control unit 2 receives the first operand of the operand p from the data bus A and the second operand from the bus B, and the intermediate result of these operands being computed by the first stage arithmetic circuit 22 via the buffer register 21 is sent to the vibe. It is stored in the line register 23. at the same time,
The first operand is the masked vector ul from bus 8 @
The signal is taken into the buffer 7 register 31 of the section, and stored in the vibe line register 32 together with the corresponding mask bit (MSB) of the shift register 37.

Next, in the performance monument υ118 part 2, the second stage arithmetic circuit 2
4, the second performance is executed and the result is output to the data bus S through the output driver 25.

On the other hand, from the masked vector control section 3, the output driver 3
3, a signal for controlling the output of the first operand is output. At this time, the mask bit held in the pipeline register 32 exclusively selects one of the output drivers 25 and 32, and only one of the operation result and the original first operand data is used as data. It is output to bus S.

Such masked vector arithmetic processing is continuously executed in a pipeline manner under microinstructions. That is,
When an operation is being performed in the second stage, the next operand data is being operated on in the first stage. For this purpose, for example, the vibration line register 2 of the arithmetic control unit 2
3 is first performed when not only the performance of the first stage n11 but also the second stage is completed, and the vibe line register 32 of the masked vector υ1tl1 part 3 is also loaded in synchronization with this. Also, data cannot be taken into the buffer 7 register 21.31 unless the first stage is empty.

Here, in the case where it takes several machine cycles to execute the calculation in the calculation circuits 22 and 24 of each stage, even when the calculation is masked by the mask bit, the V calculation can always be executed with the above configuration. There is a problem in that the operation must be held until the operation is completed, which deteriorates efficiency.

(Problems to be solved by the invention) In this way, in conventional masked vector operations,
Even when an operation is masked and unnecessary, there is a problem in that the operation is always executed and the process cannot proceed until it is finished, which causes a deterioration in processing efficiency.

It is an object of the present invention to eliminate such problems and to enable efficient execution of masked vector operations.

[Structure of the Invention] (Means for Solving the Problem) In order to achieve such an object, the present invention provides a method for avoiding the operation by not executing it when the operation is masked by mask bits. I made it possible.

In other words, the output of the shift register holding the operation mask bit string is also transferred to the operation II part 1 via the microinstruction bus, and the operation is not executed when masking the operation p. Instead of always performing the sequential transfer after the end of the calculation as in the past, it is now possible to do it in one machine cycle when masking the calculation.

In order to facilitate fi control of the microprogram for this purpose, a microinstruction wait logic signal is output when an operation is executed, so that the operation is executed in one instruction step.

(Function) With this kind of structure, not only can you control the execution of calculations as before, but also the processing can be completed in just one machine cycle in the calculation pipeline stage where the calculation is masked. When the masks are continuous, the processing time is reduced to a fraction of that, and vector operations with masks can be executed efficiently.

(Embodiment) FIG. 1 shows a schematic block diagram of main parts of a masked vector arithmetic processing device as an embodiment to which this embodiment is applied. In this example, a two-stage calculation pipeline stage is used, corresponding to the conventional example shown in FIG. A and B are input data buses,
S is the output data bus. It also has a microprogram control unit 1 that manages the entire vector operation, and its microinstruction bus MI. 2 is an arithmetic control unit, and a buffer 7
It contains a register 21, arithmetic circuits 22 and 24 of each stage and their control circuits 26 and 28, pipeline registers 23 and 27 for data and mask information, and an output driver 25. Furthermore, the masked vector tiiJtI1 section 3 includes a buffer register 31 for the first operand, a pipeline register 32, and a mask control circuit 34 for each stage.
and 36, a pipeline register 35 for mask information, and an output driver 33. A shift register 4 stores a mask bit string and outputs mask bits f sequentially from the first bit onto the microinstruction bus M1. Note that e is a microinstruction wait logic signal.

Next, the operation will be described. First, the corresponding mask bit string is stored in the shift register 4 via the data bus A. Next, the microprogram control unit 1 transmits an activation command to the arithmetic control unit 2 and masked vector II 111 unit 3 via the microinstruction bus MI, and at the same time, the first mask bit from the shift register 4 is transferred to the masked vector II 111 unit 3 via the microinstruction bus MI. M
It is output on I and transmitted to each part. The shift register 4 shifts these 11 bits by one, and the next mask bit is moved to the beginning. The mask bits transmitted to the arithmetic control section 2 are used by control circuits 26 and 28 to switch the execution of arithmetic operations at each stage.

That is, in the first stage, if the mask bit is not set, the first operand is taken into the buffer register 21 from the data bus A, and the second operand is taken from the data bus B, and the arithmetic circuit 22 of the first stage is activated.
) Execute PI3 paralysis. The calculation result is stored in the pipeline register 23.

Further, the arithmetic control circuit 26 outputs a signal e for making the microinstruction wait until the above arithmetic operation is completed and the result is stored in the register. At this time, the masked vector control unit 3 is prohibited from operating (this is referred to as operation A1).
. Conversely, if the mask bit is set, the masked vector til control unit 3 takes in the first operand data sent from the data bus A into the buffer 7 register 31, and then transfers this data into the pipeline register 32. (referred to as operation M1). At this time, the mask bits are held in pipeline registers 27 and 35 on both sides.

Next, in the second stage operation, if the mask bit held in the pipeline register 27 is not set, the intermediate data stored in the pipeline register 23 will be operated in the arithmetic circuit 24 following the above operation. Then, the result is output to the output data bus S via the output driver 25 (operation A2). Conversely, if the mask bit held in the pipeline register 35 is set, the masked vector control unit 3 converts the first operand data stored in the pipeline register 32 to output data via the output driver 33. Output to bus S (operation M2)
. At this time, operation is prohibited in each opposing portion.

While the second stage operation A2 or M2 as described above is being performed, the next array data operand can be processed simultaneously in the first stage, and the first stage operation △1 or It is carried out in the same manner as Ml. Thereafter, corresponding mask bits are similarly outputted from the shift register 4 for each operand data, and processing is sequentially executed in accordance with this until these bits are shifted out.

FIG. 2 is an operational conceptual diagram showing the operation of "-" as time passes. As mentioned above, A1 and A2 represent the calculation processing of the first and second stages, and Ml and M2 represent the mask processing of the first and second stages, respectively. FIG. 2a shows a case where the mask bit continues to be not set, and only the operations A1 and A2 in the arithmetic control section 2 are repeated. In this example, the time required to execute the calculation is 3 machine cycles.

FIG. 2 shows a case where the mask bits are set alternately, and the A1, A2 operation and the M1, M2 operation appear alternately. Here, M1 and M2 can originally be executed in one machine cycle, but due to the wait signal e of the A1 and A2 operations being executed in parallel, a waiting time as shown by diagonal lines occurs, resulting in three cycles.

In such a case, the processing efficiency is the same as in FIG. 2a. However, FIG. 2C shows the case where the mask bits are set continuously, and Ml, which is completed in only one machine cycle,
Only the M2 operation is repeated. In such a case, processing efficiency is greatly improved. In actual processing, the second
There are not many situations in which masks are alternately masked as shown in the figure, and either a or C is often continuous, so
According to the present invention, it is possible to improve processing efficiency and yield.

[Effect of the Invention 1] As explained above, if there is a masked vector arithmetic processing device to which the present invention is applied, an arithmetic vibe line in which stages of an operation requiring multiple machine cycles are performed for one step of a microinstruction are performed. In the present invention, it is possible to avoid the execution of arithmetic at the time of masking1, and when mask bits are consecutive, processing can be performed at high speed, making it possible to extremely increase processing efficiency.

[Brief explanation of drawings]

FIG. 1 is a schematic block diagram of the main parts of a masked vector calculation device according to an embodiment of the present invention, FIG. 2 is a conceptual diagram of the operation in the same embodiment, and FIG. 3 is a conventional masked vector calculation device. FIG. 2 is a schematic block diagram of main parts of a processing device. 1...Microprogram control unit 23...Intermediate operation result practical pipeline register 24...
...Second stage arithmetic circuit 25...Output driver circuit 26...First stage arithmetic unit control circuit 27...Arithmetic υ control pipeline register 28...Second stage arithmetic control circuit 29 ...Conventional calculation! 11 control circuit 3... masked vector 1lJt11 circuit 31...
Buffer 7 register 32... Pipeline register 3 for operand data
3...Output driver circuit 34...1st stage mask! 11 control circuit 35...
- Vibration line register 36 for mask tnltl information -
...Second stage mask control circuit 37...Shift register (conventional) 38...Mass 911111 circuit (conventional) 4...Shift registers A, B...Input data path S...Output data bus MI...Microinstruction bus e...Microinstruction wait logic circuit f...Mask bit

Claims (1)

[Claims] (1) Array operand to perform vector operation
A shift register that holds a bit string of mask bits assigned to each operand data that controls whether or not to execute an operation, and sequentially outputs the first mask bit to the microinstruction bus, and multiple machine cycles. At each stage of the arithmetic pipeline to be executed, according to the mask bit from the shift register, when the arithmetic operation is executed at that stage, a wait logic signal of the microprogram that controls the entire vector arithmetic process is outputted, and this is done in one program step. an arithmetic control unit that minimizes processing time by avoiding execution of an arithmetic operation when masking an arithmetic operation; 1. A masked vector arithmetic processing device, comprising: a masked vector control section that controls input/output timing of a register that holds data;