JPS63241468A - Offset voltage correcting circuit - Google Patents

Abstract

PURPOSE:To shorten a set ring time with slight chip area by providing a comparator, a detecting circuit, an up-down counter, etc. CONSTITUTION:When an input signal has no offset voltage, the peak value of the input signal exceeds comparison voltages Vcp1 and Vcp2 on the positive and negative side, so no offset voltage detection signal from the detecting circuit is detected and a 1-level output signal is outputted. Further, when the input signal has an offset voltage on the positive side, the up-down counter 25 is made to count up with the offset voltage detection output signal from the circuit 24, and the capacity value of a capacitor Ccp1 is increased. Consequently, the voltages Vcp1 and Vcp2 are shifted to the positive side. Further, when the input signal has an offset voltage on the negative side, only the output of a comparator 21 becomes 1, so the circuit 24 outputs a signal to make the counter 25 count down. Consequently, the capacity value of the capacitor Ccp1 is decreased and the voltages Vcp1 and Vcp2 are shifted to the negative side. Thus, the value of the counter 25 is increased or decreased to shift the comparison voltages, thereby correcting the offset voltage value.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to an offset voltage correction circuit, and particularly to an offset voltage correction circuit used in a comparator that utilizes charging and discharging of charge to a capacitor.

(Prior Art) FIG. 4 shows an example of a conventional offset voltage correction circuit. This circuit is described in the literature (IEEE.

J ounal of'5olid'-5tat
e circuits, vol.
1[i.

No. 4, August 1981-P 317
), the offset correction circuit 12 detects the offset voltage included in the output from the comparator 11, and applies the voltage value according to the detection result to the bypass filter 1.
The offset voltage of the comparator 11 is corrected by feeding back to the comparator 11.

The offset voltage correction circuit 12 includes an integrating circuit 12a having a large time constant and consisting of a capacitor CI and current source switches 5csi and 5cs2, and current source switches 5csi and 5cs.
A switch control circuit 12 that controls each of the two switches.
b, and a buffer amplifier 12c.

When the output of the comparator 11 is "L", the current source switch 5c
When si is on, 5cs2 is off, capacitor C1 is charged, and the output of comparator 1 is "H", 5cs2 is off.
cs2 is turned on and 5csi is turned off to discharge the charge in the capacitor CI. The offset voltage is corrected by feeding back the voltage integrated by the capacitor C1 to the bypass filter 13 via the buffer amplifier 12c.

However, in this offset voltage correction circuit using an integrating circuit, it is necessary to increase the time constant of the integrating circuit in order to prevent the influence of noise contained in the input signal, so the capacitance value of capacitor C1 is very large. Become something. This results in an increase in chip area, and there are cases where only the integrating circuit has to be formed on a separate chip.

Furthermore, increasing the time constant of the integrating circuit as described above has the disadvantage that the settling time required for the offset voltage correction circuit to operate stably increases.

(Problems to be Solved by the Invention) This invention was made in view of the above points, and the conventional offset voltage correction circuit requires an integrating circuit with a large time constant, which increases the chip area. In addition, setting a large time constant in this way improves the long settling time, prevents the influence of noise contained in the input signal, and shortens the settling time with a small chip area. An object of the present invention is to provide an offset voltage correction circuit.

[Configuration of the Invention (Means for Solving the Problems)] The offset voltage correction circuit according to the present invention includes a first comparison voltage generation means for generating a first comparison voltage on the positive side; a first comparison detection unit that compares a comparison voltage with an input signal voltage, detects that the positive peak value of the input signal exceeds the first comparison voltage value, and outputs a first detection signal; means for generating a negative second comparison voltage;
compares the second comparison voltage and the input signal voltage, detects that the negative peak value of the input signal exceeds the second comparison voltage value, and generates a second comparison voltage. a second comparison detection means for outputting a detection signal; and in response to the comparison results of the first and second comparison detection means,
when the detection signal is supplied and the second detection signal is not supplied, controlling the first and second comparison voltage generation means to shift the values of the first and second comparison voltages in the positive direction, respectively. , the second detection signal is supplied to the first detection signal.
and a comparison voltage control means for controlling the first and second comparison voltage generation means to shift the values of the first and second comparison voltages in the negative direction, respectively, when the detection signal is not supplied. It is.

(Function) In the offset voltage correction circuit having the above configuration, the first comparison detection means detects whether the positive side level of the input signal is higher than the first comparison voltage, and The second comparison detection means detects whether the level of the negative side of the input signal is higher than the second comparison voltage.

Therefore, if one of them is detected and the other is not, a positive or negative offset voltage will exist in the input signal, and the first and second comparison voltages will be adjusted accordingly. The offset of the input signal can be corrected by shifting the value in the positive direction or in the negative direction by the comparison voltage control means.

(Example) Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 shows an offset voltage correction circuit according to an embodiment of the present invention. This circuit includes a comparator 20 for detecting the positive level of an input signal, and a comparator 20 for detecting the negative level of the input signal. A comparator 21 is provided.

The comparator 20 includes an operational amplifier 20a whose non-inverting input (+) is connected to the ground potential VGND, capacitors Csll and Ccpl whose one electrode is connected to the inverting input (-) of the operational amplifier 20a, and the operational amplifier 20a.
It is a clock-type comparator that is switch-controlled by clocks φ1 and φ2 that have different phases, and is equipped with an inverter I2 connected to the output of the capacitor Cs.
Due to the capacitance ratio between 1'L and the variable capacitor Ccpl, the comparison voltage V cpl is 1 Vcpl = Ccpl (Vdd-Vss) /Cs
It is given in 1 liter.

Here, (V dd -V ss) is the amplitude value of the clock φ2 supplied to the other electrode of the capacitor Ccpl via the inverter 1. When the value of the input signal supplied to the other electrode of the capacitor CsiL becomes greater than this comparison voltage Vcpl, a signal at the "1" level is output from the comparator 20 as a positive detection signal.

Similarly, the comparator 21 includes an operational amplifier 21a whose non-inverting input (+) is connected to ground 7u VGND, and capacitors Csi2 and Ccp2 whose one electrodes are respectively connected to the inverting input (-) of the operational amplifier 21a. Equipped with
It is a chopper-type comparator that is switch-controlled by clocks φ1 and φ2 that have different phases, and the capacitor C
Due to the capacitance ratio between s12 and variable capacitor Ccp2, the comparison voltage V cp2 is Vcp2 = −Ccp2 (Vdd −Vss)
/ Cs12.

Here, (V dd -V ss) is the capacitor Ccp
This is the amplitude value of the clock φ2 supplied to the other electrode of φ2. The value of the input signal supplied from this comparator 21 to the other electrode of the capacitor Cs12 is the comparison voltage V cp2
s1'' level is output as a negative side detection signal.

Therefore, if the values of Vcpl and Vcp2 are set so that the comparators 20 and 21 output detection signals of "1" level when there is no offset voltage in the input signal, there is no offset voltage. Only one of the comparators 20 and 21 outputs "1".

At the next stage of the comparators 20 and 21, there are latch circuits 22 and 22, respectively.
23 are provided, and these latch circuits each latch the detection signal from the corresponding comparator and output it to the detection circuit 24.

The detection circuit 24 detects the respective outputs from the latch circuits 22 and 23, and when both of these outputs are "1", the output is "1".
Outputs a 1" level output signal and uses Usochi circuit 22.2
If the outputs from 3 are different from each other, an offset l-fQ output multiplication signal is output to the up/down counter 25 to increase or decrease the count value.

For example, if the output of the latch circuit 22 is "1", the latch circuit 22
3 is "0", the value of the up/down counter 25 is counted up, thereby increasing the capacitance value of the variable capacitor Ccpl and decreasing the capacitance value of the variable capacitor Ccp2. Also, the output of the latch circuit 22 is “0”.
When the output of the latch circuit 23 is "1", the value of the up/down counter 25 is counted down, thereby decreasing the capacitance value of the variable capacitor Capt and increasing the capacitance value of Ccp2.

Next, the operation of the offset voltage correction circuit having the above configuration will be explained with reference to FIG.

As shown in FIG. 2(A), when there is no offset voltage in the input signal, the peak value of the input signal exceeds the comparison voltages Vcpl and Vcp2 on the positive and negative sides, so the detection circuit 24 In this case, the offset voltage detection signal is not detected and a "1" level output signal is output.

Further, as shown in FIG. 2(B), when the input signal has a positive offset voltage, the offset voltage detection signal from the detection circuit 24 causes the up/down counter 2
5 is counted up, the capacitance value of capacitor Ccpl is increased, and the capacitance value of Ccp2 is decreased. As a result, the comparison voltages V cpl and V cp2 are as shown in FIG. 2 (C
) are shifted to the positive side, respectively.

Furthermore, if the input signal has a negative offset voltage as shown in FIG. is output, and the value of the up/down counter 25 is counted down.

As a result, the capacitance value of the capacitor Ccpl is reduced,
The capacitance value of Ccp2 is increased, and the comparison voltage VcpL,
Vcp2 is shifted to the negative side as shown in FIG. 2(E).

In this way, in this offset voltage correction circuit,
The voltage value of the offset voltage is corrected by determining the polarity of the offset voltage of the input signal in one cycle and increasing or decreasing the value of the up/down counter 25 based on the determination result and shifting the comparison voltage. Therefore, unlike the conventional offset voltage correction circuit shown in FIG. 4, there is no need to provide an integrating circuit with a large time constant, and the chip area can be reduced.

Furthermore, in this circuit, the offset voltage value can be sequentially decreased for each cycle of the input signal, so that the settling time from when the system reset is released until stable operation is performed can be shortened.

FIG. 3 shows an example of a specific configuration of the detection circuit 24, in which the positive detection signal from the latch circuit 22 is sent to an AND gate 31, an EXOR gate 32, and an AND gate 3.
3, and the negative side detection signal from the latch circuit 23 is supplied to the other inputs of the AND gate 31 and the EXOR gate 32, respectively.
It is supplied to one input of D gate 34. And A.N.
The other input of D gates 33 and 34 is EXOR gate 3.
2 outputs are supplied, and from the AND gate 33, the up
An offset voltage detection signal for counting up the down counter 25 is output, and an offset voltage detection signal for counting down the up φ down counter 25 is output from the AND gate 34. Also, AND
The output of the gate 31 becomes the output voltage when there is no offset voltage.

Since the presence or absence of the offset voltage is detected in this way, the offset voltage can be corrected by controlling the comparison voltage of the input signal based on the count level of the up-down power output.

[Effects of the Invention] As described above, according to the present invention, there is no need for an integrating circuit, so that it can be formed with a small chip area, and the settling time can be shortened.

[Brief explanation of drawings]

FIG. 1 is a block diagram illustrating an offset voltage correction circuit according to an embodiment of the present invention, FIG. 2 is a diagram illustrating the operation of the offset voltage correction circuit shown in FIG. 1, and FIG. A logic circuit diagram showing an example of a specific configuration of an offset voltage detection circuit provided in the offset voltage correction circuit shown in FIG. 1, and FIG. 4 is a circuit diagram illustrating a conventional offset voltage correction circuit. Cs1l, C5j2-...capacitor, Ccpl
, Ccp2... variable capacitance capacitor, 20
．． 21... Comparator, 22° 23... Latch circuit, 2
4...Detection circuit, 25...Up/down counter. Applicant's representative Patent attorney Takehiko Suzue Figure 1 (A) Figure 2, Figure 2, Figure 3, Figure 4

Claims (2)

[Claims] (1) A first comparison voltage generation means that generates a first comparison voltage on the positive side, and compares the first comparison voltage and an input signal voltage, and a peak value on the positive side of the input signal is determined as a peak value of the first comparison voltage on the positive side. a first comparison detection means for detecting that the first comparison voltage value has been exceeded and outputting a first detection signal; a second comparison voltage generation means for generating a second comparison voltage on the negative side; a second comparison voltage that compares a second comparison voltage with the input signal voltage, detects that a negative peak value of the input signal exceeds the second comparison voltage value, and outputs a second detection signal; and in response to the comparison results of the first and second comparison and detection means, when the first detection signal is supplied and the second detection signal is not supplied, the first and second detection means controls the comparison voltage generation means of the first and second comparison voltages in the positive direction, and when the second detection signal is supplied and the first detection signal is not supplied, the first and second comparison voltages are shifted in the positive direction. 1
and comparison voltage control means for controlling the second comparison voltage generation means to shift the values of the first and second comparison voltages in the negative direction. (2) The offset voltage correction circuit according to claim 1, wherein the comparison detection operation by the first and second comparison detection means is performed in units of one cycle of the input signal.