JPS63234673A - Phase locked loop circuit - Google Patents

Abstract

PURPOSE:To reduce the converging time to a synchronizing state after the vertical synchronizing period by switching a time constant of a loop filter so as to quicken the acquisition speed of synchronism for a prescribed period after the phase locked loop is switched from the open state into the closed state and providing a means switching the acquisition speed of synchronism for the phase clocked loop adaptively. CONSTITUTION:A switch 17 is controlled by an output from a timing generating circuit 16 and a loop filter 19 is used for a prescribed period. The time constant of the loop filter 19 is set smaller than the time constant of the loop filter 18. Thus, the acquisition speed of synchronism is faster in using the loop filter 18. Thus, when a prescribed period elapses, the switch 17 is restored and the loop is switched into the state using the loop filter 18. Thus, the phase error caused in the vertical synchronizing period is decreased quickly and till a line superimposed with a character signal or the like comes, the state is converged into the phase lock state.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a phase-locked loop circuit that is phase-locked to a horizontal synchronizing signal of a television signal.

(Prior Art) FIG. 4 shows a block diagram of a conventional phase-locked loop (hereinafter referred to as PLL) circuit used as a television horizontal synchronization signal generation circuit. This PLL circuit includes a synchronous separation circuit 11 a phase comparison circuit 2. DC amplifier 3. Voltage controlled oscillator (
(hereinafter referred to as VCO) 4 and frequency divider circuit 5. It is composed of a loop filter 8. The synchronization separation circuit 1 separates a horizontal synchronization signal from the input composite video signal and supplies it to the phase comparison circuit 2. The phase comparison circuit 2 compares the phases of the clock frequency division signal (FIG. 3(B)) which is the output of the frequency dividing circuit 5 and the horizontal synchronization signal (FIG. 3(A)) which is the output of the synchronization separation circuit 1. , outputs a phase error signal (FIG. 3(C)). This error signal is guided to the DC amplifier 3 via the loop filter 8, and is
Controls the oscillation frequency of CO4.

In the vertical flyback period of the composite video signal, there are equalization pulses and vertical synchronization pulses, and the period of these pulses is 1/2 that of the horizontal synchronization signal. Therefore, during this period, it is common to open the loop of the PLL circuit without performing phase comparison.

However, in an actual circuit, during the open loop period, the charge accumulated in the loop filter 8 decreases due to collector-base leakage current or forward base current of the transistor, and
The control voltage applied to CO4 changes. Next, after the equalization period and the vertical synchronization period, when the loop is closed again, the phase difference between the input horizontal synchronization signal and the clock frequency division signal has increased during the above-mentioned period, so the phase difference between the input horizontal synchronization signal and the clock division signal has increased, so that In this case, the phase of the input signal is changed by a step response, and the loop system operates to absorb this step phase error. At this time, if the filter time constant is small, the synchronization pull-in time will be shortened, but the phase change in the synchronized state will be large. As a result, phase fluctuations increase in the horizontal period, and in a video processing system that operates using the output of the VCO 4 as a basic clock, various problems occur, such as different sampling intervals on the left and right sides of the television screen.

In addition, in the text multiplex processing circuit that captures and decodes the teletext signal superimposed on the vertical blanking period of the television signal, the phase shift after the vertical mask period is synchronized by the time the line on which the text multiplex signal is superimposed arrives. There is a need. Therefore, it is necessary to set the loop filter time constant in accordance with the conditions, but this has the disadvantage that the noise band of the loop filter 8 is widened, and the jitter of the PLL circuit increases when the electric field is weak in the synchronized state.

(Problems to be Solved by the Invention) As described above, in the PLL circuit according to the prior art, for example, when capturing a character multiplex signal superimposed in the vertical retrace period, the phase error of the loop occurring in the vertical synchronization period is It is necessary to synchronize within time, but for that purpose the loop filter 8
If the time constant of is made small, the noise band becomes wider, the jitter of the PLL circuit increases in the case of a weak electric field, and the phase error in horizontal synchronization also increases.

Therefore, the present invention provides a phase-locked loop circuit that can shorten the pull-in time for the phase error that occurs during the vertical synchronization period, and can also suppress phase fluctuations within the horizontal synchronization. The purpose is to provide.

[Structure of the Invention] (Means for Solving the Problems) In the present invention, the time constant of the loop filter is adjusted to increase the pull-in speed for a certain period of time after the phase-locked loop switches from the open state to the closed state. means for adaptively switching the synchronization pull-in speed of the phase-locked loop.

(Function) With the above means, when the phase-locked loop is in an open state, that is, the phase error that occurs during the vertical mask period is converged in a short time, and outside of this period, the filter is switched to a filter with a large time constant. In periods other than the retrace period, phase fluctuations within the horizontal period can be reduced.

(Example of the invention) Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of the present invention, in which an input composite video signal is input to a sync separation circuit 11 via an input terminal 10. The synchronization separation circuit 11 separates a horizontal synchronization signal from the input composite video signal and supplies it to the phase comparison circuit 12. The phase comparison circuit 12 compares the phases of the lock frequency division signal (FIG. 3(B)) which is the output of the frequency dividing circuit 15 and the horizontal synchronization signal (FIG. 3(A)) which is the output of the synchronization separation circuit 1. A phase error signal (FIG. 3(C)) is output. This error signal is guided to the DC amplifier 13 via the loop filter 18.

Controls the oscillation frequency of VCOI°4.

In the vertical flyback period of the composite video signal, there are equalization pulses and vertical synchronization pulses, and the period of these pulses is 1/2 that of the horizontal synchronization signal. Therefore, during this period, phase comparison is not performed and the loop of the PLL circuit is opened. This control is performed, for example, by the output of a timing generation circuit 16 that generates various timing signals using the synchronization signal from the synchronization separation circuit 11.

By the way, the period when the phase-locked loop is open is
The charge accumulated in the loop filter 18 decreases due to collector-base leakage current or forward base current of the transistor, and the control voltage applied to the VCO 14 changes. Next, after the equalization period and the vertical synchronization period, when the loop is closed again, the phase difference between the input horizontal synchronization signal and the clock division signal increases for the period described above, so that the loop is closed. At this point, the phase of the input signal changes as if by a step response, and the loop system operates to subtract this step phase error.

Here, in the present invention, the switch 17 is controlled by the output from the timing generation circuit 16, and the loop filter 19 is used for a certain period of time. The time constant of this loop filter 19 is set smaller than the time constant of the loop filter 18. Therefore, the synchronous retraction speed is
It also becomes faster when using the loop filter 18.

Then, after a certain period of time has elapsed, the switch 17 is reset and the loop is switched to a state in which the loop filter 18 is used.

FIG. 2 shows the relationship between the switching timing of the loop filters 18 and 19 and the input composite video signal. In other words, (a) in the figure shows the input composite video signal, and (b) in the figure shows the mask signal obtained from the timing generation circuit 16. During the low level period (vertical synchronization period), the phase comparator 12 operates. is stopped and the phase-locked loop is opened, and during the period when the mask signal is at a high level, the phase-locked loop is closed. (0) in the same figure is a switching signal. During the period when this signal is at a high level, the loop filter 18 is used, and during the period when this signal is at a low level, the loop filter 18 is used.
9 is used.

As a result, the loop filter 19 with a small time constant is used for a certain period after the vertical synchronization period, so that the phase error occurring during the vertical synchronization period can be quickly reduced, and for example, a line on which a character signal is superimposed can be It is possible to converge to a phase-locked state until this occurs. On the other hand, in other periods, the loop filter 18 is used, so 1
It is possible to reduce the phase error within the horizontal period, and reduce jitter and the like during a weak electric field in a synchronized state.

In the above example, two loop filters were shown, but
In short, any filter whose time constant can be switched by a switching signal may be used.

[Effects of the Invention] As described above, the present invention can provide a phase-locked loop circuit with small phase fluctuations within the horizontal period and short convergence time to the synchronized state after the vertical synchronization period.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a timing chart for explaining the operation of the circuit in FIG. 1, and FIG. 3 is a timing chart for explaining the basic operation of the phase-locked loop circuit. The signal waveform diagram in FIG. 4 is a diagram showing a conventional phase-locked loop circuit. 11...Synchronization separation circuit, 12...Phase comparison circuit,"
°1'3... DC amplifier, 14... Voltage controlled oscillator, 15... Frequency dividing circuit, 16... Timing generation circuit, 17... Switch, 18.19... Loop filter.

Claims (1)

[Claims] a synchronization separation circuit that separates a horizontal synchronization signal from an input composite video signal; a phase comparison circuit that compares the phases of the horizontal synchronization signal and a frequency-divided output from a voltage controlled oscillator to obtain a phase error signal; A phase-locked loop circuit comprising means for supplying a control signal to an oscillation frequency control terminal of the voltage-controlled oscillator via a loop filter, wherein a plurality of timing signals synchronized with the periodic signal separated by the synchronization separation circuit are provided. A timing generation circuit that generates
means for stopping the operation of the phase comparator circuit and opening the phase lock rope only during the vertical synchronization period by a mask signal from the timing generation circuit; and means for switching the time constant of the loop filter to a time constant smaller than other periods using a switching signal.