JPS63234336A - Information processor - Google Patents

Abstract

PURPOSE:To prevent the deterioration of performance of an information processor by comparing the boundary address between a specified region and another region within a main storage device with a main memory access address and suppressing the reference and the updating of a cache memory when the result of said comparison shows a specified region. CONSTITUTION:A boundary register 11 shows the boundary between a region used exclusively by an exclusive processor and another region within the main storage device. A boundary comparator 12 compares the contents of an address register 10 which holds the main memory access address given from a requester with the contents of the register 11. When the result of said comparison shows the region which is exclusively used by an exclusive processor, a cache control circuit 13 suppresses the updating of a cache memory, i.e., the address arrays 15 and 16 and the data arrays 19 and 20. Thus it is possible to avoid such a case where the invalid data is fetched into the cache memory and the necessary data is driven out. As a result, the deterioration of performance is avoided for an information processor.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information processing device including a cache memory.

[Conventional technology]

Conventionally, this type of information processing apparatus always referred to and updated the cache memory when accessing the main memory. That is, when reading.

Check whether the data has been registered in the cache memory, and if it has been registered, retrieve the data from the cache memory. on the other hand,
If not already registered, if the cache memory has multiple compartments.

\t/ LRU
t) method, the compartment to be replaced is determined, the data is retrieved from one main storage device, and the data is sent to the request source, and the data is also written to the cache memory in preparation for subsequent reading.

[Problem that the invention seeks to solve]

In the conventional information processing apparatus described above, in the case of a system including a cashier memo storage 2 that stores all data read from the main storage, and a main storage 6 that is accessed mainly from the dedicated processing apparatus 2.

The main storage device 6 is almost never accessed from the information processing device 1. Therefore, if the data in the main storage device 6 is unnecessarily stored in the cache memory in the information processing device 1, it will result in a loss of time. As a result, there was a drawback that the performance of the information processing device 1 deteriorated.

This situation is the same in the case of a system that has one main storage device and is internally divided into two areas, as shown in FIG.

[Means for solving problems]

An information processing device according to the present invention includes a boundary register in which a boundary address of a main memory can be set in advance, an address register that holds addresses for accessing the main memory and the cache memory, and a main memory. Boundary comparing means for comparing the contents of the boundary register and a part of the address register at the time of a storage device access request, and inhibiting cache memory reference and updating depending on the comparison result of the boundary comparing means. The carriage control circuit is characterized in that it has a carriage control circuit that controls whether or not the carriage is carried out.

〔Example〕

Two embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

In FIG. 1, 10 is an address register that holds the main memory access address from the request source.

Reference numeral 11 denotes a boundary register which holds a boundary address between a portion of the main memory that is accessed exclusively by the dedicated processing unit 2 and other portions, which can be set using a conventionally known method. Reference numeral 12 denotes a boundary comparison circuit that compares the contents of the boundary register 11 and the contents of the upper register 6-1 of the address register 10. 13 is a cache control circuit. Reference numerals 15 and 16 are address arrays, which together with address array comparison circuits 17 and 18 indicate which part of the main memory is stored in data arrays 19 and 20. A data switching circuit 21 is used in this embodiment to switch between the data array output of the two compartments and the output of the system control device 3, and to send desired data to the request source.

FIG. 2 is a diagram showing the arrangement of the main storage device 5 in this embodiment. In the figure, the area 52 used exclusively by the dedicated processing device 2 is located at the lower level, but the reverse may be possible.

Next, the operation of this embodiment will be explained in detail.

First, the main memory access address from the request source is sent together with a request signal, and the address register 10
is set to The lower part of the output of the address register 10 is 9. In this embodiment, the cache memory is composed of two compartments, so the two address arrays 15 are
．． 16 and data arrays 19 and 20 via address lines 100. Furthermore, address register 10
The upper part of is connected via address line 103 to one input of address array comparison circuit 17,18. The other inputs of the address array ratio pruning circuits 17 and 18 are connected to the read data of the entries designated by the two address arrays 15 and 1607 address lines 100, respectively. The outputs of the address array comparison circuits 17 and 18 are signals indicating whether the requested main memory information is included in the data arrays 19 and 20, and are sent to the cache control circuit 13 via signal lines 101 and 102, respectively. is input.

On the other hand, the upper part of the address register 10 is also connected to one input of the boundary comparison circuit 12 via an address line 104. Note that the address information sent from the address register 10 to the boundary comparison circuit 12 is different from the address information sent to the address array comparison circuits 17 and 18, and is only the upper part. Boundary comparison circuit 12
Other inputs include the boundary between the main memory area 52 used exclusively by the dedicated processing unit 2 and the other portion 51 on the main memory 5 from the boundary register 11, which can be set using a known method. Address information shown is connected via address line 105.

The boundary comparison circuit 12 compares the magnitude relationship between the address information input via the upper address line 104 of the address register 10 and the address information input from the boundary register 11 via the address line 105. That is,
The boundary comparison circuit 12 exclusively uses a dedicated processing device when the address information inputted via the upper address line 104 of the address register 10 is greater than or equal to the address information inputted from the boundary register 11 via the address line 105. 2 indicates accessing the area 52 used by
When the cache control circuit 13 generates a signal indicating that another area 51 is to be accessed when the
Send to.

In the cache control circuit 13, when a main memory access request is made,
Data array 1 sent via signal lines 101.102
9. Test the signal indicating whether the desired data is present at 20. Cache control circuit 13 generates a data switching signal and sends it to data switching circuit 21 via signal line 110 when either of the two signals indicates that desired data is present in data array 19 or 20.

The outputs of the data arrays 19 and 20 are input to the data switching circuit 21 via data lines 108 and 109, respectively. The data is switched and sent to the requester. When none of the signals from signals 1101.102 indicate that the desired data is not present in data array 19.20, cache control circuit 1
3 issues a main memory access request to the system control device 3 via the signal line 107. Note that when the main memory access address points to the area 52 exclusively used by the dedicated processing device 2, a main memory access request is necessarily issued to the system control device 3. As will be explained later, the area 52 exclusively used by the dedicated processing device 2 is a cache memory or address array 15, 16 . This is because it is not loaded into the data array 19-20.

Read data is transferred from the system control device 3 to the data line 111
When the data is returned via the signal line 110, the cache control circuit 13 instructs the data switching circuit 21 to output the read data from the system control device 3 via the signal line 110.

When the output of the boundary comparison circuit 12 input to the cache control circuit 13 via the signal line 106 indicates that the main memory access address points to an area 51 other than the area exclusively used by the dedicated processing device 2, a predetermined A compartment to be updated is determined by a conventionally known method, and the upper part of the address information in the address register 10 sent via the address line 103 is stored in the address array 15 or 16 when a request is issued to the system control device 3.

When main memory read data is received from the system control device 3, the main memory read data is sent to the request source and stored in the data array 19 or 20 via the data line 111. Conversely, the cache control circuit 13 via the signal line 106
When the output of the boundary comparator circuit 12 inputted to indicates that the main memory access address points to the area 52 used exclusively by the dedicated processing unit, updating of the address array 15.16 and the data array 19.20 is inhibited. .

〔Effect of the invention〕

As described above, the present invention provides a boundary register that holds the boundary address between an area exclusively used by the dedicated processing unit and other areas in the main memory.

The content of part of the main memory access address from the request source is compared with the content of this boundary register, and when the comparison result indicates that the area is exclusively used by the dedicated processing unit, the cache memory is referenced and updated. Because it is suppressed,
This prevents invalid data from being taken into the cache memory and essentially necessary data from being evicted, which has the effect of preventing performance degradation.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the main part configuration of an embodiment of the present invention, FIG. 2 is a layout diagram of the main storage device in this embodiment, and FIG.
4 and 4 are block diagrams showing the configuration of an information processing system to which this embodiment is applied. 1... Information processing device, 2... Dedicated processing device, 3...
- System control device, 5... Main storage device, 10...
Address register, 11... Boundary register, 12...
・Boundary comparison circuit, 13... Catch-control circuit, 15
．． 16...Address array, 17.18...Address array comparison circuit, 19.20...Data array, 2
1...Data switching circuit;

Claims (1)

[Claims] 1. In an information processing device including a cache memory, a boundary register in which a boundary address of the main memory can be set in advance, an address register that holds an address for accessing the main memory and the cache memory, and a main memory when an access request is made; Boundary comparison means for comparing the contents of the boundary register and the contents of a portion of the address register;
An information processing apparatus comprising: a cache control circuit that controls whether or not to suppress references and updates to a cache memory depending on a comparison result of the boundary comparison means.