JPH02108138A - Cache memory circuit - Google Patents

Abstract

PURPOSE:To eliminate the wait time of a processor by providing 1st and 2nd buffer means between a processor data and a cache memory data bus. CONSTITUTION:The 1st and 2nd buffer means 7 and 8 are connected in series between the processor 1 and a main storage device 3 connected to a system bus 6 which is (n) times as wide as the data bus, and a cache memory 2 is connected to the connection point between the 1st and 2nd buffer means 7 and 8. Thus, the 1st and 2nd buffer means 7 and 8 are provided, and consequently even if data are transferred from, for example, a main storage device 3 to the cache memory 2 through the 2nd buffer means 8, the processor 1 can access data in the 1st buffer means 7 at the same time. Consequently, the processor 1 has no time wait.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a cache memory circuit provided between a processor and a main memory.

[Prior Art] Conventionally, in order to speed up memory access, a small-capacity memory capable of high-speed operation called a cache memory has been used in addition to the main memory.

FIG. 4 shows the overall configuration of a general data processing system using a cache memory.

The processor 1 is connected to a system data bus 6 via a cache memory 2 and a buffer circuit 8, and a main storage device 3 and a secondary storage device 4 are connected to the system data bus 6. Data in address areas that are frequently accessed by the processor 1 is transferred to the cache memory 2 from the main storage device 3. In addition,
In the figure, a is the processor data bus width, and n is the system data bus width+processor data bus width.

When processor 1 tries to access a certain address, if that address is in cache memory 2,
In other words, when the cache is cached, the processor 1 directly accesses the cache memory 2, which enables high-speed operation. Furthermore, when the address that the user attempts to access is not in the cache memory 2, that is, when a cache miss occurs, the contents of the cache memory 2 are transferred to the main memory 3.
The data of the block including the address accessed by the processor 1 is newly transferred from the main memory 3 to the cache memory 2 via the buffer circuit 8. That is, the contents of cache memory 2 are replaced.

[Problem to be Solved by the Invention J] However, in the conventional cache memory circuit shown in FIG. 4, the cache memory 2 cannot be accessed from both the processor 1 and the main storage device 3 at the same time. Therefore, when data is being transferred from the main storage device 3 to the cache memory 2 for updating, the processor 1 has had to stop operating until the transfer is completed.

Furthermore, since the processor data bus width is a and the system data bus width is an, a circuit for matching the bus widths is also required. Note that although the processor data bus width is fixed for each processor, the system data bus width may be expanded as described above in order to improve the data transfer speed.

The present invention enables high-speed transfer from the main memory to the cache and conversion of the data bus width to update data in a cache memory circuit used in a computer system where the data bus widths of the main memory and processor are different. The purpose is to reduce the latency caused by the processor.

[Means for Solving the Problems 1] The cache memory circuit of the present invention includes first and second memory devices connected between a processor and a main storage device connected to a system data bus having a width n times that of the data bus of the processor. buffer means are connected in series, and a cache memory is connected to a connection point between the first and second buffer means.

The cache memory consists of n groups of data sections, the first buffer means consists of n groups of datum couches, and the n groups of data buses on the processor side of the n groups of data buffers are combined into one. It is preferable that the second buffer means divides the system bus into n groups in the bit width direction and connects each to the n groups of data buffers of the first buffer means. .

[Operation] In the present invention, since the first and second buffer means are provided, for example, even when data is being transferred from the main storage device to the cache memory via the second buffer means, The processors can access the data in the first buffer means simultaneously, and the processors do not have to wait.

[Example 1] Hereinafter, the features of the present invention will be specifically explained by examples with reference to the drawings.

FIG. 1 is a block diagram showing the basic configuration of a cache memory circuit according to an embodiment of the present invention. Note that the same reference numerals are given to the constituent elements and the like that correspond to those of the conventional example shown in FIG.

As shown in the figure, in the cache memory circuit of the embodiment, a processor data bus 5 to which a processor 1 is connected
Bidirectional first and second buffer circuits 7 and 8 are connected in series between the main storage device 3 and the system data bus 6 to which the main storage device 3 and secondary storage device 4 are connected. A cache memory 2 is connected to a connection point between both buffer circuits 7 and 8 via a cache data bus 31. Note that the data width of the system data bus 6 and the cache data bus 31 is n times the data width a of the processor data bus 5, and the buffer circuit 7 is composed of n sets of data buffers. Further, the cache memory 2 consists of n sets of data caches.

FIG. 2 shows the 1. 2 is a block diagram showing in detail the relationship between second buffer circuits 7, 8 and cache memory 2. FIG.

The figure shows an example in which the system data bus 6 is 32 bits and the processor data bus 5 is 8 bits, where n=4.

In the figure, 18 to 21 indicate first to fourth data buffers, respectively, and correspond to the first buffer circuit 7 as a whole. In addition, 10 to 13 are the first to fourth numbers, respectively.
This data cache corresponds to the cache memory 2 as a whole.

The system data bus 6 is divided into four parts each consisting of 8 bits starting from the upper bit, and the first buffer circuit 7 and the second buffer 8 are made up of four sets of 8-bit buffers, each connected one-to-one in 8-bit units. ing. The processor data bus 5 is 8 bits, and has first to fourth data buffers 18.
Each bit from L8B (least significant bit) to MSB (most significant bit) of .about.21 is connected to the processor 1. Also, by the decode signal of the lower two bits of processor 1,
One of the four data buffers 18-21 is selected. These decoded signals are the first to fourth buffer selection signals 27 to 30, and the selected data buffer is actively connected to the processor 1. The direction in which data flows in the data buffers 18 to 21 is read l.
It is determined by the write signal 9, and when reading, the cache memory 2 becomes the processor 1, and when writing, the processor 1 becomes the cache memory 2.

The bus switching signal 24 is a signal that determines the owner who accesses the cache memory 2, and switches the bus between the processor 1 and the bus master of the system data bus 6. Here, it is assumed that when the level is high, it becomes the bus master on the processor side, and when it is low, it becomes the bus master on the system side.

Further, the data cache address 22 is an address signal for accessing the cache memory 2, and is either the processor address 25 or the system address 26 selected by the bus switching signal 24. Note that the addresses 25 and 26 entered manually in the address selector 23 are 4
The lower two bits are not included because the blocks are accessed simultaneously.

Next, a description will be given of read and write operations when the cache memory hits and misses, respectively.

1) Cache hit l Read When the cache memory 2 is determined to be hit, the bus switching signal 24 becomes high level, the system data bus 6 and the cache data bus 31 are cut off by the buffer circuit 8, and the output of the address selector 23, that is, the data Cache address 22 becomes processor address 25.

According to the read/write signal 9, the direction of data in the first to fourth data buffers 18 to 21 is changed from the first to fourth cache data buses 14 to 17 to the processor data bus 5.
It will be in the direction of First to fourth data caches 10 to 1
3 outputs data at the given processor address 25. The data is stored in the first to fourth data buffers 18 to 2.
However, only the buffer selected by one of the first to fourth buffer selection signals 27 to 30 that becomes active after decoding the 2 bits of the lower address outputted by the processor 1 will process the processor data. Data is passed to processor 1 via bus 5, after which the bus cycle ends.

2) Write cache hit l Similarly to 1), the buffer circuit 8 is turned off, and the first to fourth
The processor address 25 of the processor 1 is given to the data caches 10 to 13 of the processor 1. The direction of the data in the first to fourth data buffers 18 to 21 is from the processor data bus 5 to the first to fourth cache data buses 14 to 17 by the read/write signal 9.

The first to fourth buffer selection signals 27 to 30, which are determined by the lower two bits of the processor address, become active.
~One buffer among the fourth data buffers 18 to 21 and the data cache on the same bus become active and data is written.

Note that in the write-through method, the first buffer circuit 8 also becomes active, and the contents of the main storage device 3 are also updated through the system data bus 6.

3) Cache miss When it is determined that the cache memory has missed, the bus switching signal 24 becomes low level, and the system data bus 6 and cache data bus 31 are set to a through state by the buffer circuit 8. The output 22 of the address selector 23 becomes the system address 26, which is a replacement address. The cache memory 2 then starts the replacement process.

In other words, in write-back processing, if there is a free area in the cache memory 2, no special processing is performed; if there is no free area, a certain block in the cache memory 2 is written back to the main storage device 3 to create a free area. Create an area. Note that there is no special write-through processing.

The address 26 to be replaced is given by an external controller, and is input to the first to fourth data caches 10 to 13 through the address selector 23.

After the replacement process is completed, the cache memory 2 is given the missed address value. Data to be updated flows in two directions: from the buffer circuit 8 to the cache memory 2, and from the buffer circuit 8 to the processor 1 through one of the first to fourth data buffers 18 to 21.
There are two streams. Due to the former flow, cache memory 2
The data containing the error can be passed to the processor 1 through the latter flow.

That is, in the cache memory 2, a block of 4 words including the miss word is enabled, and data is stored and updated in the cache memory 2 at a time. Furthermore, the amount of data that is 3 words larger than that requested by the processor 1 from the main memory device 3 comes to the first to fourth data buffers 18 to 21, but only the one word buffer determined by the lower two bits of the processor 1 is used. is enabled, and necessary data is input to processor 1.

4) Cache miss l write Similarly to 3), the system data bus 6 and cache data bus 31 are passed through by the buffer circuit 8. The cache memory 2 then starts the replacement process.

In other words, in write-back processing, cache memory 2
If there is a free area in the cache memory 2, no particular processing is performed; if there is no free area, a certain block in the cache memory 2 is written back to the main memory 3. Note that there is no special processing for write-through.

The address 26 to be replaced is given by an external controller, and is manually input to the first to fourth data caches 10 to 13 through the address selector 23. After the replacement process is completed, the cache memory 2 is given the missed address value. The direction in which updated data flows is
In write-back, there is a path from processor 1 to cache memory 2, and in write-through, there is a path from processor 1 to cache memory 2.
There are two paths: one path goes from there to the cache memory 2, and the other path goes to the system data bus 6 and also updates the main storage device 3. In the former flow, only the contents of the cache memory 2 are rewritten, and in the latter flow, the cache memory 2 and the main storage device 3 are rewritten.

Data output from processor 1 passes through one of the first to fourth four data buffers 18 to 21 determined by the lower two bits of processor Write to one of data caches 10-13. It also performs write-back and write-through processing.

In write-through, it is necessary to update the main memory device 3, but this means, for example, that the remaining three data caches that were not selected are read, and the second buffer circuit 8 updates the remaining three data caches.
One possible method is to prepare one word of data, that is, one word of processor data and three words of data cache output excluding one word selected by the processor, for a total of four words, and write them into the main memory 3.

FIG. 3 shows another embodiment of the present invention, in which the buffer circuits 18-21 in FIG. 2 are replaced with latch circuits 32-35, and the buffer selection signals 27-30 are replaced with latch selection signals 37-
Change it to 40. Further, an address latch 3 is used to indicate the address of data stored in the latch circuits 32 to 35.
6 is provided, and an address comparator 41 is added that inputs and compares the output of the address latch 36 and the address 25 currently being executed by the processor 1, and depending on the comparison result, that is, a match or a mismatch, the latch circuits 32 to 35 and the data cache 10 to
A gate 42 is provided to determine the operation of data cache 13, that is, to make the data caches 10 to 13 non-active if the comparison result is a match, and to make them active if there is a mismatch. With this configuration, the cache memory 2 and the latch circuits 32 to 32
This results in 35 multi-stage caches.

When reading, if the comparison results match, the cache memory 2
If one of the latch circuits 32 to 35 is accessed without accessing the
The cache memory 2 is accessed by skipping through 35, the data is passed to the processor 1, and the data is latched into the latch circuits 32 to 35 by the time the bus cycle ends.

During writing, the latch circuit 32 is activated regardless of hits or misses.
-35 are ignored and written to data caches 10-13.

[Effect of the Invention 1] As described above, in the present invention, the first and second buffers, which are composed of data buffers or latches, are provided between the processor data bus and the cache memory data bus.
A buffer means is provided. As a result, for example, if a cache memory miss occurs, the second
The processor can read and write data through the first buffer means while updating the cache memory through the first buffer means.

Therefore, the processor does not have to wait for a certain amount of time. Furthermore, since the bus width is converted at the same time as the data is transferred, the bus width can also be converted at high speed.

[Brief explanation of drawings]

FIG. 1 is a schematic block diagram of a cache memory circuit according to an embodiment of the present invention, FIG. 2 is a detailed block diagram of the same cache memory circuit, FIG. 3 is another embodiment of the present invention, and FIG. 4 is a conventional cache memory circuit. FIG. 2 is a block diagram of a memory. 1: Processor 2: Cache memory 3: Main storage device 4: Secondary storage device 5: Processor data bus 6: System data bus 7: First buffer circuit 8: M2 buffer circuit 9:
Read/write signals 10 to 13: 1st to 4th data caches 14 to 17
41~4th cache data bus 18~21:1g
1 to 4th data buffer 22: data cache address 23 near address selector 24: bus switching signal 26: system address 27 to 30: buffer selection signal 31: cache data bus 32 to 35: first to fourth launch circuit 36: Address latches 37-40: First to fourth launch selection signals 41 Near address comparator 42: Gate 25: Processor address

Claims (1)

[Claims] 1. First and second buffer means are connected in series between a processor and a main memory connected to a system data bus having a width n times that of the data bus of the processor; A cache memory circuit characterized in that a cache memory is connected to a connection point between the first and second buffer means. 2. The cache memory consists of n groups of data sections,
The first buffer means includes n groups of data buffers, the n groups of data buses on the processor side of the n groups of data buffers are combined into one and connected to the processor, and the second buffer means The cache memory circuit is characterized in that the system bus is divided into n groups in the bit width direction and each of the divided groups is connected to the n groups of data buffers of the first buffer means.