JPS6323250A - Phase servo circuit - Google Patents

Abstract

PURPOSE:To coincide vertical synchronizing phases with each other on a video track formed on a tape, near an editing point, by controlling the rotational phase of a rotary magnetic head by the output of a pulse width modulation circuit. CONSTITUTION:A phase difference correcting counter 24 counts a clock pulse having a prescribed frequency, and from the output of the counter 24, an output PEC having the same cycle as that of the output of a buffer counter 18 which accumulates a bit of phase servo information in a form of circulating phase, can be obtained. The output is supplied to the reset terminal of a flip-flop (FF)23 to form a pulse width modulation signal (DPPWM) through a gate circuit, and the resetting timing of the FF23 is changed corresponding to the circulating phase of the PEC counter 24. The circulating phase of the counter 24 can be changed by adjusting the number of supplied clocks corresponding to the phase difference between a vertical synchronizing signal REC-VD, and a reproduced vertical synchronizing signal PB-VD. In this way, the phase of the synchronizing signal of a recorded part on the video track, and that of a newly recorded video signal can be recorded unitedly.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a phase servo circuit, and is particularly suitable for application to a drum phase servo of a video signal recording and reproducing device equipped with an automatic editing function.

In helical scanning VTRs such as 2-head VTRs, 1-head VTRs, 1.5-head VTRs with auxiliary heads, etc., it is possible to insert or connect another video signal to a recorded magnetic tape or a partially recorded magnetic tape. Requires automatic editing functionality for recording. Conventionally, the arrangement of control signals on the tape and the phase of the synchronization signal on the video track are matched before and after the editing point to prevent the screen from being distorted at the editing point during playback.

Editing methods include "assemble" as shown in the track pattern on tape 1 in FIG. 1a and "insert" as shown in b. In the assemble mode, after the recording of one cut is completed, the signal of the next cut is recorded. In this mode, the full erase head works, erasing all previously recorded signals after the edit point, including the control signal (CT-L signal).
Record the video signal while writing the CTL signal. If the full erase head suddenly starts working at this time, it will erase even the necessary part of the recorded signal A.
The flying erase head is operated for a predetermined period of time as shown by the dotted line in FIG.

In insert mode, the B signal is inserted into the recorded A signal. In this mode, as shown in Figure 1,
The flying erase head erases the A signal (solid line) and then records the B signal (-dotted chain line), but does not erase the CTL signal.

In these assemble modes and insert modes,
Until the editing point is reached, the head drum servo of the editing machine is locked using the vertical synchronization signal of the B signal, and while the A signal is being played back, the tracking servo (capture) of the editing machine is locked using the PC pulse of the drum and the playback CTL signal. Stun servo). Therefore, record a new B before entering the editing point.
The alignment between the vertical synchronization signal and the CTL signal of the editing machine has been completed. After the editing point, when in the assemble mode, the editing machine switches to a recording mode for recording the B signal, and at this time, the capstan servo is usually only constant-speed servo. On the other hand, in the insert mode, only the head drum system is switched to the recording mode, and the capstan servo operates with the reproduction servo (tracking servo) applied by the CTL signal of the recorded A signal.

By doing this, before and after the edit point, CTL
We try to match the signal arrangement and the phase of the synchronization signal on the video trunk, but if the compatibility between the playback device and editing device for obtaining the B signal is not completely satisfied, or the drive system changes over time, etc. may not match completely.

That is, as shown in FIG. 2a, there is a phase shift Δ■ between the vertical synchronization signal ■ of the newly recorded video signal B and the vertical synchronization signal ■ of the already recorded video signal A. If this happens, the reproduced image will shift vertically before and after the editing point, making it difficult to see. In addition, as shown in FIG. 2, the video signal A,
If there is a phase shift ΔH in the horizontal synchronization signal H of B, the horizontal oscillation of the monitor device is disturbed at the editing point, causing so-called H skipping in which the image flows.

The present invention has been made in view of the above-mentioned problems, and it is possible to record (insert or assembly file)
The purpose is to make it possible.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 3 shows a drum servo system of a VTR to which the present invention is applicable. As shown in FIG. 3, magnetic heads 3A and 3B attached to a rotating drum are rotationally driven by a drum motor, tracks at a predetermined angle are formed on the magnetic tape 1, and video signals are recorded/reproduced. . A frequency generator 4 is attached to the rotating shaft of the drum motor 2, and its output is supplied to a speed servo circuit 5, where a reference signal R is supplied.
A speed error signal is formed based on EF. The speed error signal is supplied to the drive amplifier 7 through the adder 6, and the amplifier 7
The speed of the drum motor 2 is controlled by the output.

The rotational phases of the magnetic helads 3A and 3B are detected by the PG head 8, and the output PC signal is supplied to the phase servo circuit 9. The phase servo circuit 9 receives a vertical synchronizing signal REC-VD during recording, and an external reference signal X-VD during playback.
A VD or reproduction CTL signal or the like is supplied. Also, when editing tape in insert mode or assemble mode, the vertical synchronization signal REC-V of the video signal to be recorded is
D is supplied to the phase servo circuit 9 for phase matching with the recorded signal. The phase error signal obtained from the phase servo circuit 9 is added to the speed error signal in an adder 6, and then supplied to the drum motor 2 via a drive amplifier 7.

FIG. 4 shows a circuit diagram of the phase servo circuit 9 of FIG. 3 to which the present invention is applied. FIG. 5 is a time chart showing the target to be achieved by this servo circuit, and FIGS. 6 to 9 are waveform diagrams of each part of FIG. 4.

As shown in FIG. 5, the purpose of the phase servo circuit 9 is to maintain a predetermined phase difference φ between the output PC of the PG head 8 (FIG. 5a) and a predetermined reference signal REF (FIG. 5b). It is. This reference signal may be a vertical synchronization signal of a recorded video signal during recording, and may be an external reference synchronization signal, a reproduced vertical synchronization signal, or the like during reproduction.

In FIG. 4, the phase difference detection circuit 10 is shown surrounded by a dotted line, and the other part is an editing phase correction circuit 11 for correcting the recording phase during tape editing. Phase difference detection circuit 1
0, the phase difference with the PG multiplied signal reference signal REF in FIG. . Figure 4 Monomulti 1
3, 30H2 obtained from the output PC of the PC head 8
A PC pulse PGH (FIG. 6a) is supplied, and a signal PGHDL having a predetermined pulse width shown in FIG. 6 is obtained from the output of the monomulti 13. This signal sets flip-flop FF14. On the other hand, when the phase servo circuit of FIG. 4 operates in the recording mode, the vertical synchronizing signal REC-VD (FIG. 6C) of the video signal to be recorded is supplied to the delay counter 15 as the reference signal REF. Since the counter 15 counts a predetermined number of clock pulses TF6 of a predetermined frequency from the clock circuit 16, a signal VDL (FIG. 6d) delayed by a fixed amount is obtained from its output. The FF 14 is reset by this signal VDL.

A signal DPEB shown in FIG. 6e is obtained from the Q output of the FF 14. The pulse width of this signal is representative of the phase difference between the PC pulse PGH and the recording vertical synchronization signal. Note that the delay counter 15 is provided to simplify the counting operation and configuration of a phase detection counter, which will be described later. The output of FF14 is supplied to AND gate G1 as a strobe signal, and during its high level period, clock pulse TF6 passes through gate G1. ANDGATE G
The output of l passes through OR gate G2 to phase detection counter 1.
It is supplied to the clock terminal CK of No. 7.

The phase detection counter 17 may be, for example, 512-decimal,
When the pulse width of the signal DPEB representing the phase difference φ between the drum rotation phase and the recording synchronization signal is at the design standard value, 256 clock pulses TF6 are counted as shown by the thick line in FIG. The output DPC rises to a high level as shown in FIG. 6f. Therefore, the phase detection counter 17 accumulates a count value corresponding to the phase difference φ.

Note that when the PG pulse is delayed as shown by the dotted line in Figure 6a, the count value of the counter 17 is 256-'x (x: variable), and its MSB output is as shown in Figure 6f'. It remained at a low level at the end of the count. Further, when the PC pulse advances as shown by the dashed line in FIG. 6a, the count value of the counter 17 is 256+X, and the
The S B output rises at a count value of 256, as shown in FIG.

The phase information measured by the counter 17 is read out as follows and transferred to the buffer counter 18.

That is, the output DPEB of FF14 is the flip-flop FF.
19, and at its falling edge, FF 19 is set as shown in FIG. 6g. The Q output of FF19 is
Since it is supplied to the set input of flip-flop FF20, the clock TF12 (
At the timing shown in FIG. 6h), the FF 20 is set as shown in FIG. 6i. FF20 Q output D-TR3 is FF20
and is supplied to the reset input of FF19, so F
F19 is reset and FF2 is reset one clock later.
0 is reset as shown in FIG. 6i. Therefore TF12
A signal D-TR3 having a pulse width of one cycle is obtained from the FF 20.

The clock TF12 is formed by the clock circuit 16, and one cycle thereof, ie, the period in which the signal D-TR3 is at a high level, corresponds to the length of 512 clock pulses TF6. F
The output D-TR5 (data transfer pulse) of F20 is supplied to ANDG3 as a strobe pulse, so
Clock pulse CP from clock circuit 16 is applied to gate G
3, and is supplied to the clock terminal of the phase detection counter 17 through G2. As a result, the counter 17 starts counting again as shown by the thick line in FIG. 6f, and the stored count M (
The count value increases based on the phase information I[a). Therefore, the most significant bit output DPC of the counter 17 falls at a count value of 512 as shown in FIG. 6f.

The position of this fall is determined according to the previously measured phase information, as shown in FIG. 6 f, M, f''.

That is, information on the phase difference φ between the PG pulse and the recording synchronization signal is position-modulated and obtained as position information on the falling edge of the output of the counter 17.

The output of counter 17 is supplied to the reset input of buffer counter 18 through AND gate G4. The counter 18 is a 512-decimal counter and counts the clock pulses CP from the clock circuit 16. Therefore, the most significant bit output BC is equal to the count value 25 as shown in Figure 6j.
It is a pulse signal with a predetermined period, which becomes high level at 6 and returns to low level at 512. When the buffer counter 18 is reset by the output of the counter 17, the cyclic phase of the counter 18 is changed according to the phase information of the phase detection counter 17, as shown in FIG. 6j, and this cyclic phase remains until the next reset. Retained.

That is, the position information of the falling edge of the output of the counter 17 (r, r', f' in Fig. 6)! l(, is transferred to the counter 18 as shown in FIG. 6 Lj', js.

Since the output BC of the counter 18 is supplied to the set input of the flip-flop FF23, when the output BC falls, the FF23 is set as shown in FIG. When the phase servo system shown in Figure 4 operates in normal recording mode,
A reference timing signal, for example, the clock pulse TF12 shown in FIG. 6, is supplied to the reset input of the FF23.

Therefore, from the output of the FF 23, a signal DPPWM (indicated by ', k' in FIG. 6) which is pulse width modulated according to the phase difference φ between the PC pulse PGH and the recording synchronization signal REC-VD is obtained. Note that the timing signal TF12 can be obtained from a phase difference correction PEC counter 20, which will be described later. That is, by resetting the counter 20 with a predetermined timing signal when switching to the recording mode, a timing signal T with a predetermined phase and cycle is generated from the output of the counter 20.
F12 is obtained.

After being inverted, the pulse width modulated signal is converted to an analog level through a low-pass filter, and is then converted to an analog level by the adder 6 in FIG.
The output of the speed servo circuit 5 is added to the output of the speed servo circuit 5. Therefore, when the PC pulse is delayed as shown by the dotted line in FIG. 6a, the effective pulse width (low level portion) of the pulse width modulation signal becomes longer, resulting in the output of the phase servo circuit 9 in FIG. The phase error voltage increases and the speed of the drum motor 2 is increased. On the other hand, when the PG pulse is progressing as shown by the dashed line in FIG. 6A, the effective pulse width of the pulse width modulation signal becomes shorter, and as a result, the motor 2 is decelerated.

In this way, the phase of the PG pulse PG with respect to the recording vertical synchronization signal REC-VD, that is, the rotational phase of the head is fixed to the set value φ. This fixes the track on the tape on which the video signal is recorded at the correct position. Also, during playback, if the tracking servo is performed by a capstan, for example, the external vertical synchronization signal X-VD obtained from the reference frequency source (for example, the clock circuit 16 in Figure 4) is used as the reference signal for the drum phase servo. The signal REF is supplied to the phase difference detection circuit 10, and as in the case of recording,
As shown in Figure 5a and b, the PC pulse and the reference signal RFP
The phase servo circuit 9
works.

Next, the editing mode will be explained. In the editing mode, the recording vertical synchronizing signal REC--D is supplied to the phase difference detection circuit 10 of FIG. 4 as in the recording mode, and the drum servo system operates in the recording mode. Before entering the editing point, a phase error is detected between the vertical synchronization signal REC-VD of the recorded video signal B and the reproduced vertical synchronization signal PB-VD of the already recorded video signal (signal A in Fig. 1). The rotational phase of the rotary head is changed so that this phase error becomes zero. That is, as shown in FIG. 5a and c, REC-
The phase difference between the VD and PG pulses is changed from the fixed value φ by Δφ, which results in REC-VD and PB-VD (
Phase alignment with FIG. 5d) is performed. This phase matching is
This is accomplished by adjusting the reset signal of flip-flop 723 in FIG.

Next, the configuration and operation of the editing phase correction circuit 11 shown in FIG. 4 will be explained with reference to the waveform diagrams shown in FIGS. 7 to 9.

In FIG. 4, a phase difference correction counter (PEC counter) 24 is, for example, a 10-bit counter that counts clock pulses of a predetermined frequency.

From the output of this counter 24, an output PEC (FIG. 6 1) having the same period as the output of the buffer counter 18 (FIG. 6 j) which stores phase servo information in the form of its cyclic phase is obtained. This output is a pulse modulation signal (DPPWM)
Since the signal is supplied through the gate circuit to the reset terminal of the FF 23 for forming the PEC counter 24, the reset timing of the FF 23 is changed according to the circulating phase of the PEC counter 24.

The cyclic phase of the PEC counter 24 is REC-VD and PB.
- It is changed by adjusting the number of supplied clocks according to the phase difference with VD.

As shown in FIG. 7, a signal REC-VD' (FIG. 7b) delayed by a certain time t from the vertical synchronizing signal REC-VD (FIG. 7a) of the recording video signal B is formed. Also, the vertical synchronization signal PB-VD of the reproduced video signal A (
The signal P delayed by the same time t as above from FIG. 7d)
B-VD' (FIG. 7e) is formed. A phase correction circuit operates so that the phases of these signals RFC-VD' and PB-VD' match.

Signal REC-VD' is supplied to the clear input of flip-flop FF25. Furthermore, since a predetermined timing signal CG2 is supplied to the trigger input of FF25, FF2
5, the predetermined mid-pulse (low level) signals W and ID shown in FIG. 7C are obtained. This signal WID is a signal for detecting a loss with the PB-VD during playback, and is provided with a predetermined middle D (dead zone) to prevent hunting from occurring when detecting a loss. - The defeat detection signal WTD is supplied to the data input of the flip-flop FF26. In addition, the sample pulse DLPBVD (7th
Figure f) is formed and fed to the clock input of FF26. Therefore, the level of the coincidence detection signal at the rising position of the sampling pulse is read by the FF 26.

If the rising edge of the sample pulse is within the pulse of the coincidence detection signal as shown in FIG.
If VD' is in phase leading or lagging behind RPC-VD', the rising edge of the sample pulse will be as shown in Fig. 7 f',
As shown in "f", the first loss detection signal is not being detected, and the FF
26 is set, and the output MODFY becomes "1".

Correction command signal MODFY=1 indicates that phase correction is required.

Sample pulse DLPBVD is flip-flop FF2
Also supplied to the clock input of 7. For data input of this FF27, a signal REC-VD as shown in FIG. 7g is used.
' (FIG. 7b) A signal VG12 is supplied which is at a high level before and becomes a low level afterward. Therefore, FF27 is DL
It is set or reset according to the level of VC,12 at the rising timing of PBVD, and its Q output is
A signal 1) IRE is obtained by determining the direction of phase lead or delay of PB-VD' with respect to C-VD'. When the sample pulse is in an advanced phase as shown in Fig. 7 f', the correction direction indication signal DIRE becomes "1", and in this case, the phase correction is performed in the direction shown by the arrow in Fig. 7 f'. .

Further, when the sample pulse has a delayed phase as shown in FIG. 7f', the signal DIRE becomes "0", and in this case, phase correction is performed in the direction of the arrow in FIG. 7f".

In order to prevent the phase correction time from becoming long, the step width of one correction amount is changed in two steps, one in the vicinity of the -defeat detection width and one outside of it. Therefore, the correction command signal MODFY output from the FF 26 is supplied to the flip-flop FF 28, and the FF 28 counts the number of times the sample pulse DLPBVD passes through the coincidence detection range. Since the output of the FF 28 is supplied to the set input of the flip-flop 29 via the differentiating circuit 30, the FF 29, which is reset when fil is turned on, remains in the reset state when the number of passes does not reach two. Therefore, the hundred output of FF29 “1°
The AND gate G5 is opened, and a relatively low frequency (long period) clock pulse CP3 (Figure 8a)
is supplied to the pulse number control circuit 31 through the gate G5 and further through the OR gate G7. As a result, REC-
The phase of PB-VD with respect to VD is changed in large steps as shown in FIG.

Next, when the coincidence detection band (hatched area) in FIG. 10 is passed twice, the Q output of the FF 28 drops to a low level, and a negative pulse cent signal is formed in the differentiating circuit 30. As a result, FF29 is set, and its Q output "1" opens AND gate G6, and the clock pulse CP2 (FIG. 9a) with a frequency four times that of CF2 is output to the gate) G6.
6, and is supplied to the pulse control circuit 3I through G7. As a result, as shown in FIG. 10, the phase of PB-VD is 1.
It is corrected with a step width of /4.

It should be noted that CF is
When 2 is selected, the AND gate G8 is opened with the 100 output of the FF29, and the output PEC of the PEC counter 24 is
When you select 8 and CF2, FF29
Opens the AND gate G9 with the Q output of the counter 24
The output PECl0 of the 2nd pin higher order is selected. Note that the number of passes through the coincidence detection zone in Figure 10 is FF2.
The number of inversions of the corrected direction indicating signal DIRE obtained from the output of 7, that is, the number of turns in FIG. 10 may be counted.

Furthermore, regions with a constant pulse width are provided on both sides of the coincidence detection width shown in FIG. It's okay.

Clock pulse PECCP (C
F2 or CF2) is a D-type flip-flop FF32
is supplied to the clock terminal of Since the data transfer signal D-TR5 (FIGS. 8 and 9b) shown in FIG. A delayed signal is obtained with opposite polarity. FF32 100 output and signal D-TRS
is supplied to AND gate G10, so gate GIO
Pulse 0NECLK for one clock period from the output of (
8C and 9C) are formed.

This pulse is generated by the AND gate G of the pulse number control circuit 31.
ll is supplied. The one-clock pulse is generated each time the signal D-TRS is generated, that is, once per rotation of the head drum.

The gate Gll receives a correction direction instruction signal DIRE, a correction command signal MODFY, and a clock pulse CP3 or C.
A clock pulse obtained by doubling F2 with the frequency multiplier 33 (
8d and 9d) are provided. Therefore, when the phase of the sample pulse DLPBVD is at the position shown in FIG. 7 β', the correction command signal M OD F of the output of FF26
When Y is “1”, the correction direction instruction signal D of the output of FF27
Since IRE is 1″, one clock pulse 0NEC
During the interval LK (FIG. 8C), two clock pulses (FIG. 8d) output from the multiplier 33 pass through the gate G11 and are supplied to the OR gate 012. Furthermore, the one-crochet pulse is inverted by the inverter 34, and the OR gate G13
Since the clock pulse CP3 is supplied to the AND gate G14 through the gate G14, in periods other than the one clock pulse, the clock pulse CP3 is supplied to the OR gate G12 through the gate G14.

As a result, the clock pulse shown in FIG. 8e is obtained from the output of the OR gate G12, and this clock pulse is
Provided to the clock input of counter 24. Therefore, once per revolution of the head drum, the counter 24
Since the counter counts one extra clock pulse, the phase of the output PEC8 of the counter 24 is advanced by the time width of one clock pulse as shown in FIG. 6 β'. Output PEC8
passes through the AND gate G8 and the OR gate G15 and is supplied to the reset input of the FF23 as the phase adjustment pulse PEC-0UT.
supply voltage increases.

Therefore, the PG pulse advances in phase. That is, using the PG pulse as a reference, the sample pulse DLPBVD generated from the reproduced signal is moved in the direction of the arrow from the state shown in FIG. 7 f'. This changes the phase of DLPBVD to drum 1.
Each rotation changes as shown in Pl, P2, . . . in FIG. 10.

When the sample pulse passes through the coincidence detection zone as shown in Figure 10 and reaches position P4 (corresponding to the phase f'' in Figure 7)
, the correction direction instruction signal DIRE output from FF27 is “0”
Then, the gate G11 is closed. Therefore, only the inverted signal of the one-clock pulse is supplied from the inverter 34 to the gate G14 through the gate G13, so that the clock pulse that has passed from the gate G14 by one clock as shown in FIG. and is supplied to the PEC counter 24. Therefore, the output PE of the counter 24
The phase of C8 is shown in Figure 6! As shown in FIG. 1, the pulse width is delayed by the time width of one clock pulse. Therefore, the effective pulse width of the pulse width modulation signal DPPWM output from the FF 23 is narrowed, the voltage supplied to the drum motor 2 is lowered, and the DG pulse has a delayed phase.

That is, based on the PG pulse, the sample pulse DL
The PBVD is changed from the state shown in FIG. 7f'' in the direction of the arrow.

When the phase of the sample pulse passes through the coincidence detection band and becomes as shown in FIG.
”, and at the same time, the sample pulse passes through the coincidence detection band twice, so the clock pulse CP2 with four times the frequency
can be switched to Therefore, as described above, the clock pulse e in FIG. 9, which is one clock more, is supplied from the pulse number control circuit 31 to the PEC counter 24, and the phases of the sample pulses are changed as shown in FIG. 10, P5, P6, Pl... be adjusted. Note that the phase of the sample pulse may be changed from the position P4 in the direction of the coincidence detection band by a small step width, and in this case, the number of clock pulses CP2 is
The counter 24 counts the clock pulses shown in FIG. 9f, which are decreased by one per rotation, in the same manner as described above.

When the rising edge of the sample pulse DLPBVD falls within the coincidence detection range as shown in FIG. 7f, the correction command signal MOD F Y output from the FF 26 becomes O''.

Since the 100 output of FF26 is supplied to G13 of the clock number control circuit 31, after -defeat is detected,
Continuous clock pulse CP2 is applied to gates G14 and G12.
The signal is supplied to the PEC counter 24 through the PEC counter 24. Therefore, the phase of the output PEC10 of the counter 24 is held constant.

In this way, the reset point R (falling edge The position of point ) is changed, for example, as indicated by the dotted line in FIG. 5e. This causes the PC pulse (Fig. 5a)
) and REC-VD, a bias amount Δφ is added to the set phase difference φ between REC-VD and REC-VD.

Note that when a change in pulse width occurs in the pulse width modulation signal DPPWM, the phase difference detection circuit 10 shown in FIG. Therefore, when the servo system becomes stable, the phase difference between the PG pulse and PEC-VD is maintained at φ+Δφ.

Note that during editing phase matching, it is necessary to maintain the adjustment range of the reset point R of the pulse width modulation signal within a predetermined range. This is because if the adjustment range is unlimited, for example, the R point in FIG. 5e will approach 8 points and may exceed 8 points. In this case, the phase servo system is disturbed and the head phase rotates by one rotation for editing phase adjustment, which is extremely undesirable. For this reason, the phase adjustment is performed only in the region defined by the dashed line between β and β″ in FIG.

In FIG. 4, the phase adjustment pulse PEC-0UT obtained from the OR gate G15 is applied to the D-type free knob flop F
F37.38 are fed to respective clock inputs. Further, in the clock circuit 16, timing pulses T1 and T2 shown in FIG. 6 m and n are formed. These pulses T
1, T2 and its inverted signal Tl, T2 is game) 016,
G17, and the outputs of these gates are respectively F F
3'? , 38. Therefore, FF3
7 samples the range of actual 'K>%J in FIG.

Therefore, the output DIRE of the FF 27 becomes "1" and the direction of change of the phase adjustment pulse P'EC-0UT is reversed to the left direction of the arrow in FIG. 6m.

Similarly, when the FF38 samples the range indicated by the solid line in Figure 6 m, this is set, so the output S
The FF 27 is forcibly reset by K. Therefore, the direction of change of the phase adjustment pulse is reversed to the right direction of the arrow in FIG. 6m.

In this way, in the editing assemble mode, until the assemble point is entered, the editing machine operates in the playback mode and tracking servo is performed by the capstan, and during this time, as described above, the recording signal and the playback signal are aligned in phase. will be held. After the assembly point, aligned phases are maintained and the editor is switched to recording mode. In the insert mode, tracking servo is performed in the playback mode as described above until the insertion point is reached, and phase alignment is performed during this time. After the insert point, tracking servo using the reproduced CTL signal continues, but since the reproduced vertical synchronization signal is no longer obtained, the editing phase correction circuit 11 maintains the phase. In the w6 collector, only the magnetic head system is switched to the recording mode.

Note that when switching to the normal recording mode after operating in the dawn collection mode, the phase correction information held in the PEC counter 20 is cleared and the PG pulse and PEC-
It is necessary to cancel the phase correction amount of Δφ given between VD and VD.

Next, FIG. 11 is a partial block diagram showing another embodiment of the present invention, and FIG. 12 is a waveform diagram of FIG. 11.

In FIG. 11, the same signals are attached to the same parts as in FIG. 4, and the shared circuit parts are omitted.

In this embodiment, the fixed delay amount (FIG. 6b) by the monomulti 13 in FIG. 4 is controlled according to the phase difference between REC-VD and PB-VD, and thereby the F )
A correction amount of Δφ is added to the set phase difference φ between the G pulse and REC-VD. In Figure 11, P
The C pulse (FIG. 12a) is supplied to a monomulti 39 for timing adjustment, and the delayed signal shown in FIG. 12 is obtained from its output. The output of the monomulti 39 is the differentiator circuit 40
Since the flip-flop 41 is set through the FF
The Q output of 41 rises as shown in FIG. 12C. Since the output of FF41 is supplied as a strobe pulse to AND gate 018, the clock pulse PECCP output from gate G7 in FIG. 4 passes through gate G18 and is supplied to lock number control circuit 31 as in FIG. be done.

The clock number control circuit 31 receives a correction direction instruction signal DIRE and a correction command signal MOD, which are formed in the same manner as shown in FIG.
Since F Y and MODFY are supplied, PB-
Clock pulses whose number is adjusted according to the phase difference between VD and REC-VD are obtained from the control circuit 31. This clock pulse is supplied to the PEC counter 24, so the PEC counter 24 performs a counting operation as shown in FIG. 12d, and after counting a predetermined number of clocks, its output P
EC10 or PEC8 falls as shown in FIG. 12d.

Output PECl0 or PEC8 is G) C8, C9, G
15 and supplied to the reset input of FF4. Therefore, the Q output of FF4 falls as shown in FIG. 12C, thereby setting FF14 as shown in FIG. FF14 is the recording vertical synchronization signal REC-VD (first
2 r), the signal DPEB shown in FIG. 12 e is obtained from the Q output of Fl"14. The pulse width of this signal is the same as that of the PG pulse and REC- as in FIG. 6 e.
Corresponding to the phase difference with VD, phase difference information can be obtained by measuring the pulse width. This phase difference information fixes the phase difference between the PC pulse and REC-VD to φ.

Similar to the embodiment shown in FIG. 4, the number of clocks supplied to the PEC counter 24 is increased or decreased by one clock per rotation of the drum so that the phase difference between REC-VD and PB-VD becomes zero. As a result, the rise of the Q output of the FF 14 is gradually changed as shown by the arrow in FIG. 12e. As a result, a bias amount Δφ is added to the phase difference φ between the PC pulse and REC-VD, which causes REC-VD and PB-
The phase difference with VD becomes zero.

The present invention is directed to a VT system which sequentially forms inclined recording tracks on a magnetic tape using the rotating magnetic heads 3A and 3B as described above.
In order to edit and record with R, the position of one edge is determined based on the phase relationship between the phase pulse PG indicating the rotational phase of the rotating magnetic head and the recording vertical synchronization signal REC-VD in the video signal to be newly recorded. is determined, and the recorded vertical synchronizing signal REC-VD in the video signal to be newly recorded and the reproduced vertical synchronizing signal PB-VD reproduced by the rotating magnetic head up to the editing start point are determined. A pulse-in-pulse modulation circuit (
Phase detection counter 17 and buffer counter 1 of the embodiment
8, a phase difference correction counter 24, a flip-flop 23, etc.).

Therefore, by controlling the rotational phase of the rotating magnetic head with the output of the pulse width modulation circuit, it is possible to match the vertical synchronization phase on the video trunk formed on the tape before and after the editing point. In particular, phase matching can be achieved using a constant amplitude pulse width modulation signal consisting of a high level and a low level without performing signal processing in the amplitude direction, so the circuit configuration is simple and it is easy to use for digital processing. It is suitable for use in integrated circuits.

[Brief explanation of the drawing]

Figures 1a and b are diagrams of recording patterns on tape to explain the processes of the assemble mode and the insert edit mode, respectively, and Figure 2 aSb shows the phase shift of the synchronization signal before and after the editing point, respectively. Fig. 3 is a professional diagram of a VTR drum servo system to which the present invention is applied, and Fig. 4 is a circuit diagram of a phase servo circuit to which the present invention is applied. Fig. 5 is a time chart showing the target to be achieved by this servo circuit, Figs. 6 to 9 are waveform diagrams of each part of Fig. 4, and Fig. 10 is a phase alignment between the reproduction synchronization signal and the recording synchronization signal. Graph showing the process of
FIG. 12 is a partial block diagram showing another embodiment of the present invention.
The figure is a waveform diagram of each part in FIG. 11. In addition, in the symbols used in the drawings, 9--・-----------1------- Phase servo circuit 10--...------- Phase difference detection circuit 11 ・−1−−−−−・−−−−−−1 Editing phase correction circuit 17−・−・・−・・−Phase detection counter 18 ・
・−・−・−・−−−−−−−Buffer counter 23
・−・・−・・−−1−−−−−Flip flop 2
4-・-・-・・・～ P'EC counter.

Claims (1)

[Claims] 1. When editing and recording on a VTR that uses a rotating magnetic head to sequentially form inclined recording tracks on a magnetic tape, a phase pulse indicating the rotational phase of the rotating magnetic head and a new recording The position of one edge is determined based on the phase relationship with the recording vertical synchronization signal in the video signal to be newly recorded, and the recording vertical synchronization signal in the video signal to be newly recorded and the above A phase servo circuit provided with a pulse width modulation circuit that forms a pulse whose position on the other edge is determined by the phase relationship with a reproduced vertical synchronization signal reproduced by a rotating magnetic head. 2. The phase servo circuit according to claim 1, wherein the control step amount for the other edge in the pulse width modulation circuit is variable depending on the amount of phase error between the recording vertical synchronization signal and the reproduction vertical synchronization signal. .