JPS63232450A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS63232450A JPS63232450A JP62066023A JP6602387A JPS63232450A JP S63232450 A JPS63232450 A JP S63232450A JP 62066023 A JP62066023 A JP 62066023A JP 6602387 A JP6602387 A JP 6602387A JP S63232450 A JPS63232450 A JP S63232450A
- Authority
- JP
- Japan
- Prior art keywords
- bump
- opening
- internal wiring
- barrier metal
- onto
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 14
- 238000004519 manufacturing process Methods 0.000 title claims description 4
- 229910052751 metal Inorganic materials 0.000 claims abstract description 31
- 239000002184 metal Substances 0.000 claims abstract description 31
- 230000004888 barrier function Effects 0.000 claims abstract description 25
- 238000000151 deposition Methods 0.000 claims abstract description 6
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 238000009832 plasma treatment Methods 0.000 claims abstract description 5
- 238000007747 plating Methods 0.000 claims abstract description 5
- 238000000034 method Methods 0.000 claims description 14
- 230000015572 biosynthetic process Effects 0.000 abstract description 7
- 239000011248 coating agent Substances 0.000 abstract 1
- 238000000576 coating method Methods 0.000 abstract 1
- 238000007493 shaping process Methods 0.000 abstract 1
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 8
- 239000010408 film Substances 0.000 description 7
- 238000007796 conventional method Methods 0.000 description 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 5
- 239000010931 gold Substances 0.000 description 5
- 229910052737 gold Inorganic materials 0.000 description 5
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 4
- 229910052763 palladium Inorganic materials 0.000 description 4
- 229910052719 titanium Inorganic materials 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000010409 thin film Substances 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000003825 pressing Methods 0.000 description 2
- 241001026509 Kata Species 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 239000002893 slag Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1301—Shape
- H01L2224/13011—Shape comprising apertures or cavities, e.g. hollow bump
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13144—Gold [Au] as principal constituent
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔概要〕
半導体装置における内部配線を導出するバンプ電極の形
成において、
バリアメタル層上にバンプ形成領域として設けたマスク
層開孔に、その側面にプラズマ処理によりバリアメタル
層の一部を堆積してから、バンプメタルをめっきして枡
型のバンプを形成することにより、
バンプの押圧が内部配線に対して過大な押しっけになら
ないようにしたバンプ電極の形成を簡易にさせたもので
ある。[Detailed Description of the Invention] [Summary] In the formation of bump electrodes leading out internal wiring in a semiconductor device, a barrier metal layer is formed on the side surface of a mask layer opening provided as a bump formation region on a barrier metal layer by plasma treatment. By depositing a portion of the electrode and then plating bump metal to form a square-shaped bump, it is possible to easily form a bump electrode that prevents the bump from exerting too much pressure on the internal wiring. This is what I was made to do.
本発明は、半導体装置製造方法に係り、特に、内部配線
を導出するバンプ電極の形成方法に関す。The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of forming bump electrodes for leading out internal wiring.
集積化された半導体装置には、その実装密度を高めるた
め、半導体チップの内部配線から突出させたバンプ電極
を設け、これを外部配線との接続用に供するものがある
。In order to increase the packaging density of integrated semiconductor devices, some integrated semiconductor devices are provided with bump electrodes that protrude from the internal wiring of the semiconductor chip and are used for connection with external wiring.
その場合、上記バンプ電極は、接続に際して当該半導体
装置を損傷させることのないように形成されることが重
要である。In that case, it is important that the bump electrodes be formed so as not to damage the semiconductor device during connection.
バンプ電極形成の従来方法は、第２図の工程順側断面図
に示すが如くである。即ち、
同図において、先ず〔図（ａ）参照〕、絶縁膜２を介し
て基板１上に設けられたアルミニウムの内部配線３を被
覆する絶縁膜４に内部配線３を表出させる開孔５を形成
し、その上に例えばチタンおよびパラジウムの二層構成
（下層がチタン）でなるバリアメタル層６を被着する。The conventional method for forming bump electrodes is as shown in the step-by-step sectional side view of FIG. That is, in the figure, first [see Figure (a)], an opening 5 is formed in the insulating film 4 that covers the aluminum internal wiring 3 provided on the substrate 1 via the insulating film 2, through which the internal wiring 3 is exposed. A barrier metal layer 6 made of, for example, a two-layer structure of titanium and palladium (the lower layer is titanium) is deposited thereon.
次いで〔図（ｂ）参照〕、その上にレジストからなり開
孔５の領域を包含する開孔８を有するマスク屓７を形成
し、開孔８に表出するバリアメタル層６に金を電解めっ
きして開孔８を充填し、金のバンプ９を形成する。Next [see Figure (b)], a mask bottom 7 made of resist and having an opening 8 that covers the area of the opening 5 is formed thereon, and the barrier metal layer 6 exposed in the opening 8 is electrolyzed with gold. The apertures 8 are filled by plating to form gold bumps 9.
次いでｃ図ｆｃ）参照〕、マスクＨ７を除去してから、
バンプ９をマスクにしたエツチングによりバンプ９直下
以外のバリアメタルｌ１ｉ６を除去して、バンプ電極の
形成を完了する。Then, after removing the mask H7,
By etching using the bump 9 as a mask, the barrier metal l1i6 other than directly under the bump 9 is removed to complete the formation of the bump electrode.
この場合の寸法は、例えば、開孔５の大きさが５０μｍ
程度、バリアメタルｌ１ｉ６の厚さカ０．６μｌ程度、
マスク屓７の厚さが２５μｍ程度、開孔８の大きさが６
０μｍ程度（従って、バンプ９の大きさおよび高さは、
それぞれ６０および２５μｍ程度となる）といった具合
である。In this case, the size of the opening 5 is, for example, 50 μm.
The thickness of the barrier metal l1i6 is approximately 0.6μl,
The thickness of the mask bottom 7 is about 25 μm, and the size of the opening 8 is 6
approximately 0 μm (therefore, the size and height of bump 9 are
60 and 25 μm, respectively).
ところで、かく形成されたハンプ電極は、第３図の問題
点説明図に示す如く、外部配線１０に接続される際のバ
ンプ９の押圧により、開孔５を通して軟らかい内部配線
３を強く押しつける。このため内部配線３が外側に押し
出されて絶縁膜２に１１で示すようなりラックを住じさ
せる場合がある。By the way, the thus formed hump electrode strongly presses the soft internal wiring 3 through the opening 5 due to the pressure of the bump 9 when connected to the external wiring 10, as shown in the diagram for explaining the problem in FIG. For this reason, the internal wiring 3 may be pushed outward, causing a rack as shown at 11 to reside in the insulating film 2.
このクランク１１は、当該半導体装置の信頼性を低下さ
せる問題となる。This crank 11 poses a problem that reduces the reliability of the semiconductor device.
この問題を解決し得るものとして、特開昭５４＝１２４
６７４号公報に開示されたバンプ電極がある。As a solution to this problem, JP-A-54=124
There is a bump electrode disclosed in Japanese Patent No. 674.
それは、第４図の側断面図に示すが如きものであり、バ
ンプ９が、開孔５の領域に開孔１２を設けてバリアメタ
ル層６を表出させたバンプ９ａに変わっている。こうす
ることにより、ハンプが開孔５を通して内部配線３を押
しつけることが防止される。This is as shown in the side cross-sectional view of FIG. 4, in which the bump 9 is replaced by a bump 9a in which an opening 12 is provided in the area of the opening 5 to expose the barrier metal layer 6. This prevents the hump from pressing the internal wiring 3 through the opening 5.
しかしながら、この構造のバンプ電極は、開孔１２の底
面にバリアメタル層６が表出しているため、バリアメタ
ル層６の余分な部分を除去する工程でバンプ９ａをマス
クに利用することが困難となり、形成工程が複雑になる
問題がある。However, in the bump electrode having this structure, since the barrier metal layer 6 is exposed at the bottom of the opening 12, it is difficult to use the bump 9a as a mask in the process of removing the excess portion of the barrier metal layer 6. , there is a problem that the formation process becomes complicated.
上記問題点は、基板上の内部配線を被覆する絶縁膜に該
内部配線を表出させる第一の開孔を形成し、その上にバ
リアメタル層を被着した後、その上に該第一の開孔の領
域を包含する第二の開孔を有するマスク屓を形成し、プ
ラズマ処理により該第二の開孔に表出する該バリアメタ
ル層の一部を該第二の開孔の側面に堆積してから、該第
二の開孔の底面および側面にバンプメタルをめっきして
枡型のバンプを形成する工程を含んで、該内部配線を導
出するバンプ電極を形成する本発明の製造方法によって
解決される。The above problem can be solved by forming a first opening in the insulating film that covers the internal wiring on the substrate to expose the internal wiring, and then depositing a barrier metal layer thereon. forming a mask bottom having a second aperture that covers a region of the aperture, and forming a part of the barrier metal layer exposed in the second aperture by plasma treatment on a side surface of the second aperture; The manufacturing method of the present invention includes the step of depositing bump metal on the bottom and side surfaces of the second opening to form a square-shaped bump, thereby forming a bump electrode for leading out the internal wiring. Solved by method.
本方法により形成されたバンプ電極は、バンプが枡形を
なして中空であるため、第３図で説明したクラック１１
が発生するような内部配線に対する過大な押しっけがな
（なり、第４図に示したバンプ電極と同様に、外部配線
に接続する際のバンプの押圧に起因する当該半導体装置
の信頼性低下を防出する。In the bump electrode formed by this method, since the bump is square-shaped and hollow, the cracks 11 explained in FIG.
There should be no excessive pressure on the internal wiring, which would cause a drop in the reliability of the semiconductor device due to the pressure of the bump when connecting to the external wiring, similar to the bump electrode shown in Figure 4. Prevent.
然も、本方法では、バンプが第４図に示したバンプ９ａ
に設けられた開孔１２の底面部分にもバンプメタルが存
在する枡形となるので、先に述べた余分なバリアメタル
層６の除去にバンプを利用することが可能になり、バン
プ電極形成の工程が第４図図示バンプ電極の場合より簡
易になる。However, in this method, the bump is the bump 9a shown in FIG.
Since the bump metal is also present at the bottom of the opening 12 provided in the square shape, the bump can be used to remove the excess barrier metal layer 6 mentioned above, and the process of forming the bump electrode can be completed. is simpler than in the case of the bump electrode shown in FIG.
以下本発明方法によるバンプ電極形成の実施例について
第１図の工程順側断面図により説明する。An example of forming bump electrodes by the method of the present invention will be described below with reference to step-by-step side cross-sectional views of FIG. 1.
企図を通じ同一符号は同一対象物を示す。The same reference numerals refer to the same objects throughout the design.
同図において、先ず〔図ｔａ＋参照〕、従来方法の場合
と同様に、絶縁膜２を介して基板ｌ−ヒに設けられたア
ルミニウムの内部配線３を被覆する絶縁膜４に内部配線
３を表出させる開孔５を形成し、その上に例えばチタン
およびパラジウムの二層構成（下層がチタン、−ヒ屓が
パラジウム）でなるバリアメタル層６を被着する。In the same figure, first of all, as in the case of the conventional method, the internal wiring 3 is exposed on the insulating film 4 that covers the aluminum internal wiring 3 provided on the substrate l-hi through the insulating film 2. An opening 5 is formed to allow the opening 5 to come out, and a barrier metal layer 6 made of, for example, a two-layer structure of titanium and palladium (the lower layer is titanium and the lower layer is palladium) is deposited thereon.
次いで〔図（ｂｌ参照〕、その上にレジストからなり開
孔５の領域を包含する開孔８を有するマスク層７を形成
し、プラズマ処理例えば酸素を用いた反応性イオンエツ
チング（ＲＩ Ｅ）処理により、開孔８に表出するバリ
アメタル層６の表面部分を飛散させる。さすれば、飛散
したメタル（ここではパラジウム）は、開孔８の側面に
堆積してメタル薄膜１３を形成する。Next, as shown in FIG. As a result, the surface portion of the barrier metal layer 6 exposed in the opening 8 is scattered.The scattered metal (here, palladium) is then deposited on the side surface of the opening 8 to form a metal thin film 13.
次いでｃ図（Ｃ）参照〕、開孔８の底面および側面に、
即ち、開孔８に表出するバリアメタル層６およびメタル
薄膜１３に金を電解めっきして、枡形をなす金のバンプ
９ｂを形成する。Then, on the bottom and side surfaces of the opening 8,
That is, the barrier metal layer 6 and metal thin film 13 exposed in the opening 8 are electrolytically plated with gold to form square-shaped gold bumps 9b.
次いで〔図（ｄｌ参照〕、従来方法の場合と同様に、マ
スクＮ７を除去してから、バンプ９ｂをマスクにしたエ
ツチングによりバンプ９ｂ直下以外のバリアメタルＦ４
６を除去して、バンプ電極の形成を完了する。Next, as in the conventional method, after removing the mask N7, etching is performed using the bump 9b as a mask to remove the barrier metal F4 except directly under the bump 9b.
6 is removed to complete the formation of the bump electrode.
この場合の寸法は、基本的には従来方法の場合と変わり
がなく、例えば、開孔５の大きさが ５０μｍ程度、バ
リアメタルＭ６の厚さが０．６μｍ程度、マスクＦｉｆ
７の厚さが２０μｍ程度、開孔８の大きさが６０１ＩＩ
ＩＩ稈度、バンプ９ｂ形成の金めつきの厚さが５μＩ程
度（従って、バンプ９ｂの大きさ、高さおよび肉厚は、
開孔８の上部に盛り上がりがあって、それぞれ６０．２
５および５μｍ程度となる）といった具合である。The dimensions in this case are basically the same as those in the conventional method; for example, the size of the opening 5 is about 50 μm, the thickness of the barrier metal M6 is about 0.6 μm, and the mask F
The thickness of the hole 7 is about 20 μm, and the size of the opening 8 is 601II.
II culm, the thickness of the gold plating forming the bump 9b is about 5μI (therefore, the size, height and wall thickness of the bump 9b are:
There is a bulge at the top of the opening 8, each having a diameter of 60.2
5 and 5 μm).
また、その際の先に述べたＲＩＥ処理の条件は、例えば
、処理圧力が凡そ０．０３Ｔｏｒｒ、酸素の流量が３０
０〜５００ｃｃ、高周波電力が３００〜４００Ｗ、処理
時間が２〜３分、にするのが良い。In addition, the conditions of the RIE process mentioned above at that time are, for example, the process pressure is approximately 0.03 Torr, and the oxygen flow rate is 30 Torr.
It is preferable that the volume is 0 to 500 cc, the high frequency power is 300 to 400 W, and the processing time is 2 to 3 minutes.
かく形成されたバンプ電極は、バンプ９ｂが枡形をなし
て中空であるため、第３図で説明したように外部配線１
０に接続される際にバンプ９ｂの押圧があっても、クラ
ック】１が発生するような内部配線３に対する過大な押
しっけがなくなり、バンプ９ｂの押圧に起因する当該半
導体装置の信頼性低下を防止する。Since the bump 9b formed in this way has a square shape and is hollow, the external wiring 1 can be connected to the external wiring 1 as explained in FIG.
Even if there is pressure from the bump 9b when connecting to 0, there is no excessive pressure on the internal wiring 3 that would cause cracks 1, and the reliability of the semiconductor device is reduced due to the pressure from the bump 9b. To prevent.
然も、上述したバンプ電極の形成方法は、第４図に示し
たバンプ電極の形成の場合に比して、余分なバリアメタ
ル層６の除去にバンプ９ｂをそのまま利用することが出
来るので、工程が簡易である。However, in the method for forming the bump electrode described above, compared to the case of forming the bump electrode shown in FIG. is simple.
なお、本発明は、上記の説明から判るように、内部配線
とハンプの材料の硬さの束ね合いにより発生ずる問題を
解決するものであり、内部配線３、バリアメタルｌ１ｉ
ｆ６およびバンプ９ｂの材料が上記実施例に限定される
ものではない。As can be seen from the above description, the present invention solves the problem caused by the hardness of the materials of the internal wiring and the hump.
The materials of f6 and bump 9b are not limited to those in the above embodiments.
以′Ｉ：、説明したように本発明の構成によれば、半導
体装置における内部配線を導出するバンプ電極の形成に
おいて、バンプの押圧が内部配線に対して過大な押しつ
けにならないようにしたバンプ電極の形成を簡易にさせ
ることが出来て、上記押圧に起因する当該半導体装置の
信頼性低下の防止対策を安価にさせる効果がある。As described above, according to the configuration of the present invention, in forming a bump electrode for leading out internal wiring in a semiconductor device, a bump electrode is formed in which the pressure of the bump is not excessively pressed against the internal wiring. This has the effect of simplifying the formation of the semiconductor device and reducing the cost of measures to prevent reliability degradation of the semiconductor device caused by the above-mentioned pressing.
第１図は本発明方法実施例の工程順側断面図、第２図は
従来方法の工程順側断面図、
第３図は従来方法による場合の問題点説明図、第４図は
バンプ電極改良案の側断面図、である。
図において、
１は基板、
２．４は絶縁膜、
３は内部配線、
５．８．１２は開孔、
６はバリアメタル層、
７はマスク層、
９．９ａ、 ９ｂはバンプ、
ＩＯは外部配線、
１１はクラック、
１３はメタル薄膜、
である。
本！！明方法実兇硬１のニオ［横便１断面図第 １ 図
ｉｔ来７ｒ ；ｆｋ）１ ＊！ＬＪ１１１ｊ （Ｊｌｉ
Ｗｒｋ ｍ茅 ２ 国
イ疋来方；太に」ろｔｒｉ、合の閂題に、説明図葉 ３
図
バンア電滓面改良業の滑Ｊ断面図
箋 ４ 図Fig. 1 is a cross-sectional view of the method according to the present invention in the order of steps, Fig. 2 is a cross-sectional view of the conventional method in the order of steps, Fig. 3 is an explanatory diagram of problems in the case of the conventional method, and Fig. 4 is a bump electrode improvement. It is a side sectional view of the plan. In the figure, 1 is the substrate, 2.4 is an insulating film, 3 is internal wiring, 5.8.12 is an opening, 6 is a barrier metal layer, 7 is a mask layer, 9.9a and 9b are bumps, IO is external 11 is a crack, and 13 is a metal thin film. Book! ! Clear Method Practical Hardness 1's Nio [Transverse stool 1 cross-sectional view 1st figure it to 7r ; fk) 1 *! LJ111j (Jli
Wrk m茅 2 Kuni Ihikira kata; fat ni''rotri, in the main title, explanatory map leaf 3
Diagram 4: J section map of Banga electrical slag surface improvement industry
Claims (1)
出させる第一の開孔を形成し、その上にバリアメタル層
を被着した後、その上に該第一の開孔の領域を包含する
第二の開孔を有するマスク層を形成し、プラズマ処理に
より該第二の開孔に表出する該バリアメタル層の一部を
該第二の開孔の側面に堆積してから、該第二の開孔の底
面および側面にバンプメタルをめっきして枡型のバンプ
を形成する工程を含んで、該内部配線を導出するバンプ
電極を形成することを特徴とする半導体装置製造方法。After forming a first opening to expose the internal wiring in an insulating film covering the internal wiring on the substrate and depositing a barrier metal layer thereon, the area of the first opening is formed on the barrier metal layer. forming a mask layer having a second aperture containing the second aperture, and depositing a portion of the barrier metal layer exposed in the second aperture on the side surface of the second aperture by plasma treatment; A method for manufacturing a semiconductor device, comprising the step of plating bump metal on the bottom and side surfaces of the second opening to form a square-shaped bump, to form a bump electrode for leading out the internal wiring. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62066023A JPS63232450A (en) | 1987-03-20 | 1987-03-20 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62066023A JPS63232450A (en) | 1987-03-20 | 1987-03-20 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63232450A true JPS63232450A (en) | 1988-09-28 |
Family
ID=13303910
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62066023A Pending JPS63232450A (en) | 1987-03-20 | 1987-03-20 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63232450A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011515829A (en) * | 2008-02-22 | 2011-05-19 | コミッサリア ア レネルジー アトミーク エ オ ゼネルジ ザルタナテイヴ | Connection component with hollow insert and method for manufacturing the same |
| JP2016178201A (en) * | 2015-03-20 | 2016-10-06 | コミッサリア ア レネルジー アトミーク エ オ エナジーズ アルタナティブス | Manufacturing method of conductive member for electronic constituent including end with cavity |
-
1987
- 1987-03-20 JP JP62066023A patent/JPS63232450A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011515829A (en) * | 2008-02-22 | 2011-05-19 | コミッサリア ア レネルジー アトミーク エ オ ゼネルジ ザルタナテイヴ | Connection component with hollow insert and method for manufacturing the same |
| EP2255383B1 (en) * | 2008-02-22 | 2019-01-02 | Commissariat à l'Énergie Atomique et aux Énergies Alternatives | Connection component with hollow inserts and method for making same |
| JP2016178201A (en) * | 2015-03-20 | 2016-10-06 | コミッサリア ア レネルジー アトミーク エ オ エナジーズ アルタナティブス | Manufacturing method of conductive member for electronic constituent including end with cavity |
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