JPS63232437A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS63232437A
JPS63232437A JP62066148A JP6614887A JPS63232437A JP S63232437 A JPS63232437 A JP S63232437A JP 62066148 A JP62066148 A JP 62066148A JP 6614887 A JP6614887 A JP 6614887A JP S63232437 A JPS63232437 A JP S63232437A
Authority
JP
Japan
Prior art keywords
film
semiconductor chip
semiconductor
film carrier
lead terminals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62066148A
Other languages
Japanese (ja)
Inventor
Shigeru Kagiyama
鍵山　滋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62066148A priority Critical patent/JPS63232437A/en
Publication of JPS63232437A publication Critical patent/JPS63232437A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto

Abstract

PURPOSE:To improve yield, reliability and bonding properties by forming pads respectively connecting lead terminals fitted to a vessel at positions on a film in a film carrier corresponding to each lead terminal. CONSTITUTION:A semiconductor chip 3 with a semiconductor element and a plurality of element electrodes connected to the semiconductor element, a film 4 for a film carrier, a central section of which is punched in size approximately the same as or slightly larger than the outside dimensions of the semiconductor chip 3, and a plurality of pads 5p, which are shaped at positions on the film corresponding to respective lead terminal 11 set up to a vessel 1 housing the semiconductor chip 3 and the surfaces of which are connected separately at the inside ends of lead terminals 11, are provided. A plurality of pattern wirings 5, which are connected to each pad 5p respectively, formed in a protruding manner onto the film 4 and to punched sections and tips of which are connected separately to the corresponding element electrodes in the semiconductor chip 3, are furnished. Accordingly, yield, reliability and bonding properties are improved, and the applicability of the state of the film carrier can be extended.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 °本発明は半導体装置に関し、特に半導体チップを多数
のリード端子が設けられた容器に収納する半導体装置に
関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device in which a semiconductor chip is housed in a container provided with a large number of lead terminals.

〔従来の技術〕[Conventional technology]

一般に、ＰＧＡ　（Ｐｉｎ　Ｇｒｉｄ　Ａｒｒａｙ）と
呼ばれる一つの面に多数のリード端子を配列した多ビン
の容器を用いて半導体装置を組立る場合、半導体チップ
の素子電極とリード端子間を接続するのに、従来の技術
としては、通常のワイヤボンディングによる方法とフィ
ルムキャリアを用いたＴ　Ａ　Ｂ　（Ｔａｐｅ　Ａｕｔ
ｏｍａｔｅｄ　Ｂｏｎｄｉｎｇ）方式とがある。Generally, when assembling a semiconductor device using a multi-bin container called a PGA (Pin Grid Array) in which a large number of lead terminals are arranged on one surface, it is necessary to connect between the element electrodes of the semiconductor chip and the lead terminals. Conventional techniques include normal wire bonding and TAB (Tape Out) using a film carrier.
There is a bonding method.

前者は従来からある方法をそのまま多ビンのワイヤボン
ディングに適用したものであり、後者はフィルムキャリ
アの内側リードに半導体チップの各素子電極を接続（Ｉ
ＬＢ・・・Ｉｎｎｅｒ　ＬｅａｄＢｏｎｄｉｎｇ）　し
た後、外側リードの途中から外側のフィルムキャリアの
不要な部分を切り落として−体化した半導体チップ、内
側及び外側リード、フィルムキャリアの一部を分離し、
外側リードを容器の各リード端子に接続（ＯＬ　Ｂ−・
・０ｕｔｅｒ　ＬｅａｄＢｏｎｄｉｎｇ）する方法であ
る。特に後者の方法はピン数が増えるにつれてボンディ
ング作業効率、ボンディング性の面で利点が大きくなる
。The former is a conventional method applied directly to multi-bin wire bonding, while the latter connects each element electrode of a semiconductor chip to the inner lead of a film carrier (I
LB...Inner Lead Bonding) After that, the unnecessary part of the outer film carrier is cut off from the middle of the outer lead to separate the integrated semiconductor chip, inner and outer leads, and a part of the film carrier.
Connect the outer lead to each lead terminal of the container (OL B-・
・This is a method of 0uter Lead Bonding). In particular, the latter method has greater advantages in terms of bonding efficiency and bonding performance as the number of pins increases.

また、後者の場合はフィルムキャリアに半導体チ・シブ
をボンディングした状態で出荷されることもある。In the latter case, the semiconductor chips may be bonded to the film carrier before being shipped.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来の半導体装置は、通常のワイヤボンディン
グかフィルムキャリアにより素子電極・リード端子間を
接続する構成となっているので、ワイヤーボンディング
による場合は、ボンディング数が多くなるとそれに応じ
てポンディングパッドの面積が小さくなるためボンディ
ングずれ、打ち間違いなどの不具合が発生し易くなり歩
留り。The conventional semiconductor device described above is configured to connect element electrodes and lead terminals using normal wire bonding or a film carrier, so when wire bonding is used, the number of bonding pads increases as the number of bonding increases. As the area becomes smaller, problems such as bonding misalignment and misprinting are more likely to occur, which reduces yield.

信頼性が低下するという欠点がある。This has the disadvantage of reduced reliability.

一方、フィルムキャリアによる場合は、ボンディング性
に優れているが、ＩＬＢ、ＯＬＢめ計２回のボンディン
グが必要となること、フィルムキャリア状態で出荷する
場合、ユーザー側でＯＬＢ等の設備を導入しなければい
けないという問題があり、適用範囲が限定されるという
欠点がある。On the other hand, when using a film carrier, bonding properties are excellent, but bonding is required twice for ILB and OLB, and if shipped in a film carrier state, the user must install equipment such as OLB. However, it has the disadvantage that the scope of application is limited.

本発明の目的は、歩留り、信頼性、ボンディング性が優
れ、フィルムキャリア状態の適用範囲を拡大することが
できる半導体装置を提供することにある。An object of the present invention is to provide a semiconductor device that has excellent yield, reliability, and bonding performance, and can expand the range of application in the film carrier state.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の半導体装置は、半導体素子とこの半導体素子に
接続された複数の素子電極とを備えた半導体チップと、
中央部が前記半導体チップの外形寸法とほぼ同じかやや
大きい寸法で打ち抜かれたフィルムキャリア用のフィル
ムと、前記半導体チップを収納する容器に設けられた各
リード端子に対応する前記フィルム上の位置に形成され
表面が前記リード端子の内側端とそれぞれ接続する複数
のパッドと、これら各パッドとそれぞれ接続し前記フィ
ルム上及び前記打ち抜かれた部分に突出して形成され先
端が前記半導体チップの対応する素子電極にそれぞれ接
続する複数のパターン配線とを有している。A semiconductor device of the present invention includes a semiconductor chip including a semiconductor element and a plurality of element electrodes connected to the semiconductor element;
A film for a film carrier, the central part of which is punched out with dimensions that are approximately the same as or slightly larger than the external dimensions of the semiconductor chip, and a position on the film that corresponds to each lead terminal provided in a container that accommodates the semiconductor chip. a plurality of pads whose surfaces are respectively connected to the inner ends of the lead terminals; and a plurality of pads which are connected to each of these pads and which are formed to protrude on the film and the punched portion and whose tips have corresponding element electrodes of the semiconductor chip. It has a plurality of pattern wirings each connected to.

〔実施例〕〔Example〕

次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.

第１図（ａ）、（ｂ）はそれぞれ本発明の第１の実施例
を示す平面図及び断面図である。FIGS. 1(a) and 1(b) are a plan view and a sectional view, respectively, showing a first embodiment of the present invention.

容器１には、リード端子１１が多数配列され、中央部に
は半導体チップ３が搭載固定される。A large number of lead terminals 11 are arranged in the container 1, and a semiconductor chip 3 is mounted and fixed in the center.

半導体チップ３には、半導体素子とこれら半導体素子に
接続された多数の素子電極が配列されている。In the semiconductor chip 3, semiconductor elements and a large number of element electrodes connected to these semiconductor elements are arranged.

フィルム４は、フィルムキャリアから分離されたもので
、中央部が半導体チップ３の外形寸法とほぼ同じかやや
大きい寸法で打ち抜かれ、片面には、容器１の各リード
端子１１に対応する位置にこれら各リード端子１１の内
側端と表面がそれぞれ接続するパッド５．と、これらパ
ッド５．にそれぞれ接続しかつ打ち抜かれた部分に突出
し先端が半導体チップ３の各素子電極とそれぞれ接続す
るパターン配線５とが設けられている。The film 4 is separated from the film carrier, and the center part is punched out to have dimensions that are approximately the same as or slightly larger than the external dimensions of the semiconductor chip 3. On one side, these are placed at positions corresponding to the respective lead terminals 11 of the container 1. Pads 5 to which the inner ends and surfaces of each lead terminal 11 are respectively connected. And these pads 5. Pattern wirings 5 are provided in the punched portions, and the protruding tips are connected to the respective element electrodes of the semiconductor chip 3, respectively.

パターン配線５及びパッド５ｐは、まず、フィルムキャ
リアの連続した状態でフィルム４上に形成され、次に半
導体チップ３の各素子電極がフィルムキャリアのパター
ン配線５と接続される。この状態で半導体チップ３の電
気試験、ＢＴスクリーニング等を実施することができる
。この状態の１コマ分を第２図に示す。The pattern wiring 5 and the pad 5p are first formed on the film 4 in a continuous state of the film carrier, and then each element electrode of the semiconductor chip 3 is connected to the pattern wiring 5 of the film carrier. In this state, electrical tests, BT screening, etc. of the semiconductor chip 3 can be performed. One frame in this state is shown in FIG.

電気試験等が済んだ半導体チップ３は、接続されている
パターン配線５．パッド５１．、フィルム４と共にフィ
ルムキャリアから切離される。The semiconductor chip 3 which has undergone electrical tests etc. is connected to the pattern wiring 5. Pad 51. , and the film 4 is separated from the film carrier.

一方、容器１の中央部とリード端子１１の内側端には低
温はんだめっき等が施こされており、この容器１の中に
フィルムキャリアから切離された半導体チップ３等を搭
載しヒーターブロック等により容器１．半導体チップ３
等を加熱圧着して半導体チップ３の固定、及びパッド５
．とリード端子１１との接続を同時に行う。On the other hand, the central part of the container 1 and the inner ends of the lead terminals 11 are plated with low-temperature solder, etc., and the semiconductor chips 3 etc. separated from the film carrier are mounted inside this container 1, and the heater block etc. Container 1. semiconductor chip 3
etc. to fix the semiconductor chip 3 and pad 5.
．． and the lead terminal 11 are connected at the same time.

最後にシームウェルド法等により蓋２が容器１に取付け
られ半導体装置が形成される。Finally, the lid 2 is attached to the container 1 by seam welding or the like to form a semiconductor device.

第３図は本発明の第２の実施例を示す断面図である。FIG. 3 is a sectional view showing a second embodiment of the invention.

この実施例は、プラスティックＰＧＡの容器１ａを使用
し、内部の半導体チップ３全体をシリコーン樹脂７で被
い、接着剤にて金属のＭ２．で封止したものである。In this embodiment, a plastic PGA container 1a is used, the entire internal semiconductor chip 3 is covered with a silicone resin 7, and a metal M2. It is sealed with.

なお、フィルム４はポリイミド樹脂でつくられることが
多く、この場合、半導体チップ３の固定、パッド５ｐ、
リード端子１１．１１．間の接続等は２００℃を越えな
い温度で行なわれる。Note that the film 4 is often made of polyimide resin, and in this case, it is used for fixing the semiconductor chip 3, pads 5p,
Lead terminal 11.11. Connections between the two are made at a temperature not exceeding 200°C.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、容器に設けられた各リー
ド端子に対応するフィルムキャリアのフィルム上の位置
にこれらリード端子をそれぞれ接続するパッドを形成す
ることにより、ワイヤボンディングのようなボンディン
グずれ、打ち間違いかなくなるので、歩留り、信頼性、
ボンディング性を高めることができ、フィルムキャリア
状態で出荷する場合でもユーザー側にＯＬＢ等の設備を
導入しなくても容器に組立てることができるので、適用
範囲を拡大することができる効果がある。As explained above, the present invention prevents bonding misalignment such as wire bonding by forming pads for connecting the lead terminals at positions on the film of the film carrier corresponding to the respective lead terminals provided on the container. Since there are no typos, yield, reliability,
Bonding properties can be improved, and even when shipped in the form of a film carrier, it can be assembled into a container without introducing equipment such as an OLB on the user side, which has the effect of expanding the scope of application.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図（ａ）、（ｂ）はそれぞれ本発明の第１の実施例
を示す平面図及び断面図、第２図は第１図の実施例のフ
ィルムキャリア状態の１コマ分の平面図、第３図は本発
明の第２の実施例を示す断面図である。 １．１．・・・容器、２．２ａ・・・蓋、３・・・半導
体チップ、４・・・フィルム、５・・・パターン配線、
５ｐ・・・パッド、６・・・枠、７・・・シリコーン樹
脂、１１゜Ｊｌ、・・・リード端子。 ｆＮＢ″：４− ｉ　ｌ　図 茅　２　図 茅３　哲FIGS. 1(a) and (b) are a plan view and a sectional view showing a first embodiment of the present invention, respectively, FIG. 2 is a one-frame plan view of the embodiment shown in FIG. 1 in a film carrier state, FIG. 3 is a sectional view showing a second embodiment of the present invention. 1.1. ... Container, 2.2a... Lid, 3... Semiconductor chip, 4... Film, 5... Pattern wiring,
5p...pad, 6...frame, 7...silicone resin, 11°Jl,...lead terminal. fNB'': 4-i l Fig. 2 Fig. 3 Tetsu

Claims (1)

【特許請求の範囲】[Claims] 　半導体素子とこの半導体素子に接続された複数の素子
電極とを備えた半導体チップと、中央部が前記半導体チ
ップの外形寸法とほぼ同じかやや大きい寸法で打ち抜か
れたフィルムキャリア用のフィルムと、前記半導体チッ
プを収納する容器に設けられた各リード端子に対応する
前記フィルム上の位置に形成され表面が前記リード端子
の内側端とそれぞれ接続する複数のパッドと、これら各
パッドとそれぞれ接続し前記フィルム上及び前記打ち抜
かれた部分に突出して形成され先端が前記半導体チップ
の対応する素子電極にそれぞれ接続する複数のパターン
配線とを有することを特徴とする半導体装置。a semiconductor chip comprising a semiconductor element and a plurality of element electrodes connected to the semiconductor element; a film for a film carrier having a center portion punched out with dimensions approximately equal to or slightly larger than the external dimensions of the semiconductor chip; a plurality of pads formed at positions on the film corresponding to respective lead terminals provided in a container for storing semiconductor chips, the surfaces of which are respectively connected to the inner ends of the lead terminals; A semiconductor device characterized in that it has a plurality of pattern wirings formed protrudingly on the top and in the punched portion, the tips of which are respectively connected to corresponding element electrodes of the semiconductor chip.
JP62066148A 1987-03-20 1987-03-20 Semiconductor device Pending JPS63232437A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62066148A JPS63232437A (en) 1987-03-20 1987-03-20 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62066148A JPS63232437A (en) 1987-03-20 1987-03-20 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS63232437A true JPS63232437A (en) 1988-09-28

Family

ID=13307491

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62066148A Pending JPS63232437A (en) 1987-03-20 1987-03-20 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS63232437A (en)

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