JPS63231800A - Sample and hold circuit - Google Patents

Abstract

PURPOSE:To prevent a capacitor from increasing in capacity and to facilitate the IC-implementation of a circuit by adding a transistor (Tr) which is cut off at timing similar to active addition, using the collector current of this Tr, and reducing the charging current of a hold capacitor only in holding operation. CONSTITUTION:A switch SW1 connected to the constant current source Is of a sample holding circuit is opened at the moment of transition to the holding operation to delay the cutoff operation of a Tr Q5 by the same timing with a Tr Q4 by the influence of a parasitic capacitor C2. At this time, the collector current I2 of the Tr Q5 is sent back by a current mirror circuit 3 and supplied to a switch SW2. Further, the switch SW2 is closed when the switch SW1 is opened. Then the output current I3 (=I2=I3) of the current mirror circuit 3 is subtracted from the hold capacitor C1 and the charging current of the capacitor C1 is supplied in holding operation to prevent the capacitor C1 from increasing in capacity.

Description

[Detailed Description of the Invention] [Object of the Invention] (Field of Industrial Application) The present invention relates to a sample and hold circuit, and in particular to an IC.
This invention relates to a sample-and-hold circuit that is suitable for internal integration and has no hold errors.

(Prior Art) FIG. 4 is an example of a conventional sample Φ hold circuit. Ql and Q2 are a differential transistor pair whose emitters are commonly connected. The collectors of these transistors Ql, Q2 are connected to transistors Q3, Q4, . Resistance 1.
An active load consisting of 几2 is connected. The collector and base of the transistor Q2 are exposed, forming a voltage follower connection. The transistor Ql,
A bias current Is is connected to the common emitter of Q2 via switch line 1. Input terminal 1 is connected to the base of the transistor Q1, and connected to the base of the transistor Q2. A hold capacitor C1 is connected to the output terminal 2.

The sample contention hold circuit configured in this manner is widely used. The operation of this circuit will be described below. FIG. 5 shows the operating states and waveforms of each part of the sample-and-hold circuit.

When the switch 8Wl is closed, the sample-and-hold circuit performs a through operation as a voltage follower amplifier, and holds the voltage value at the moment when the switch SWI changes from closed to open. At this time, since a parasitic capacitance cp exists in the pace portion of the transistor Q3, the transistor Ql.

Compared to Q2, transistor Q3. Q4 cutoff will be delayed.

In other words, even if the hold operation is performed at the timing shown in FIG. 5(a), the collector current of transistor Q4 will be as shown in FIG.
As shown in C), it does not reach O immediately, but decreases exponentially. This electrician 1 is the hole (3).

Since the capacitor C1 is charged during the hold operation, a hold error voltage ■ is generated (FIG. 5(d)). This error voltage V
is given by the following formula.

That is, when the capacitor C1 is small, the hold error V appears more prominently. Particularly in the case of a sample-and-hold circuit with a built-in IC, the capacitor C1 cannot be made large, so hold errors are a problem.

(Problems to be Solved by the Invention) As mentioned above, in the conventional sample-and-hold circuit shown in FIG. This has the disadvantage that there is a delay, which causes an error in the hold voltage.

An object of the present invention is to provide a sample-and-hold circuit that has no error in hold voltage and is optimal for built-in IC.

[Structure of the invention]

(Means for solving the problem) The present invention adds a transistor to the active load so as to cut off at the same timing, and holds the collector current of this transistor using a current mirror circuit. Only during operation, the charging current of the hold capacitor C1 is subtracted.

(Function) With the above-described configuration, it is possible to cancel out the current that attempts to charge the capacitor C1 at the moment of hold, which would have generated the error voltage V in the conventional circuit. As a result, it is possible to prevent the error voltage V of the hold voltage from occurring, and it is possible to realize sample and hold without any difference.

(Example) An example of the present invention will be described below with reference to the drawings. FIG. 1 shows an embodiment of the invention.

In addition to the conventional sample-and-hold circuit configuration shown in FIG. 4, the present invention adds a transistor Q5 whose base is connected to the common pace of the active load (Q3-Q4). The emitter resistance R3 of this transistor Q5 (=几2=几1
) to VOO. Further, in addition to the transistor Q5, its current input terminal is connected to the transistor Q5.
A current mirror circuit 3 connected to the collector of No. 5 is also added. The current output terminal of this current mirror circuit 3 is connected to the sample and hold output terminal 2 via a newly provided switch 8W2. Here, the switch SW2 operates in the opposite manner at the same timing as the switch 8W4. That is, when switch SWI is open, switch 8W2 is closed, and when switch SW1 is closed, switch SW2 is closed.
becomes open. Therefore, during the through operation, the switch 8W2 is open, so that the influence of the collector current l2 (=11) of the transistor Q5 does not appear on the output terminal 2. In other words, it operates exactly like a conventional circuit.

The operation of the sample and hold circuit shown in FIG. 1 will be explained below with reference to the waveform diagram shown in FIG. When the switch SWI opens at the moment when the hold operation is started, the cutoff 7 of the transistor Q5 is also delayed by the same timing as that of the transistor Q4 due to the influence of the parasitic capacitance Cp. At this time, the collector current (2) of the transistor Q5 is turned back by the current mirror circuit 3 and guided to the switch SW2. At this time, the switch SW2 is closed at the same time as the switch SWI is opened, so the output current I3 (=
I2 = II) from the hold capacitor c1.

In this way, the moment the hold operation starts, the capacitor C
The current L (Fig. 2 (d)) that attempts to charge the electric current 3 that is equal in absolute value and opposite in polarity to the electric current L (Fig. 2 (d))
e) ), the hold error voltage appearing at the output terminal 2 can be canceled out (FIG. 2(f)). In this embodiment, the switch SW2 is provided on the output terminal side of the current mirror circuit 3, but it goes without saying that even if it is provided on the input side, the same operation will be achieved.

FIG. 3 shows the switches swl, SW2. An example of a specific configuration of the current mirror circuit 3 is shown. As shown, the current mirror circuit 3 includes transistors Q8. Q9. Resistance 5. The switch 8W2 is configured using a transistor Q7 that cuts off the transistor Q8 by clamping the emitter potential of the transistor Q8 with its own emitter potential. The base of this transistor switch Q7 forms a current source Is together with the resistor 4, and is commonly connected to the base of the transistor Q6 which also serves as the switch SW1.

and the transistor Q6. By connecting the switch changeover control terminal 4 to the common base of C7, the sample and hold operation can be controlled using this same control terminal 4.

〔Effect of the invention〕

As described above, according to the present invention, generation of error voltage can be prevented without increasing the capacitance of the hold capacitor. Therefore, it is possible to provide a sample-and-hold circuit that is optimal for built-in IC.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a sample-and-hold circuit according to an embodiment of the present invention, FIG. 2 is a waveform diagram for explaining the operation of the embodiment, and FIG. FIG. 4 is a circuit diagram showing an example of a specific configuration, FIG. 4 is a configuration diagram of a conventional circuit, and FIG. 5 is a waveform diagram for explaining the operation of the conventional circuit. Q1-Q9...Transistor, R1-R6...
Resistor, C1...Hold capacitor, Cp...
Parasitic capacitor, SWI, sw2...switch, I
s...constant current source, 1...input terminal, 2...
- Output terminal, 3... Current mirror circuit, 4... Switch switching control input terminal. Agent Patent Attorney Nori Chika Yudo Hiroshi Uji

Claims (1)

[Claims] a first transistor whose base is connected to the input terminal; a second transistor forming a differential pair with the first transistor and whose base and collector are connected; and the first and second transistors. an active load consisting of a third and fourth transistor pair whose collectors are connected to the respective collectors; a fifth transistor whose base is connected to the common base of the third and fourth transistors; a current mirror circuit in which a current input terminal is connected to the collector of the transistor No. 5 and a current output terminal thereof is connected to the base of the second transistor; and a common emitter of the first and second transistors and a current source. a first switch that opens and closes the connection; and a second switch that is provided in a current path from the collector of the fifth transistor to the base of the second transistor and that opens and closes in conjunction with the first switch. , and a capacitor connected between the second transistor and a reference potential.