JPH01109806A - Sample-and-hold circuit - Google Patents

Abstract

PURPOSE:To eliminate droop due to a bias current by supplying an operating current of a differential pair in the hold mode from a bias voltage source via a diode switch and supplying the operating current to the other from a power line. CONSTITUTION:In reaching the hold mode, the emitter follower operation is attained in the sample mode, and a transistor(TR) Q12 charging a hold capacitor CH is interrupted by the conduction of a diode D14, the charging is stopped and an instantaneous value of a potential Vin+VD of the capacitor CH is held. The operating current of the TR Q15 is supplied from a bias voltage terminal 17 via the diode D14 and the operating current of the TR Q16 is supplied from a power line 15. Thus, the droop rate is reduced remarkably to 2/5 of that of a conventional circuit.

Description

Detailed Description of the Invention (Field of Industrial Application) The present invention relates to a sample-and-hold circuit that samples and holds instantaneous values of analog signals, and particularly to a sample-and-hold circuit that handles high-speed analog signals and is suitable for integrated circuit implementation. .

(Prior Art) Conventionally, there is a circuit as shown in FIG. 2 as this type of sample and hold circuit, and its operation will be described below.

Now, in FIG. 2, sample and hold control input terminals 3 and 4 (normally, input terminal 4 receives an inverted input of a rectangular wave whose phase is 180 degrees different from input terminal 3).
The control input voltages SH and SH are respectively in a high level state “
When the transistor is in the low level state (hereinafter simply referred to as "H" and "L"), the transistor Q of the differential transistor pair Q, , Qs and the differential transistor pair Q, , Q7 ,, Qy are both in conduction state, transistors Q, , Q6 are both in (!r state), and this rgJ#
The state of i is in sample mode. That is, the analog input signal (2) inputted from the input terminal 1 is applied to the base of the transistor Q1, and Ql operates as an emitter follower. A diode D connected to the emitter of Q operates as a level shift circuit, and its current is supplied by a constant current source I4. The pace emitter voltage of Ql is V a m l , and the diode DI to D3 is
Assuming that the forward voltages of are all equal and set as VD, the voltage applied to the base of transistor Q2 is V+-Va
g+ +3V, the current that is the sum of the current of constant current source I and the operating current of Q is passed through Q4 to constant current source ■1
The current will be . The hold capacitor Ji CH is connected to the emitter and the Ql that performs emitter follower operation is the above V + - V
The CM is charged by receiving a voltage of sg+ + 3 Vp as the base. The pace emitter voltage of Ql at this time is VH2
Then, the potential of CM is ■, -(Vms+ +Vsg*
) +3Vo Tonari, V,, the potential is 3 V at 1°
o (Vlllll +VB12) Level shifted and followed. Furthermore, as shown in FIG. 2, an emitter follower circuit consisting of a transistor Qa whose base is connected to the emitter of Ql and a constant current source Is is connected,
When the output signal Va is taken out from the emitter of Q8, that is, the output terminal 2, when the pace emitter voltage of Q8 is V□8, ■. is V+-(Vsa+ +Vam
2+■s*s)+3Vo. Here, Q r +
If the current density of each element is set to be equal between Q 21 Q s +D1 and Shiri, Va*+ +Vl11
2 +V++ga = 3V.

As a result, it becomes possible to set V 1fi=V o. That is, in the sample mode, the output signal Vo equally follows the input signal v1m.

Next, if SH and SH are "Lm and uHn, respectively, then Q
4. Q7 are both cut off, Qs and Q.

Q7. are both conductive, and the circuit is in hold mode. In other words, Q7. The charging operation of CM is stopped because Ql is cut off, and the transistor Q whose base is connected to one end of C11 that is not the ground side.

starts operating, and the values of the potentials V, . . . +Vo of C□ are held. At this time, the currents of the constant current sources It, It are supplied from the constant current source I via the diodes D4, Qs, and Q6, and from the power supply line 5 via Q, Qs, and Qa.

As described above, in the sample mode, the input signal v1. The output signal Vo follows (VO==v,,)L,
When the state is switched to the hold mode, the function of the sample and hold circuit to hold the instantaneous value of V l m is executed.

(Problems to be Solved by the Invention) In the conventional sample-and-hold circuit described above, in the hold mode, the output signal V0 becomes I m due to the bias current (base current) I8 of the transistor connected to the hold capacitor CM. It exhibits the so-called drogue characteristic, which shows a gradual decreasing tendency at a ratio of /Co.

On the other hand, when handling high-speed input signals, it is generally necessary to set the operating current of the element to a large value, and the bias current also becomes large, so in the conventional example shown in Figure 2, the droop becomes too large. , the sample and hold circuit loses its original holding function.

In addition, in order to reduce the droop, the bias current is set to 1. A junction field effect transistor or a transistor with a large current amplification factor is often used as the transistor connected to the hold capacitor C11 with the intention of reducing the In addition, a process is required to fabricate the above-mentioned special transistors at the same time, and the process becomes complicated and expensive just to deal with the droop problem.

Furthermore, there are cases where complicated and expensive circuit technology is used, such as using a Darlington connection type for the transistor connected to C), or installing a new bias current compensation circuit, or when increasing the value of CM. Even considering that integrated circuit processes are not required, they are inherently unsuitable for high speeds and create problems in that the circuit response cannot follow rapidly changing input signals in sample mode.

<Means for Solving the Problems> The sample and hold circuit of the present invention includes a current mirror circuit, a first transistor having a base to which an input signal is input and a collector connected to a diode-type connection of the current mirror circuit; A first transistor comprising a single or plural diodes or diode-connected transistors, the cathode of which is connected to the emitter of the first transistor, and the anode of which is connected to the output point of the current mirror circuit.
a second diode element consisting of one or more diodes or diode-connected transistors whose anode side is connected to a bias voltage and whose cathode side is connected to the anode side of the first diode element; a first differential circuit in which a collector of a transistor is connected to an emitter of the first transistor and a collector of the other transistor is connected to an anode side of the first diode element; and a base of the first diode element; a second transistor connected to the anode side, the collector connected to the power supply, and the emitter connected to the hold capacitor; the collector of one transistor is connected to the power supply and the collector of the other transistor is connected to the emitter of the second transistor; and a second differential circuit.

(Function) The present invention switches between sample mode and hold mode using an analog switch in which the operating current is controlled by a differential switch as an input circuit, and in the hold mode, the operating current of one differential pair is controlled by a diode. By supplying one voltage from the bias voltage source via a switch and the other directly from the power supply line, the hold capacitor charging transistor is cut off, thereby eliminating droop caused by the bias current.

(Example) Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

Now, the input voltages SH and SH of the sample and hold control input terminal 13 and its inverted input terminal 14 are respectively “H”.
", "L' state, that is, when the state of this circuit is in the sample mode, the transistor Q + 4 T Q l? of the differential transistor pair Q H4, Q r and the differential transistor pair Q161Q17. are both in a conductive state, transistors Q ls+Q 16 are both in a cut-off state, and the analog signal v1 . is applied to the base of transistor Qll, and Q++ acts as an emitter follower. The diode D or I)ti connected to the Qth emitter is the transistor Q
The output current of the current mirror circuit consisting of +9+Q20 becomes its operating current and operates as a level shift circuit.

Transistor Q12, whose emitter is connected to hold capacitor Cn, operates as an emitter follower and charges 0.4 If we can assume that all are equally ■ゎ, then the potential of C8 is V, , -(V, , .).

+ V sm+2> +3 V o can be set,
vl, 3Vo (V*t+++Vsg+2
) to follow the input. Furthermore, the first
As shown in the figure, an emitter follower circuit consisting of a transistor Q +a whose base is connected to the emitter of Q10 and a constant current source Its is added, and the output signal Vo is taken out from the emitter of Q +s, that is, the output terminal 12. , Q +6 base-emitter voltage fi' V
eg ls Teto Vo =Vt-(V
mg+++Vsatt+Vsgta) + 3 Vo. Here, if the current density of each element of Q mouth + Q 11 + Q 1m and D day or Dlm is set equal, V
B11+V@H2#2VD.

Vsg+++Vsg+z+Veg+a#3 Vo ToT
Therefore, the potential of CM is V+−+Vo
, output voltage■. =v, 11, and each follows the input signal ■1 in the sample mode.

When SH and SH are respectively L” and “H”, that is, Q
When Q141Q17 are both cut off and Qls+QI6 are both turned on, this circuit enters the hold mode.

In sample mode, it operates as an emitter follower,
Q+2 that was charging CH is diode DI4
Due to the conduction of C, it is cut off and the charging operation is stopped.
H potential V1. +V. The instantaneous value of is held. At this time,
The condition for turning off Q12 is the potential V of CM.
, , +V, plus the pace emitter voltage of Q12, V t, +2 V. That is, the base potential of Q l 2 changes from the potential of the bias voltage terminal 17 to the diode D1.
Since it is sufficient that the potential is greater than the potential obtained by subtracting the forward voltage of 4, the potential of bias voltage terminal 17 is set to vll, and the forward voltage of diode DI4 is Q ll+ Q + □, D+
+ or DI3 with the current density equal to V, then V s+ Vo < V t-+ 2 Vo
becomes. - As an example, assuming that vo takes a value in the range 0 to -2 [v], Vo is generally 0.7 to 0.8
(V), a value of about O[:V] is sufficient for VB+.

Alternatively, it is also possible to make the bias voltage terminal 17 common to the power supply line 15 and configure DI4 with a plurality of diodes to satisfy the above conditions.

The operating current of QL51Q16 in the conducting state is Q15
is supplied from the bias voltage terminal 17 via D14, and Q+6 is supplied from the power supply line 15.

As shown in FIG. 1, in an example in which an emitter follower is practically added to the output section to drive a load, transistors Q1. If we assume that the leakage current of the hold capacitor Mcll can be ignored and the current amplification factor of Q +a is hpg, then
Drupe Plate'U et al becomes JJ-L/CH. On the other hand, in the conventional example pt, transistor Q3. Assuming that the current increase rate of Q8 is hFl, 1H'L - I I 10I ±I /C
, 4 fcdt h□, the value of each constant current source is temporarily set as I r = I 2 =
If I set 5==i,,,I,=2・I4, Tsukuda=
5. Becomes tan/co.

Since the droop rate of the embodiment shown in FIG.
2hpg According to the circuit of the embodiment, it is possible to significantly reduce the droop rate to "L" of the conventional example.

(Effects of the Invention) As explained above, according to the present invention, in a circuit that samples the instantaneous value of an analog signal and further holds it, that is, a sample-and-hold circuit, the sampling This can be maintained without compromising the time tracking speed and without requiring a complicated or expensive integrated circuit manufacturing process to simultaneously manufacture special elements such as junction field effect transistors. This has the effect of making it possible to improve the characteristics by more than twice that of conventional circuits.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing one embodiment of the present invention, and FIG. 2 is a circuit diagram of a conventional example. 1.11...Input terminal, 2.12...Output terminal, 3
, 4゜13, 14... Control input terminal, 5, 6, 1
5.16...Power line, 17...Bias voltage terminal,
Q I"Qs + Qz, Q12゜Q14~Q2o...
・Transistor, D, ~D4, D+1~D14
...Diode, CH...Hold capacitance, It~I
4. Ill~Ill... Constant current source.

Claims (1)

[Claims] a current mirror circuit; a first transistor having a base to which an input signal is input and a collector connected to a diode-type connection point of the current mirror circuit; a cathode side connected to the emitter of the first transistor and an anode side connected to the current mirror circuit; a first diode element consisting of a single or a plurality of diodes or diode-connected transistors connected to an output point of the circuit; an anode side connected to a bias voltage and a cathode side connected to the anode side of the first diode element; a second diode element consisting of a single or a plurality of diodes or diode-connected transistors; the collector of one transistor is connected to the emitter of the first transistor, and the collector of the other transistor is connected to the first diode element; a first differential circuit connected to the anode side of the first diode element; a second transistor having a base connected to the anode side of the first diode element, a collector connected to a power supply, and an emitter connected to a hold capacitor; and a second differential circuit in which a collector of one transistor is connected to a power supply and a collector of the other transistor is connected to an emitter of the second transistor.