JPS63263699A - Sample holding circuit - Google Patents

Abstract

PURPOSE:To maintain the holding function of a sample holding circuit by interrupting a prescribed transistor (TR) in a holding mode to remove droop due to bias current. CONSTITUTION:When a control input voltage SH and the inverse of SH are respectively 'L' and 'H', i.e. when both TRs Q14, Q17 are interrupted and TRs Q15, Q16 are conducted, the device is set up in a holding mode. In a sampling mode, emitter follower operation is executed, a TR Q12 changing a capacitor CH is interrupted by the connection of a diode D14 to stop its charging operation and the instantaneous value of the CH is held. Thereby, the operating current of the conductive TR Q16 is supplied from a power supply 15 and the operating current of the TR Q15 becomes the output current of a current mirror circuit consisting of TRs Q19, Q20 and a reference current for the current mirror circuit which flows in the route of a TR Q11 and a diode D14. Thereby, the voltage VCE of the TR Q15 is boosted, the base voltage of the TR Q12 is dropped and the TR Q12 is interrupted.

Description

Detailed Description of the Invention (Field of Industrial Application) The present invention relates to a sample-and-hold circuit that samples and holds the instantaneous value of an analog signal, and particularly relates to a technique that handles high-speed analog signals and is effective when applied to integrated circuits. .

(Prior Art) Conventionally, there is a circuit as shown in FIG. 2 as this type of sample and hold circuit, and its operation will be described below.

Now, in FIG. 2, sample-and-hold control input terminals 3 and 4 (normally, an inverted input of a chalcopyrite rectangular wave having a phase difference of 180 degrees with respect to input terminal 3 is input to input terminal 4.

), the differential transistor pair Qa+Qs and the differential transistor pair Qa+Qs and the differential transistor pair Qa+Qs and Transistor pair Q6. Of transistor Q7, transistor Q4. Both transistors Q7 are in a conductive state, transistors Qg and Q6 are both in a cut-off state, and the state of this circuit is in the sample mode. That is, the analog input signal Via input from input terminal 1 is applied to the base of transistor Q1, and Ql is eQ which operates as an emitter follower.
Diode D connected to the emitter of t! D3 operates as a level shift circuit, and its current is connected to a constant current source I.
Supplied by 4. The pace emitter voltage of Ql is V
Assuming that the forward voltages of BR1 + diodes Ds to D3 are all equal, v! 1, the voltage applied to the base of transistor Q2 is Vln-Vaε1+3V! l
becomes. A current obtained by adding the current of the constant current source 14 and the operating current of Ql becomes the current of the constant current source 11 via Q4.

Q2, which has a hold capacitor C, connected to its emitter and operates as an emitter follower, has the above V 1n -VBI, 1+ 3
Vll f) Receives voltage and charges CH. If the pace emitter voltage of Q2 at this time is set as VBε2, the potential of C is Vln - (Vaat +Vap-2)
+3VD, the potential is 3V with respect to Vln! + -(
VBEI +Vap2) Level shifted and followed. Furthermore, as shown in FIG. 2, an emitter follower circuit consisting of a transistor Q8 whose base is connected to the emitter of Q2 and a constant current source I3 is connected so that the output signal vo is taken out from the emitter of Qa, that is, the output terminal 2. In this case, the pace emitter voltage of Qa is VB+!
When 8, VO is Vln-(Vaas +Vap:2+V
aag)+3Vn. Here, Q1+ 02 +Q
If the current densities of each element from a + Ds to D3 are set to be equal, Vaas +Vap2+Var:
g #3v! 1, so that V xo
It becomes possible to set #V o. That is, in the sample mode, the output signal Vo follows the input signal Vln equally.

Next, when SH and SH are 11, 1'' and "H", respectively, Q4 and Q7 are both cut off, and Q bow wQ6 is both turned on, and the circuit is in hold mode. That is, Q7 and Q2 Since C is cut off, the charging operation of C is stopped, and the transistor Q:1 whose base is connected to one end of CH other than the ground side starts operating, increasing the potential of CH
The value of 1[l+v, is retained. At this time, constant current source t,
l The current of I2 is from constant current source 4 via diode D4, Qs, and Qa, and Qa and Q! 1. It is supplied from power supply 115 via Q6.

As mentioned above, as shown in FIG. 2, in the sample mode, the output signal vo follows the input signal V1n (Vo
=V1n) When the state is switched to L and hold mode, the function of the sample and hold circuit to hold the instantaneous values of V and Il is executed.

(Problems to be Solved by the Invention) In the conventional sample-and-hold circuit described above, in the hold mode, the bias current (base current) of the transistor connected to the bold capacitor CH! Due to B, the output signal vo gradually decreases at a rate of IS/CH.
It exhibits so-called droop characteristics.

When handling high-speed input signals, it is generally necessary to set the operating current of the element to a large value, so the bias current also becomes large, and in the conventional example shown in Figure 2, the droop becomes too large and the sample-and-hold circuit is will lose its retention function.

Also, in order to reduce the droop, the bias current I1
1, a junction field effect transistor or a transistor with a large current amplification factor is often used as the transistor connected to the hold capacitor C. However, if a transistor of a different type than other parts is used in one part, in addition to the standard integrated circuit process, a process to simultaneously manufacture the above-mentioned special transistors will be required. This results in the disadvantage that the integration process becomes complicated and expensive.

In order to improve the droop characteristics, the transistor connected to the hold capacitor CH may be connected to Darlington, or circuit techniques such as installing a new bias current compensation circuit may be used, or the value of the hold capacitor CH may be increased. Countermeasures such as those that do not require complex and expensive integrated circuit processes are possible. However, the employment of such a circuit is essentially not suitable for increasing the speed of circuit response, and causes a problem that the circuit response cannot follow a rapidly changing input signal in the sample mode.

(Means for Solving the Problems) The sample and hold circuit of the present invention includes a current mirror circuit, an analog input signal to be sampled and held is input to the base, and the collector is connected to the diode type connection point of the current mirror circuit. a first transistor;
a first diode element consisting of a single or plural diodes or diode-connected transistors whose cathode side is connected to the emitter of the first transistor and whose anode side is connected to the output point of the current mirror circuit; a second diode or a diode-connected transistor whose anode side is connected to the emitter of the transistor and whose cathode side is connected to the anode side of the first diode element; and a collector of one transistor is connected to the emitter of the first transistor. and a first differential circuit in which the collector of the other transistor is connected to the anode side of the first diode element, the base is connected to the anode side of the first diode element, the collector is connected to a power supply, and the emitter is connected to the anode side of the first diode element. a second transistor connected to a hold capacitor; and a second differential circuit in which a collector of one transistor is connected to a power supply and a collector of the other transistor is connected to an emitter of the second transistor. There is.

(Function) In the present invention, an analog switch in which the operating current is controlled by a differential switch is used as an input circuit to switch between the sample mode and the hold mode, and the operating current of one differential pair in the hold mode is , the sum of the reference current of the current mirror circuit flowing in the path from the first transistor to the second diode (or diode-connected transistor) and the output current of the current mirror circuit is supplied, and the second transistor (hold capacitance By cutting off the charging transistor (charging transistor), droop caused by bias current is eliminated.

(Example) Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram showing one embodiment of the present invention.

Now, the input voltages SH and SH of the sample hold control input terminal 13 and its inverted input terminal 14 are respectively "H".
, in the "H" state, that is, when the state of this circuit is in the sample mode, the differential transistor pair Q14. Q□5 and differential transistor pair Q16゜(hy, transistor (h41 Q*y) are both in a conductive state, transistor (hs+ The diodes D11 to D13 connected to the emitter of aQtr are applied to the base of hl, and Qll operates as an emitter follower.The output current of the current mirror circuit consisting of transistors Q1e*Q2o becomes the operating current of the diodes D11 to D13, which operate as a level shift circuit. .Hold capacitance C at the emitter.

The transistor Q12 to which Q11 is connected operates as an emitter follower and charges CH.
If we can assume that the forward voltages of IB 12 and diodes D11 to D13 are all equal vll, then the potential of cH is V5a-(Var+sx+Vaa*z) +3V
! 1 Too <, Nido tjE deki, Vmu. For “C3V”
The level is shifted by n-(Var:s1+Vaat2> to follow the input.Furthermore, as shown in FIG.
An emitter follower circuit consisting of a transistor Q1a whose base is connected to the emitter of Qja and a constant current source 113 is added, and an output signal v is output from the emitter of Qja, that is, the output terminal 12.

If the pace emitter voltage of Qlg is vaala, then VO=VI11-(V
aa*x+Vat*2+Vaasa) + 3 VB
Tona 4, ,: Kode Qllll Q121 Q1a+
If the current density of each element from Dlt to D13 is set equal, Vaa*1 + V@ε2nd #2 Vn + vBpt
lj + vllE12 + vBa18 Cape 3 VF6, therefore, the potential of CH is v Ia + V1
1, the output voltage V O = V 111, and each follows the input signal Vta in the sample mode.

When SH and SH are "Ln" and "H", respectively, that is, both Q141 and Q17 are in the cut-off state, QlN.

When Q16 are both conductive, the circuit is in hold mode. In the sample mode, Qs2, which operates as an emitter follower and was charging CM, becomes cut off due to the conduction of diode D14, stopping the charging operation, and the instantaneous values of the potentials v and Il+vB of C and 4 are held. Ru. That is, the operating current of Q16 in the conducting state is supplied from the power supply 15, and the operating current of QJg is Q t
The current is the sum of the output current of the current mirror circuit consisting of p + Q 20 and the reference current of the current mirror circuit flowing through the path of Q1111h4. Therefore, the VC1=voltage of the transistor (ha) increases, and eventually the base voltage of the transistor (h2) drops, and the voltage of the transistor (h2) increases.
2 is in a cutoff state.

As shown in Figure 1, in an example in which an emitter follower is added to the output section for practical purposes to drive a load, the current amplification factor of Qsa is , transistor Q
3. Assuming that the current amplification factor of Qs is hpa, let us assume that the value of each constant current source is l, = 12 = 13
If we set =I = 2.14, then it becomes. Since the droop rate of the embodiment shown in FIG. 1 is as follows, the circuit of this embodiment has true playability.

(Effects of the Invention) As explained above, according to the present invention, in a circuit that samples the instantaneous value of an analog signal and further holds it, that is, a sample-and-hold circuit, when integrating circuits are taken into consideration, Without compromising tracking speed and requiring a complex or expensive integrated circuit process to simultaneously fabricate special elements such as junction field effect transistors, the retention characteristics can be improved compared to conventional processes using a standard process. This has the effect of making it possible to improve the performance by more than twice that of the conventional circuit.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing one embodiment of the present invention, and FIG. 2 is a circuit diagram of a conventional example. 1.11...Input terminal, 2.12...Output terminal, 3
．． 4゜13, 14... control input terminal, 5.6, 15.
16...Power line, Qs ~ Qa, Qss ~ Qzo-
) transistor, D1~D4 + D11~D14・
・・Diode, C, ・・Hold capacitance, 11 to 14
slSj~1鵞3... Constant current source.

Claims (1)

[Claims] a current mirror circuit; and a first circuit whose base is input with an analog input signal to be sampled and held and whose collector is connected to a diode-type connection point of the current mirror circuit.
a first diode element consisting of one or more diodes or diode-connected transistors whose cathode side is connected to the emitter of the first transistor and whose anode side is connected to the output point of the current mirror circuit; a second diode or diode-connected transistor whose anode side is connected to the emitter of the first transistor and whose cathode side is connected to the anode side of the first diode element; and a collector of one transistor is connected to the first transistor. a first transistor connected to the emitter of the transistor and a collector of the other transistor connected to the anode side of the first diode element.
a second transistor whose base is connected to the anode side of the first diode element, whose collector is connected to a power supply and whose emitter is connected to a hold capacitor; and the collector of one transistor is connected to the power supply. A sample hold circuit comprising a second differential circuit in which the collector of the other transistor is connected to the emitter of the second transistor.