JPS63229891A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS63229891A
JPS63229891A JP6472787A JP6472787A JPS63229891A JP S63229891 A JPS63229891 A JP S63229891A JP 6472787 A JP6472787 A JP 6472787A JP 6472787 A JP6472787 A JP 6472787A JP S63229891 A JPS63229891 A JP S63229891A
Authority
JP
Japan
Prior art keywords
mask
layer
semiconductor
growth
grown
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6472787A
Other languages
Japanese (ja)
Inventor
Kenya Nakai
中井 建彌
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP6472787A priority Critical patent/JPS63229891A/en
Publication of JPS63229891A publication Critical patent/JPS63229891A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To realize the formation of a deeply buried layer through a vapor growth method wherein a semiconductor substrate surface exposed by etching is selectively coated with a mask, and a second semiconductor layer is grown after a semiconductor layer is so grown that the layer surface makes an obtuse angle with the mask surface. CONSTITUTION:An n-type clad layer 2, an active layer 3, a p-type clad layer 4, and a p<+>-type contact layer 5 are successively grown on an n-type semiconductor substrate 1. Next, a mask 11 is selectively formed thereon, and etching is performed onto layers 5-2 to reach under the mask 11 for the formation of a recessed part. A process follows, wherein a mask 12 is selectively formed on the mask 11 for the growth of a buried layer 6a. In this case, a vapor growth surface is so controlled that the layer 6a surface is grown to be a trapezoid making an obtuse angle with the mask 12 surface. Next, the mask 12 is removed for the formation of a semiconductor 6b on the layers 6 and 2. By these processes, a deeply buried layer is flatly grown through a vapor growth method.

Description

【発明の詳細な説明】 〔概要〕 この発明は、半導体層の埋め込み成長に際して、半導体
基体面を選択的に被覆する第1のマスクの下に達するエ
ツチングを行い、半導体基体の該エツチングによる表出
面を第2のマスクで選択的に被覆して、表面が該第2の
マスクの表面と鈍角をなす第1の半導体層を成長し、該
第2のマスクを除去して、該第1の半導体層及び該半導
体基体の表出面上に第2の半導体層を成長することによ
り、 気相成長方法、特にMO−CVD法によって、深い埋め
込み層を平坦に成長することを可能とするものである。
Detailed Description of the Invention [Summary] The present invention involves performing etching that reaches below a first mask that selectively covers the surface of a semiconductor substrate during buried growth of a semiconductor layer, and etching the exposed surface of the semiconductor substrate by the etching. is selectively covered with a second mask to grow a first semiconductor layer whose surface forms an obtuse angle with the surface of the second mask, and the second mask is removed to grow the first semiconductor layer. By growing a second semiconductor layer on the exposed surface of the layer and the semiconductor body, it is possible to grow a deep buried layer flatly by means of a vapor phase growth method, in particular a MO-CVD method.

〔産業上の利用分野〕[Industrial application field]

本発明は半導体装置の製造方法、特に半導体層の埋め込
み成長に、有機金属熱分解気相成長方法(MO−CVD
法)等の気相成長方法の適用を可能とする半導体装置の
製造方法の改善に関する。
The present invention is applicable to a method for manufacturing a semiconductor device, particularly to the buried growth of a semiconductor layer using a metal organic pyrolysis vapor deposition method (MO-CVD).
This invention relates to an improvement in a method for manufacturing a semiconductor device that enables the application of vapor phase growth methods such as the above method.

例えば半導体発光装置は光通信等の光応用システムで極
めて重要な役割を担っていて、その信頼性の確保、向上
、電子回路とのより良い適合がますます要望され、さら
に光応用システムの拡大に対応する生産性の向上が不可
欠となっている。
For example, semiconductor light-emitting devices play an extremely important role in optical application systems such as optical communications, and there is an increasing need to ensure and improve their reliability and better compatibility with electronic circuits. Corresponding productivity improvements have become essential.

〔従来の技術〕[Conventional technology]

半導体発光装置について多種の構造、製造方法が既に開
発されているが、その半導体層の成長には従来概ね液相
エピタキシャル成長方法(LPE法)が適用されており
、例えば石英系ファイバによる伝送に適する波長1.3
〜1.6囮程度の帯域の半導体レーザとして知られてい
る、第2図に模式断面図を示すインジウム燐/インジウ
ムガリウム砒素燐(InP/ InGaAsP)系BH
(Buried Heterostructure)レ
ーザは、LPE法を適用して下記の様に製造されている
Various structures and manufacturing methods have already been developed for semiconductor light emitting devices, but conventionally liquid phase epitaxial growth (LPE) has generally been applied to grow semiconductor layers. 1.3
Indium phosphide/indium gallium arsenide phosphide (InP/InGaAsP)-based BH, whose schematic cross-sectional view is shown in Fig. 2, is known as a semiconductor laser with a band of ~1.6 decoys.
(Buried Heterostructure) lasers are manufactured as follows by applying the LPE method.

すなわち、例えばn型InP基板21の(100)面上
に、先ずn型1nPクラッド層22、InGaAsP活
性層23、p型InPクラッド層24及びp型InGa
AsP :1ンタクト層25を順次エピタキシャル成長
する。
That is, for example, first, on the (100) plane of the n-type InP substrate 21, an n-type 1nP cladding layer 22, an InGaAsP active layer 23, a p-type InP cladding layer 24, and a p-type InGa
AsP:1 contact layers 25 are epitaxially grown in sequence.

この半導体基体面上に長さ方向が(011)方向のスト
ライブ状のマスクを設け、例えば臭素(Br) −メタ
ノール溶液を用いてエツチングし、逆メサ状のストライ
プ領域を形成する。
A stripe-shaped mask whose length direction is in the (011) direction is provided on the surface of the semiconductor substrate, and etched using, for example, a bromine (Br)-methanol solution to form an inverted mesa-shaped stripe region.

このエツチングした領域に例えば半絶縁性InP層26
を半導体基体の上面が平坦になる様に埋め込み成長して
、電流狭窄とレーザ光の横モードを制御する屈折率ガイ
ディングとを行わせ、次いでp側電極28、n側電極2
9を配設する。
For example, a semi-insulating InP layer 26 is formed in this etched region.
is buried and grown so that the upper surface of the semiconductor substrate becomes flat to perform current confinement and refractive index guiding to control the transverse mode of the laser beam, and then the p-side electrode 28 and the n-side electrode 2 are formed.
Place 9.

このLPE法は結晶欠陥の発生が少なく、上述の半導体
基体の上面を平坦にする埋め込み成長が可能であるが、
そのプロセスは生産性の向上になじみ難<、更に相律に
支配されて成長が不可能な場合がある。
This LPE method produces fewer crystal defects and allows buried growth to flatten the top surface of the semiconductor substrate described above.
This process is difficult to adapt to productivity improvement, and furthermore, growth may be impossible due to being dominated by phase laws.

他方開−CVD法は、常温で安定な水素化合物が得られ
ない■族或いは■族元素については有機化合物、■族゛
、■族或いは■族元素については通常水素化合物を出発
原料とする気相エピタキシャル成長法で、最近著しく進
展して結晶の質及び生産性が向上するのみならず、単分
子層程度の薄膜、超格子構造の成長まで可能となりつつ
ある。
On the other hand, the open-CVD method uses an organic compound for group Ⅰ or group Ⅰ elements for which hydrogen compounds that are stable at room temperature cannot be obtained, and a vapor phase method that uses hydrogen compounds as the starting material for group ⑛, Ⅰ, or Ⅰ elements. Epitaxial growth has recently made remarkable progress, not only improving crystal quality and productivity, but also making it possible to grow thin films on the order of monomolecular layers and superlattice structures.

しかしながら上述の従来例のInP層26の如く、半導
体基体面の深いくぼみに半導体層を埋め込み成長し、し
かもその上面を平坦にすることは、■−CVO法では甚
だ困難である。
However, it is extremely difficult to grow a semiconductor layer buried in a deep recess on the surface of a semiconductor substrate and to flatten the upper surface of the semiconductor layer, as in the case of the InP layer 26 of the conventional example described above, using the -CVO method.

すなわち第3図(a)の模式図の如くマスク33が庇状
に張り出し、埋め込み成長を行うくぼみの端面31がそ
の底面32との間になす角θが鈍角の傾斜面であれば、
破線で示す如く成長が進行し、例えば角θが約135度
のときにくぼみの深さhが5n程′  度までの範囲で
、上面がほぼ平坦な埋め込み半導体層が得られる。
That is, if the mask 33 protrudes like an eaves as shown in the schematic diagram of FIG. 3(a), and the angle θ formed between the end face 31 of the recess where the filling growth is performed and the bottom face 32 is an obtuse angle,
The growth progresses as shown by the broken line, and for example, when the angle θ is about 135 degrees, a buried semiconductor layer with a substantially flat top surface is obtained in which the depth h of the depression is up to about 5n'.

第3図(blの模式図の如く、埋め込み成長を行うくぼ
みの端面31がその底面32に対してほぼ垂直であれば
、埋め込み成長を行うくぼみの深さhが例えば34程度
までの範囲で、図示の如くマスク33の近傍のくぼみ3
4以外は上面がほぼ平坦な埋め込みが行われるが、深さ
hがこの程度を越えればくぼみ34が大きくなって使用
に耐えなくなる。
As shown in the schematic diagram in FIG. 3 (bl), if the end face 31 of the depression in which the buried growth is performed is approximately perpendicular to the bottom surface 32, the depth h of the depression in which the buried growth is performed is within a range of, for example, about 34 mm. As shown in the figure, the depression 3 near the mask 33
In the case other than 4, the upper surface is buried with a substantially flat surface, but if the depth h exceeds this level, the recess 34 becomes so large that it becomes unusable.

更に埋め込み成長を行うくぼみの端面31がその底面3
2に対して鋭角をなす傾斜面であれば、埋め込み成長を
行うくぼみの深さhが例えば1−程度で第3図(C)に
例示する模式図の如く、(111)8面35が現れて底
面32の隅近傍では成長が殆ど進行しない。
Furthermore, the end surface 31 of the depression where the filling growth is performed is the bottom surface 3.
If the slope is at an acute angle with respect to 2, the depth h of the depression in which the buried growth is performed is, for example, about 1, and a (111)8 plane 35 appears as shown in the schematic diagram in FIG. 3(C). Growth hardly progresses near the corners of the bottom surface 32.

MO−CVD法ではこの様に埋め込み成長が困難である
ことから、MO−CVD法によって製造可能な構造とし
て例えば第4図に示す半導体レーザが提供されている。
Since buried growth is difficult in the MO-CVD method, a semiconductor laser shown in FIG. 4, for example, has been provided as a structure that can be manufactured by the MO-CVD method.

本従来例において、31はn型半導体基板、32はn型
クラッド層、33は活性層、36はp型クラッド層、3
7はp型コンタクト層であり、n型半導体層34とn型
半導体層35とによって電流狭窄と損失ガイディングを
行うが、先ず基板31上に半導体層32〜35を順次成
長しT、′a状のエツチングを活性層33に及ばないよ
うに実施し、この溝を埋めこむp型りラッド層36とp
型コンタクト層37とを成長している。なおp側電極3
8はこの溝上に設けられる。
In this conventional example, 31 is an n-type semiconductor substrate, 32 is an n-type cladding layer, 33 is an active layer, 36 is a p-type cladding layer, 3
7 is a p-type contact layer, and current confinement and loss guiding are performed by the n-type semiconductor layer 34 and the n-type semiconductor layer 35. First, the semiconductor layers 32 to 35 are sequentially grown on the substrate 31. Etching is carried out so as not to reach the active layer 33, and the p-type rad layer 36 filling this groove and the p-type
A mold contact layer 37 is grown. Note that the p-side electrode 3
8 is provided on this groove.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

MO−CVO法などの気相成長方法は上述の様に選択的
成長には難点が多く、従来LPE法によって製造されて
いる半導体発光装置を実現できないために、第4図に例
示した従来例の如き構造が提供されてはいるが、その特
性に遜色があり、更に光・電子集積回路装置(OEIC
)などを考慮する場合に、半導体基体面が平坦でないこ
とが障害となる。
As mentioned above, vapor phase growth methods such as the MO-CVO method have many difficulties in selective growth and cannot realize the semiconductor light emitting device conventionally manufactured by the LPE method. Although such a structure has been provided, its characteristics are inferior, and the optical/electronic integrated circuit device (OEIC)
) etc., the fact that the semiconductor substrate surface is not flat becomes an obstacle.

この様な状況から、第2図に例示した従来例の如き良好
な特性が得られている半導体発光装置に要求される電流
狭窄及びモード制御のための深い埋め込み成長などを、
気相成長方法、特にMO−CVD法によって実現可能に
する半導体装置の製造方法が強(要望されている。
Under these circumstances, deep buried growth for current confinement and mode control required for semiconductor light emitting devices with good characteristics such as the conventional example shown in FIG.
There is a strong demand for a method for manufacturing semiconductor devices that can be realized using a vapor phase growth method, particularly an MO-CVD method.

〔問題点を解決するための手段〕[Means for solving problems]

前記問題点は、■半導体基体の埋め込み成長層に置換す
る部分をエツチングして第1のマスクが庇状に張り出し
たオーバーハング状態とした後に、■第2のマスクで半
導体基体のエツチングによる表出面を選択的に被覆し、
第1のマスクも被覆して、■エツチングによる半導体基
体面上の第2のマスクの表面に対してその表面が鈍角を
なす第1の半導体層を先ず成長する。次いで■第2のマ
スクを除去して、この第1の半導体層と第2のマスクで
被覆されていたエツチングによる半導体基体面上に第2
の半導体層を成長して埋め込み成長を完了する製造方法
により解決される。
The problem is as follows: (1) After etching the portion of the semiconductor substrate to be replaced with the buried growth layer to create an overhang state in which the first mask protrudes like an eave, (2) etching the exposed surface of the semiconductor substrate with the second mask; selectively coated with
Also covering the first mask, a first semiconductor layer is first grown whose surface forms an obtuse angle with respect to the surface of the second mask on the semiconductor substrate surface by etching. Next, (1) the second mask is removed, and a second layer is formed on the etched semiconductor substrate surface that was covered with the first semiconductor layer and the second mask.
The problem is solved by a manufacturing method that grows a semiconductor layer and completes the buried growth.

〔作 用〕[For production]

本発明による製造方法では例えば後述する実施例の如く
、埋め込み成長を2段階で実施する。
In the manufacturing method according to the present invention, the buried growth is performed in two stages, for example, as in the embodiment described later.

その第1段階として、オーバーハング状態の第1のマス
ク11に加えて、半導体基体のエツチングによる表出面
上に第2のマスク12を、その開口の外周と半導体基体
の第1のマスク11に接する上端とを通る面が例えば半
導体基体の(111)B面程度の勾配になる様に設けて
、第1の半導体層6八を成長する。この様にエピタキシ
ャル成長面を制限することにより、第1の半導体層6A
はMO−CVD法等の気相成長方法でその表面が第2の
マスク12の表面に対して鈍角をなす台形に成長する。
In the first step, in addition to the overhanging first mask 11, a second mask 12 is placed on the etched exposed surface of the semiconductor substrate, and the outer periphery of the opening is in contact with the first mask 11 of the semiconductor substrate. The first semiconductor layer 68 is grown so that the plane passing through the upper end has a slope similar to, for example, the (111)B plane of the semiconductor substrate. By restricting the epitaxial growth surface in this way, the first semiconductor layer 6A
is grown into a trapezoidal shape whose surface forms an obtuse angle with respect to the surface of the second mask 12 by a vapor phase growth method such as MO-CVD.

次いで第2段階として第2のマスク12を除去し、第1
の半導体層6Aと第2のマスク12で被覆されていたエ
ツチングによる半導体基体面上に、第2の半導体層6B
を成長する。この第2段階の成長では傾斜面が上述の様
に整形されているために、エツチング深さが例えば5−
或いはこれを越える場合でもMO−CVD法等の気相成
長方法で成長が進行し、埋め込みが支障なく実現する。
Then, in a second step, the second mask 12 is removed and the first mask 12 is removed.
A second semiconductor layer 6B is formed on the etched semiconductor substrate surface that has been covered with the semiconductor layer 6A and the second mask 12.
grow. In this second stage of growth, since the inclined surface is shaped as described above, the etching depth is, for example, 5-5.
Even if the amount exceeds this, growth proceeds by a vapor phase growth method such as MO-CVD, and embedding can be achieved without any problem.

〔実施例〕〔Example〕

以下本発明を第1図に工程順模式断面図を示す実施例に
より具体的に説明する。
The present invention will be specifically explained below with reference to an example shown in FIG. 1, which is a schematic cross-sectional view of the process order.

第1図(a)参照= n型rnP半導体基板1の(10
0)面上に、例えば錫(Sn)を濃度1×1018a6
″3程度にドープし厚さ3μm程度のn型1nPクラッ
ド層2、例えば厚さ0.15μm程度、ノンドープでル
ミネセンスピーク波長1.3μのInGaAsP活性J
W3、例えばカドミウム(Cd)を濃度I XIO”c
m−’程度にドープし厚さ2.0μm程度のp型InP
クラッド層4、例えば亜鉛(Zn)を濃度5×1011
Ia14程度にドープし厚さ0.5μm程度のp+梨型
1nGaAsPンタクト層5を順次エピタキシャル成長
する。
Refer to FIG. 1(a) = (10
0) On the surface, for example, tin (Sn) is applied at a concentration of 1×1018a6
An n-type 1nP cladding layer 2 doped to approximately 3 μm and having a thickness of approximately 3 μm, for example, an undoped InGaAsP active layer 2 having a thickness of approximately 0.15 μm and a luminescence peak wavelength of 1.3 μm.
W3, for example cadmium (Cd) at a concentration of I
P-type InP doped to about m-' and about 2.0 μm thick
Cladding layer 4, for example, zinc (Zn) with a concentration of 5×1011
A p+ pear-shaped 1nGaAsP contact layer 5 doped to about Ia14 and having a thickness of about 0.5 μm is sequentially epitaxially grown.

本実施例ではこの成長はNo−CVD法により、圧カフ
60torr 、基板温度650℃とし、原材料として
、Inはトリメチルインジウム(In(CHs) 3)
、Gaはトリメチルガリウム(Ga (Ctb) s)
、Asはアルシン(Astl+)、Pはホスフィン(P
H3)、不純物としてドープするSiはモノシラン(S
iH4)、Cdはジメチルカドミウム(ca (CH:
l) z)を用い、キャリアガスは水素(H2)を用い
ている。
In this example, this growth was carried out by the No-CVD method at a pressure cuff of 60 torr and a substrate temperature of 650°C, and as a raw material, In was trimethylindium (In(CHs) 3).
, Ga is trimethylgallium (Ga(Ctb)s)
, As is arsine (Astl+), P is phosphine (P
H3), Si doped as an impurity is monosilane (S
iH4), Cd is dimethyl cadmium (ca (CH:
l) z) and hydrogen (H2) is used as the carrier gas.

第1図(bl参照: 第1のマスク11をこの半導体基
体上(011)方向のストライプ状に、例えば二酸化シ
リコン(SiOz)を用いて幅W、1=3iIm程度に
形成する。
FIG. 1 (see bl) A first mask 11 is formed in a stripe shape in the (011) direction on this semiconductor substrate using, for example, silicon dioxide (SiOz) and has a width W of about 1=3 iIm.

この半導体基体のInGaAsPコンタクト層5を先ず
硝酸(HNO3)系溶液でエツチングした後に、希釈し
た塩酸(HCI)系溶液でエツチングして、破線で示す
如く、n型1nPクラッド層2に達して深さが3.5I
rm程度、オーバーハング幅讐。h=1.5−程度で、
端面がほぼ垂直なくぼみを形成する。
The InGaAsP contact layer 5 of this semiconductor substrate is first etched with a nitric acid (HNO3) based solution, and then etched with a diluted hydrochloric acid (HCI) based solution to reach the n-type 1nP cladding layer 2 to a depth as shown by the broken line. is 3.5I
About rm, overhang width. h = about 1.5-,
The end face forms a nearly vertical depression.

次いで例えば臭素(Br)−エタノール溶液により(1
11)A面が発達するエツチングを行い、InGaAs
P活性層3の幅−a=1.5IIm程度、深さh = 
5 prn程度の逆メサ状ストライプ領域を形成する。
Then, for example, (1
11) Perform etching to develop the A side, and
Width of P active layer 3 - a = approximately 1.5 IIm, depth h =
An inverted mesa-like stripe region of about 5 prn is formed.

第1図(C1参照: この半導体基体上に例えば酸化ア
ルミニウム(Ah(h)をスパッタし、リソグラフィ法
によりパターニングして、第2のマスク12を形成する
。本実施例ではこの第2のマスク12の開口幅を例えば
w、z = 12μmとして、この開口の外周12Eと
第1のマスク11に接する半導体基体の上端5Eとを過
る面の勾配を、半導体基体の(111)B面程度として
いる。
1 (see C1: For example, aluminum oxide (Ah(h)) is sputtered onto this semiconductor substrate and patterned by lithography to form a second mask 12. In this embodiment, this second mask 12 is For example, the width of the opening is w, z = 12 μm, and the slope of the plane that passes between the outer periphery 12E of this opening and the upper end 5E of the semiconductor substrate in contact with the first mask 11 is approximately the (111)B plane of the semiconductor substrate. .

第1図(dl参照: 半絶縁性1nP埋め込み層6の第
1段階のエピタキシャル成長を行う。
FIG. 1 (see dl: The first stage of epitaxial growth of the semi-insulating 1nP buried layer 6 is performed.

本実施例では深い準位を形成するアクセプタ不純物とし
て鉄(Fe)をドープし、MO−CVD法により例えば
圧力を760TorrS基板温度を650℃として、1
0%水素希釈P)13を460cc 7分とし、In 
(CIり sを25℃で50cc 7分のH2通気、フ
ェロセン鉄(Fe(CzHs))を0℃で5cc/分の
H2通気で送り込み、総流量をH2で10β/分として
いる。
In this example, iron (Fe) is doped as an acceptor impurity that forms a deep level, and the pressure is set to 760 TorrS and the substrate temperature is 650°C by the MO-CVD method.
0% hydrogen dilution P)13 was made into 460cc for 7 minutes, and In
(CI Ris) was fed with 50 cc of H2 aeration for 7 minutes at 25°C, and ferrocene iron (Fe(CzHs)) was fed with 5 cc/min of H2 aeration at 0°C, with a total flow rate of 10β/min of H2.

この成長では(111)B面が発達し易く、本実施例で
は図示の如< (111)B面のファセットを形成して
、このInP埋め込み層6^の成長が終了する。
In this growth, the (111) B plane is likely to develop, and in this embodiment, the (111) B plane facet is formed as shown in the figure, and the growth of the InP buried layer 6^ is completed.

第1図(el参照: マスク12をマスク11に対して
選択的に除去し、半絶縁性InP埋め込み層6の第2段
階のエピタキシャル成長を行う。
1 (see el): The mask 12 is selectively removed with respect to the mask 11, and a second stage of epitaxial growth of the semi-insulating InP buried layer 6 is performed.

この成長もMO−CVD法により前記第1段階の成長と
同様の条件で実施するが、マスク11のオーバーハング
幅(図(blの居。、)を本実施例程度とすることによ
り、InP埋め込み層6Bのほぼ平坦な埋め込み成長が
実現する。
This growth is also carried out by the MO-CVD method under the same conditions as the first stage of growth, but by making the overhang width of the mask 11 (Figure (the location of bl) approximately the same as in this example), InP is buried. A substantially flat buried growth of layer 6B is achieved.

なお前記成長条件のうちIn(CH3)zを300cc
 /分程度とすることにより、(111)B面のファセ
ットが現れてマスク11の近傍に若干の段差を生ずる傾
向を低減することができる。
Among the above growth conditions, In(CH3)z was 300cc.
By setting the distance to about 1/min, it is possible to reduce the tendency for facets of the (111)B plane to appear and create a slight step in the vicinity of the mask 11.

第1図(f)参照: マスク11を除去してp側電極8
及びn側電極9を形成し、襞間等のプロセスを経て本実
施例の素子が完成するが、本発明による半導体基体はそ
の上面が平坦であるために、LPE法による半導体発光
装置と同様の形状に形成することができる。
See FIG. 1(f): Remove the mask 11 and remove the p-side electrode 8.
and n-side electrode 9 are formed, and the device of this example is completed through processes such as inter-folding. However, since the semiconductor substrate according to the present invention has a flat upper surface, it is similar to the semiconductor light emitting device using the LPE method. It can be formed into any shape.

本実施例では、闇値電流15mA程度、定格動作状態に
おける外部微分効率25%程度が得られ、第2図に示す
LPE法によるBHレーザと同等以上の性能を有するこ
とが実証されている。
In this example, a dark value current of about 15 mA and an external differential efficiency of about 25% in the rated operating state are obtained, and it has been demonstrated that the laser has performance equivalent to or better than that of the BH laser based on the LPE method shown in FIG. 2.

上述の説明ではInP/ InGaAsP系レーザを引
例しているが、例えばGaAs/AlGaAs系などの
他の半導体材料、レーザ以外の各種の半導体装置につい
ても本発明により同様の効果が得られる。
Although the above description refers to an InP/InGaAsP laser, similar effects can be obtained by the present invention with respect to other semiconductor materials such as GaAs/AlGaAs and various semiconductor devices other than lasers.

〔発明の効果〕〔Effect of the invention〕

以上説明した如(本発明によれば、例えば半導体発光装
置の電流狭窄及びモード制御のための深い埋め込み層な
どの成長が、気相成長方法、特にMO−CVD法によっ
て実現可能となり、従来LPE法等によることを余儀無
くされて製造工程の隘路となっている成長プロセスを、
MO−CVD法を始めとする気相成長法に切り換える半
導体装置の製造方法の改善が達成される。
As explained above (according to the present invention), for example, the growth of a deep buried layer for current confinement and mode control of a semiconductor light emitting device can be realized by a vapor phase growth method, particularly an MO-CVD method, and the growth of a deep buried layer for current confinement and mode control of a semiconductor light emitting device can be realized using a vapor phase growth method, in particular an MO-CVD method, and a conventional LPE method. The growth process, which has become a bottleneck in the manufacturing process due to
Improvements can be achieved in the manufacturing method of semiconductor devices by switching to vapor phase growth methods such as MO-CVD methods.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の実施例の工程順模式断面図、第2図及
び第4図は従来例の模式断面図、第3図はMO−CVD
法による埋め込み成長の模式図である。 図において、 1はn型InP半導体基板、 2はn型1nPクラッド層、 3はInGaAsP活性層、 4はp型InPクラッド層、 5はf型1nGaAsPコンタクト層、5Eはその端、
6.6A、6Bは半絶縁性1nP埋め込み層、8.9は
電極、 11.12はマスク、12Eはマスク12の端を示す。 笑方ヒ1便]の二程円頁頌式−η′狛図第 1 図 ’ffQ(W’j のrJtlll[AffデIt12
1潴 1 医 イLtイク月のll?QJ’rLI2コ第 2m Ho−cvグムにJ、る埋め込班ぺ長の項式図第 3図 ちt丁ヒ未4ミイ7’J6勺Rtξ dプrimcン]
第4n
Figure 1 is a schematic sectional view of the process order of the embodiment of the present invention, Figures 2 and 4 are schematic sectional views of the conventional example, and Figure 3 is a MO-CVD
FIG. 2 is a schematic diagram of embedded growth by the method. In the figure, 1 is an n-type InP semiconductor substrate, 2 is an n-type 1nP cladding layer, 3 is an InGaAsP active layer, 4 is a p-type InP cladding layer, 5 is an f-type 1nGaAsP contact layer, 5E is the end thereof,
6.6A and 6B are semi-insulating 1nP buried layers, 8.9 is an electrode, 11.12 is a mask, and 12E is an end of the mask 12. [Aff de It12
1 潴 1 Medical I Lt Iku month ll? QJ'rLI 2nd 2nd m Ho-cv gum to J, ru embedded team Pe's term formula diagram 3rd figure Chi t Ding Hi Mi 4 Mii 7'J6 勺Rtξ dprimcn]
4th n

Claims (1)

【特許請求の範囲】 半導体基体の表面を第1のマスクで選択的に被覆して、
該半導体基体に該第1のマスクの下に達するエッチング
を行い、 該第1のマスク及び該半導体基体の該エッチングによる
表出面を第2のマスクで選択的に被覆して、表面が該第
2のマスクの表面と鈍角をなす第1の半導体層を成長し
、 該第2のマスクを除去して、該第1の半導体層及び該半
導体基体の該エッチングによる表出面上に第2の半導体
層を成長することを特徴とする半導体装置の製造方法。
[Claims] Selectively covering the surface of the semiconductor substrate with a first mask,
etching the semiconductor substrate to reach below the first mask; selectively covering the first mask and the exposed surface of the semiconductor substrate by the etching with a second mask; growing a first semiconductor layer forming an obtuse angle with the surface of the mask; removing the second mask; and growing a second semiconductor layer on the etched exposed surface of the first semiconductor layer and the semiconductor substrate; 1. A method for manufacturing a semiconductor device, characterized by growing a semiconductor device.
JP6472787A 1987-03-19 1987-03-19 Manufacture of semiconductor device Pending JPS63229891A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6472787A JPS63229891A (en) 1987-03-19 1987-03-19 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6472787A JPS63229891A (en) 1987-03-19 1987-03-19 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS63229891A true JPS63229891A (en) 1988-09-26

Family

ID=13266472

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6472787A Pending JPS63229891A (en) 1987-03-19 1987-03-19 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS63229891A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008172101A (en) * 2007-01-12 2008-07-24 Furukawa Electric Co Ltd:The Embedding method, semiconductor device manufacturing method, and semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008172101A (en) * 2007-01-12 2008-07-24 Furukawa Electric Co Ltd:The Embedding method, semiconductor device manufacturing method, and semiconductor device
JP4653124B2 (en) * 2007-01-12 2011-03-16 古河電気工業株式会社 Semiconductor device manufacturing method

Similar Documents

Publication Publication Date Title
JPH06291416A (en) Semiconductor laser and manufacture thereof
JPH07221392A (en) Quantum thin wire and its manufacture, quantum thin wire laser and its manufacture, manufacture of diffraction grating, and distributed feedback semiconductor laser
JP5027647B2 (en) Embedded heterostructure devices fabricated by single step MOCVD
JP2708165B2 (en) Semiconductor structure and method of manufacturing the same
US5227015A (en) Method of fabricating semiconductor laser
US7474683B2 (en) Distributed feedback semiconductor laser
US6556605B1 (en) Method and device for preventing zinc/iron interaction in a semiconductor laser
US7998770B2 (en) Method for forming a semiconductor light-emitting device
JP5169534B2 (en) Integrated optical semiconductor device manufacturing method and integrated optical semiconductor device
US7816157B2 (en) Method of producing semiconductor optical device
JPS63229891A (en) Manufacture of semiconductor device
JPH077232A (en) Optical semiconductor device
JP3047049B2 (en) Method of manufacturing buried semiconductor laser
JPH0936487A (en) Fabrication of semiconductor device
JP3830552B2 (en) Method for manufacturing buried semiconductor laser device
JP2018101752A (en) Semiconductor optical element and method for manufacturing the same
JPH0448669A (en) Semiconductor laser device and its manufacture
JP3132054B2 (en) Method of manufacturing buried semiconductor laser
JPS63129683A (en) Manufacture of buried semiconductor laser
JPH09186391A (en) Compound semiconductor device and manufacture thereof
JPH0824208B2 (en) Manufacturing method of semiconductor laser
JPS63284877A (en) Manufacture of semiconductor device
JP3188931B2 (en) Thin film growth method
JPH07297140A (en) Fabrication of optical semiconductor device
JP2000138418A (en) Manufacture of semiconductor laser