JPH09186391A - Compound semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a compound semiconductor device such as a DFB (distributed feedback) laser or the like whose surface is excellent in flatness through a simple manufacturing process. SOLUTION: A dielectric mask 2 provided with an opening which varies in width with its position is provided onto a semiconductor substrate 1, a first semiconductor layer 5 is selectively grown in the opening through an organic metal vapor phase epitaxy method, and then a second semiconductor layer 8 is grown on all the surface, wherein the first semiconductor layer 5 is set thicker in a region 4 where the opening is small in width than in a region 3 where the opening is large in width, and a part of the second semiconductor layer 8 located on the dielectric mask 2 is made to grow in polycrystal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a compound semiconductor device and a method of manufacturing the same, and more particularly, to a compound semiconductor device such as an OEIC (Optoelectronics IC) in which an optical waveguide and a semiconductor laser are integrated and a method of manufacturing the same. It is about.

[0002]

2. Description of the Related Art In recent years, optical semiconductor devices such as semiconductor lasers have been greatly improved in their characteristics by using multiple quantum wells (MQWs). Further, an optical waveguide or an optical modulator and a laser element are integrated. Integrating devices having different functions, such as integration.

In such integration, an MQW structure can be formed with good controllability, a wide bandgap semiconductor layer containing P can be formed with good reproducibility, and a metal-organic vapor phase suitable for mass production is provided. The growth method (MOVPE method) is used.

A conventional optical modulator integrated DFB (distributed feedback type) laser using the MOVPE method (see Japanese Patent Laid-Open No. 4-100291) will be described with reference to FIG. 6A is a cross-sectional view taken along the alternate long and short dash line connecting AA ′ in FIG. 6B, and FIG. 6B is a plan view at the time when the selective growth mask is formed. is there.

6A and 6B. First, Si is formed on an n-type InP substrate 31 which also serves as a cladding layer.
By providing an O ₂ film and then patterning,
In the optical modulator formation region 32, the DFB laser formation region 3
Si having a stripe-shaped opening wider than 3
An O ₂ mask 34 is formed.

[0006] Then, by the MOVPE method, InGa
An AsPMQW active layer 35 and an InGaAsP light guide layer 36 are deposited. In this case, since the semiconductor layer does not grow on the SiO ₂ mask 34 but only in the opening, the stripe width D is narrower than that of the optical modulator forming region 32.
In the FB laser forming region 33, the optical modulator forming region 3
It will be deposited thicker than 2.

As a result, the energy gap between the MQW quantum levels in the DFB laser formation region 33 becomes smaller than the energy gap between the MQW quantum levels in the optical modulator formation region 32. An energy gap distribution is formed.

Next, a corrugation 37 is formed on the surface of the InGaAsP optical guide layer 36 in the DFB laser forming region 33, and then a p-type InP clad layer 38 and ap ⁺ -type InGaAsP contact layer 39 are sequentially formed.
An optical modulator integrated DFB laser is completed by appropriately dividing each element after forming each electrode.

In this case, by utilizing the selective growth method using the SiO ₂ mask 34, an energy gap distribution can be formed naturally in the laser cavity direction,
An optical modulator integrated type DFB laser with little optical absorption loss can be obtained.

[0010]

However, in this case, p
Since the type InP clad layer 38 and the p ⁺ type InGaAsP contact layer 39 also do not grow on the SiO ₂ mask 34, they are deposited thicker in the DFB laser forming region 33 than in the optical modulator forming region 32. There is a problem in that the step 40 between the optical modulator formation region 32 becomes large and the flatness becomes extremely poor, which greatly impedes the subsequent photolithography process.

In order to solve such a problem, the InGaAsPMQW active layer 35 and the InGaAs are used.
After growing the P light guide layer 36, once the MOVPE
The SiO ₂ mask 34 is removed from the growth apparatus, and then the p-type InP clad layer 38 and the p ⁺ -type I are removed.
The nGaAsP contact layer 39 may be grown,
There is a problem that the manufacturing process becomes complicated.

Therefore, an object of the present invention is to provide a compound semiconductor device such as an optical modulator integrated DFB laser having a good surface flatness by a simple manufacturing process.

[0013]

FIG. 1 is an explanatory view of the principle configuration of the present invention, and means for solving the problems in the present invention will be described with reference to FIG. 1 (a) and 1 (b) (1) The present invention relates to a compound semiconductor device in which a dielectric mask 2 having an opening provided on a semiconductor substrate 1 and a first semiconductor layer 5 provided at the opening. , The first semiconductor layer 5
Second semiconductor layer 8 provided on the top and the dielectric mask 2
And at least a first semiconductor layer 5
Is thicker than the region 3 having a large opening area in the region 4 having a small opening area, and the second semiconductor layer 8 is a polycrystalline semiconductor on the dielectric mask 2. To do.

As described above, when the layer thickness distribution is formed on the first semiconductor layer 5 using the dielectric mask 2, the second semiconductor layer 8 covering the first semiconductor layer 5 is formed on the dielectric mask 2. Moreover, the surface of the growth layer, that is, the surface of the clad layer 10 can be made substantially flat by depositing it as a polycrystalline semiconductor.

(2) According to the present invention, in the above (1), the first semiconductor layer 5 is composed of the active layer 7 and the light guide layer 6, and the first semiconductor layer 5 of the second semiconductor layer 8 is included. The portion 9 in contact with is a cladding layer made of a III-V group compound semiconductor containing Al.

In this way, by providing a layer thickness distribution in the active layer 7, an energy gap distribution is formed in the cavity direction of the active layer, and elements having different functions are provided in different energy gap regions for integration. In addition, the portion 9 in contact with the first semiconductor layer 5 is a cladding layer made of a III-V group compound semiconductor having a wide bandgap containing Al to enhance carrier confinement efficiency and improve temperature dependence. can do.

(3) Further, according to the present invention, a dielectric mask 2 having openings having different sizes depending on locations is provided on the semiconductor substrate 1, and the first semiconductor layer 5 is formed by using the metal organic chemical vapor deposition method. In a method of manufacturing a compound semiconductor device, in which a second semiconductor layer 8 is grown on the entire surface after being selectively grown in the opening, the layer thickness of the first semiconductor layer 5 is set to be smaller in the region 4 having a smaller opening area. Is thicker than the region 3 having a large area, and the portion of the second semiconductor layer 8 that grows on the dielectric mask 2 is made of a polycrystalline semiconductor.

As described above, the layer thickness distribution can be formed in the first semiconductor layer 5 by the selective growth using the dielectric mask 2, and the second semiconductor layer covering the first semiconductor layer 5 can be formed. The growth layer surface, that is, the surface of the cladding layer 10 can be made substantially flat by non-selective growth in which 8 is deposited as a polycrystalline semiconductor also on the dielectric mask 2.

(4) Further, according to the present invention, in the above (3), when the first semiconductor layer 5 is grown, Ga and In are grown.
A methyl-based organometallic compound is used as a raw material of, and an ethyl-based organometallic compound is used as a raw material of Ga or In when growing a portion 9 of the second semiconductor layer 8 in contact with at least the first semiconductor layer 5. It is characterized by

As described above, in the MOVPE method, the methyl-based organometallic compound is used as the raw material of Ga and In to enhance the selective growth property, and the ethyl-based organometallic compound is used as the raw material of Ga or In. Selective growth can be eliminated.

(5) Further, in the present invention according to the above (3), when growing at least the portion 9 of the second semiconductor layer 8 in contact with the first semiconductor layer 5, low-temperature growth at 500 ° C. or lower is performed. It is characterized by

As described above, the growth temperature is set to a low temperature of 500 ° C. or lower, so that the selective growth property is reduced, and the substantially flat second semiconductor layer 8 is formed on the entire surface including the dielectric mask 2. You can

(6) According to the present invention, in the above (3), a halogen or a compound containing a halogen is used when the first semiconductor layer 5 is grown, and at least the second semiconductor layer 8 is formed. When growing the portion 9 in contact with the first semiconductor layer 5, the supply of halogen or a compound containing halogen is reduced or stopped.

As described above, the crystal growth is carried out in the state where the halogen or the compound containing the halogen is introduced,
Selective growth is possible even when a semiconductor that originally has poor selective growth properties, such as a III-V compound semiconductor containing Al.

(7) In addition, according to the present invention, in any one of the above (3) to (6), the portion 9 of the second semiconductor layer 8 in contact with the first semiconductor layer 5 contains III-V group. It is characterized by being made of a compound semiconductor.

As described above, by making the portion 9 of the second semiconductor layer 8 in contact with the first semiconductor layer 5 a III-V group compound semiconductor containing Al, non-selection is performed without adding special growth conditions. Since the growth is facilitated and the band gap is wide, the carrier confinement ratio can be improved. The Al-containing III-V group compound semiconductor may have a thickness of one molecular layer or more.

(8) Further, the present invention is characterized in that in the above (7), the first semiconductor layer 5 is the active layer 7 and the light guide layer 6 made of a III-V group compound semiconductor containing no Al. And

As described above, by using a III-V group compound semiconductor containing no Al such as InGaAsP as the active layer 7 and the light guide layer 6, selective growth is facilitated without adding special growth conditions.

[0029]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The manufacturing process of an embodiment of the present invention will be described with reference to FIGS. Note that FIG. 2A is a cross-sectional view, and FIG. 2B, FIG. 3C, FIG.
5 (i) is a plan view, and FIG. 3 (d),
4 (g) and FIG. 5 (j) are shown in FIG. 3 (c),
FIG. 4 (f) and FIG. 5 (i) show a cross section taken along the alternate long and short dash line connecting AA ′, and FIG.
(H) and FIG. 5 (k) show FIG. 3 (c) and FIG. 4 respectively.
FIG. 6F shows a cross section taken along the alternate long and short dash line connecting BB ′ in FIG.

First, a corrugation 12 for forming a distributed feedback resonator of an optical modulator integrated DFB laser is formed in a predetermined region of a Si-doped n-type InP substrate 11 which also serves as a cladding layer.

Next, referring to FIG. 2 (b), the entire surface has a thickness of 0.05 to 0.2 μm, for example,
A 0.1 μm SiO ₂ film is deposited by a thermal CVD method and then patterned by a photolithography process to form a wide opening corresponding to the optical modulator forming region 14 and a narrow opening corresponding to the laser forming region 15. A SiO ₂ mask 13 having an opening portion on a stripe, which is connected to each other by a tapered region, is formed.

In this case, the width of the opening corresponding to the optical modulator forming region 14 is 50 to 100 μm, for example, 80.
The width of the opening corresponding to the laser forming region 15 is 4 to 20 μm, for example, 10 μm.

Next, before the crystal growth, the surface of the n-type InP substrate 11 is cleaned by slightly etching with a sulfuric acid-based etching solution, and the SiO ₂ mask 13 is used.
Remove the residual photoresist on top.

3C to 3E, TMGa (trimethylgallium) as a Ga source, TMIn (trimethylindium) as an In source, AsH ₃ as an As source, and PH ₃ as a P source.
After growing an InGaAsP optical guide layer 16 having a composition corresponding to a wavelength of 1.0 μm by the MOVPE method using, an InGaAsP barrier layer having a composition corresponding to a wavelength of 1.1 μm and a wavelength of 1.35 μm are formed. The MQW active layer 17 is deposited by alternately stacking InGaAsP well layers having a corresponding composition.

In this case, as shown in FIG.
On the O ₂ mask 13, an InGaAsP light guide layer 16 is formed.
And the MQW active layer 17 do not grow, and as shown in FIG.
The thicknesses of the P light guide layer 16 and the MQW active layer 17 are the same as those of the InGaAsP light guide layer 1 in the optical modulator formation region 14.
6 and the thickness of the MQW active layer 17 are thicker.

For example, I in the optical modulator forming region 14
The nGaAsP light guide layer 16 and the MQW active layer 17 have thicknesses of 400 to 800 Å, for example, 500 Å and 200 to 800 Å, for example, 500 Å, respectively. The thickness of the layer 17 is 800-
1600Å, for example, 1000Å and 400 to 16
00Å, for example, 1000Å.

InGaAsP of the MQW active layer 17
Since there are five well layers, the above thickness is the total thickness of the well layers and barrier layers for five layers.

As described above, since the thickness of the MQW active layer 17 in the optical modulator forming region 14 and the laser forming region 15 is different, the quantum level in the MQW active layer 17 is also different, and the MQW active layer 17 has a different quantum level. The energy gap distribution is formed naturally.

In this case, since the quantum level becomes higher as the MQW becomes thinner, the energy gap becomes larger, and therefore, the light absorption loss of the laser light in the optical modulator formation region 14 can be made smaller. The optical modulator forming region 14 in this case functions as a spot size converter.

The growth conditions in this case, including the layers to be grown thereafter, are a growth pressure of 50 Torr, a total flow rate of the supply gas of 8000 sccm, and hydrogen as a carrier gas.

4F to 4H, TEGa (triethylgallium) as a Ga source, TEIn (triethylindium) as an In source, TEAl (triethylaluminum) as an Al source, and AsH ₃ as an As source. 1 with a substrate temperature of 600 to 700 ° C., for example, 650 ° C.
Molecular layer ~ 1000Å, for example, 200Å thick p-type A
The lGaInAs cladding layer 18 is grown, but since the III-V group compound semiconductor containing Al is also deposited on the dielectric film, in this case, the polycrystalline AlGaInAs layer grows on the SiO ₂ mask 13, In the subsequent crystal growth process, the p-type AlGaInAs cladding layer 18 functions as a selective growth blocking layer.

[0042] In this case, since the deposition gas is consumed even on the SiO ₂ mask 13, regardless of the shape of the SiO ₂ mask 13, the thickness substantially the same overall in a substantially constant growth rate at any portion The growth layer is deposited and the surface becomes substantially flat.

5 (i) to 5 (k), TMGa is used as a Ga source, and TMI is used as an In source.
n, AsH as As source _Three, And PH as P source_ThreeTo
Depending on the MOVPE method used, the thickness is 1.5 to 2.0 μ.
m, for example, 1.8 μm p-type InP clad layer 19,
And a thickness of 0.1 to 0.3 μm, for example 0.2 μm
p⁺A type InGaAsP contact layer 20 is grown.

In this case, polycrystalline AlG is already formed on the SiO ₂ mask 13 as a part of the p-type AlGaInAs layer 18.
Since the aInAs layer is deposited, the p-type InP clad layer 19 and the p ⁺ -type InGaAsP contact layer 20 also grow substantially flat over the entire surface.

Then, SiO 2 having a thickness of 0.2 μm is formed on the entire surface._Two
Width by depositing a film and then patterning
1.0-2.0 μm, for example, 1.3 μm stripe
Shaped SiO_TwoA mask 21 is formed, and this SiO_Twomask
21 as a mask, bromine-based etching solution and bromic acid-based
P type InP clad layer 19 and p
⁺Etching the InGaAsP contact layer 20
You.

In this case, the bromic acid type etching solution is p-type I.
The nP cladding layer 19 is etched, but p-type AlGa
Since the InAs clad layer 18 cannot be etched, the p-type AlGaInAs clad layer 18 also functions as an etching stop layer.

Then, using this SiO ₂ mask 21 as it is as a selective growth mask, the Fe-doped InP burying layer 22 is formed.
After forming, the SiO ₂ mask 21 is removed, an element isolation groove and a SiO ₂ passivation film are formed, and then,
After forming the p-side electrode and the n-side electrode, a width of 300 μm,
Optical modulator integrated type D cleaved on a chip with a length of 1000 μm
The BF laser is completed.

As described above, by forming the MQW active layer 17 by selective growth, an energy gap distribution is provided in the laser cavity direction, and a portion of the p-type cladding layer grown on the MQW active layer 17 in contact with the MQW active layer 17 is formed. A
since it is configured with the p-type AlGaInAs cladding layer 18 including l, substantially planar layer is grown on the entire surface without selective growth becomes flat subsequent growth layer, then the SiO ₂ mask 2
It is possible to accurately perform the photolithography process in the formation process of No. 1, the formation process of the element isolation groove, and the formation process of the electrode.

In the description of the above embodiment, the p-type AlGaInAs cladding layer 1 containing Al so as to be in contact with the MQW active layer 17 in order to eliminate the selective growth property.
8 is provided, the selective growth property may be eliminated by performing low temperature growth at a growth temperature of 500 ° C. or lower.

Similarly, in order to eliminate the selective growth property, Mg in the p-type cladding layer in contact with the MQW active layer 17 is used.
The concentration of p-type impurities such as Zn and Zn may be set to a high concentration of 10 ¹⁹ cm ⁻³ or higher, or the growth may be performed under growth pressure conditions near normal pressure. Furthermore, the growth rate is 5 μm / hour or higher. It may be a high speed.

In the above description of the embodiment, when the p-type AlGaInAs cladding layer 18 containing Al is grown, TEGa is removed in order to eliminate selective growth.
And an ethyl-based organometallic compound such as TEIn are used, but if Al is contained, TMGa, TMIn, and
A methyl-based organometallic compound such as TMAl (trimethylaluminum) may be used.

In addition, although the InP substrate is used as the substrate in the above description of the embodiment, a GaAs substrate may be used. In this case, after the corrugation and the SiO ₂ mask are formed on the GaAs substrate. First,
Selectively grow the lower AlGaAs cladding layer, then
After the AlGaAs optical guide layer and the AlGaAs MQW active layer are selectively grown, the upper AlGaAs cladding layer and the GaAs contact layer may be grown.

In this case, the growth layer is A except for the contact layer.
However, if the growth is carried out while introducing a halogen-based gas such as HCl or BrCH ₃ , selective growth is possible. Therefore, the lower AlGaAs cladding layer, the AlGaAs optical guide layer and the AlGaAs MQW active layer are halogen-based. After the selective growth is performed while introducing the gas, the upper AlGaAs cladding layer and the GaAs contact layer may be grown in a state where the supply of the halogen-based gas is reduced or stopped to eliminate the selective growth property.

When GaAs is used as the substrate, A is used as the cladding layer, the light guide layer and the active layer.
A wider forbidden band semiconductor such as 1GaInP or AlGaInAsP may be used.

In addition, since the III-V group compound semiconductor containing Al such as AlGaAs, AlGaInP, and AlGaInAsP has a high selective growth property by high temperature growth, low pressure growth, or low speed growth, they are combined to form a lower clad layer. The light guide layer and the active layer may be selectively grown.

Further, although the n-type substrate is used in the above description of the embodiment, a p-type substrate may be used.
In that case, all conductivity types should be reversed,
Although the optical guide layer is provided only on one side, it may be provided on both sides. Further, the p-type AlGaInAs clad layer 18 is used as the p-type clad layer in contact with the active layer. You may use.

Further, in the above description of the embodiment, the DFB laser utilizing corrugation has been described, but a DBR utilizing corrugation is similarly used.
A (distributed Bragg reflector) type laser may also be used.

[0058]

According to the present invention, the surface of the growth layer can be made substantially flat by forming the film thickness distribution by selective growth and then performing crystal growth under the condition that the selective growth property is deteriorated. Therefore, the photolithography process is facilitated, and an optical semiconductor device in which elements having different functions are monolithically integrated can be manufactured with high accuracy and high yield.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a principle configuration of the present invention.

FIG. 2 is an explanatory diagram of a manufacturing process partway through an embodiment of the present invention.

FIG. 3 is an explanatory view of the manufacturing process up to the middle of FIG. 2 and subsequent steps of the embodiment of the present invention.

FIG. 4 is an explanatory view of the manufacturing process up to the middle of FIG. 3 and subsequent steps of the embodiment of the present invention.

FIG. 5 is an explanatory diagram of a manufacturing process of the embodiment of the present invention after FIG. 4;

FIG. 6 is an explanatory diagram of a conventional optical modulator integrated DFB laser.

[Explanation of symbols]

1 Semiconductor Substrate 2 Dielectric Mask 3 Region with Large Area of Opening 4 Region with Small Area of Opening 5 First Semiconductor Layer 6 Light Guide Layer 7 Active Layer 8 Second Semiconductor Layer 9 Contacting First Semiconductor Layer Part 10 Clad layer 11 n-type InP substrate 12 Corrugation 13 SiO ₂ mask 14 Optical modulator formation region 15 Laser formation region 16 InGaAsP optical guide layer 17 MQW active layer 18 p-type AlGaInAs clad layer 19 p-type InP clad layer 20 p ⁺ type InGaAsP contact layer 21 SiO ₂ mask 22 Fe-doped InP buried layer 31 n-type InP substrate 32 Optical modulator formation region 33 DFB laser formation region 34 SiO ₂ mask 35 InGaAsPMQW active layer 36 InGaAsP optical guide layer 37 Corrugation 38 p-type InP cladding Layer 3 p ⁺ type InGaAsP contact layer 40 step

Claims (8)

[Claims] 1. A dielectric mask having an opening provided on a semiconductor substrate, a first semiconductor layer provided in the opening,
At least the second semiconductor layer is provided on the first semiconductor layer and the dielectric mask, and the layer thickness of the first semiconductor layer is an opening in a region where the area of the opening is small. A compound semiconductor device, wherein the second semiconductor layer is thicker than a region having a large area, and the second semiconductor layer is a polycrystalline semiconductor on the dielectric mask. 2. The first semiconductor layer comprises an active layer and a light guide layer, and the portion of the second semiconductor layer in contact with the first semiconductor layer comprises a III-V group compound semiconductor containing Al. The compound semiconductor device according to claim 1, wherein the compound semiconductor device is a clad layer. 3. A dielectric mask having openings having different sizes depending on locations is provided on a semiconductor substrate, and a first semiconductor layer is selectively grown in the openings by using a metal organic chemical vapor deposition method. In a method of manufacturing a compound semiconductor device in which a second semiconductor layer is grown on the entire surface, the layer thickness of the first semiconductor layer is made thicker in a region having a smaller opening area than in a region having a large opening area, Further, a method of manufacturing a compound semiconductor device, wherein a portion of the second semiconductor layer that grows on the dielectric mask is a polycrystalline semiconductor. 4. When growing the first semiconductor layer,
A methyl-based organometallic compound is used as a Ga and In raw material, and an ethyl-based organometallic compound is used as a Ga or In raw material when growing at least a portion of the second semiconductor layer in contact with the first semiconductor layer. The method for manufacturing a compound semiconductor device according to claim 3, wherein the method is used. 5. The manufacturing of a compound semiconductor device according to claim 3, wherein low temperature growth of 500 ° C. or lower is performed when growing at least a portion of the second semiconductor layer in contact with the first semiconductor layer. Method. 6. When growing the first semiconductor layer,
Using halogen or a compound containing halogen, and reducing or stopping the supply of the halogen or the compound containing halogen when growing at least a portion of the second semiconductor layer in contact with the first semiconductor layer. The method for manufacturing a compound semiconductor device according to claim 3, wherein the compound semiconductor device is manufactured. 7. The method according to claim 3, wherein a portion of the second semiconductor layer in contact with the first semiconductor layer is made of a III-V group compound semiconductor containing Al. Method for manufacturing compound semiconductor device. 8. The first semiconductor layer does not contain Al.
8. The method of manufacturing a compound semiconductor device according to claim 7, wherein the active layer and the light guide layer are made of a III-V group compound semiconductor.