JPH07335989A - Compd. semiconductor device and production process thereof - Google Patents

Abstract

PURPOSE:To provide a compd. semiconductor element having a high-reliability interconnection structure made on the basis of the elective epitaxial growth technology. CONSTITUTION:A compd. semiconductor element is composed of a compd. semiconductor substrate 10, compd. semiconductor crystal layer 20 formed on the (111) B face of the substrate, mask layer 12 formed the substrate and contact parts 44 formed on the layer 12. The top face 22A of the layer 20 is composed of the (-1, -1, -1) face and electrodes 40 are formed this face. The layer 20 has at least, one slant face 22B composed of the (0, -1, -1) face. The contact parts 44 are electrically connected to the electrodes 40 through an interconnecting layer 42 extending on the face 22B.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a compound semiconductor device having a wiring structure and manufactured by a selective epitaxial growth technique of a compound semiconductor crystal on a compound semiconductor substrate, and a manufacturing method thereof.

[0002]

2. Description of the Related Art For example, an AlGaAs compound semiconductor crystal layer is formed on a GaAs substrate by metal organic chemical vapor deposition (MOCVD).
Method) has attracted attention in recent years because it can uniformly form a large-area ultra-thin film on a GaAs substrate and is used for mass production of semiconductor lasers and high-mobility transistors. On the other hand, a selective epitaxial growth technique for a GaAs-based compound semiconductor crystal layer on the (111) B plane of a GaAs substrate has been developed (see, for example, literature, S. Ando, e.
t al., "Selective epitaxy of GaAs / AlGaAs on (111) B
substrates by MOCVD and applications to nanometer
structures ", Journal of Crystal Growth 115 (1991),
pp 69-73). Here, the (111) B plane of GaAs means a state in which the outermost surface of the GaAs substrate is composed of an As atomic layer. In addition, in this specification, {h, k,
l} means a family of crystal planes represented by Miller index hkl, (h, k, l) means a specific crystal plane represented by Miller index hkl, and <h, k, l> is Miller index hkl. Means a family of crystal plane directions (orientations), and [h, k, l] means a particular crystal plane direction (orientation) represented by a Miller index hkl. In order to distinguish the crystal planes or the crystal plane directions of the compound semiconductor substrate and the compound semiconductor crystal layer, when a compound semiconductor substrate is shown, a subscript “S” is added, for example, [h, k, l] _S. When the compound semiconductor crystal layer is shown, the subscript “C” is added, for example, [h, k, l] _C.

In the selective epitaxial growth technique for a GaAs-based compound semiconductor crystal, first, as shown in FIG. 12A, a SiO layer having a thickness of about 0.1 μm is formed on a (111) _S B surface of a GaAs substrate 110. _A mask layer 112 made of ₂ or SiN is deposited by the CVD method or the like. next,
As shown in FIG. 12B, the mask layer 112 is removed in a stripe shape or a rectangular shape by using a normal photolithography technique and an etching technique, and the mask layer 11 is removed.
2 has an opening formed on the GaAs substrate 110 (111)
_S B surface is exposed. The exposed GaAs substrate 1
Hereinafter, the portion 10 will be referred to as a window 114. One direction of the window 114 is [0,
1, -1] coincides with the _S direction, 2 [other direction GaAs substrate 110 of the window 114, -1, -1] to match the _S direction, the mask layer 112 portion of the stripe-shaped or rectangular To remove. 12 and 13, a partially cutaway view of the GaAs substrate 110 is shown.

On such a window 114, for example, G
MOCVD of the compound semiconductor crystal layer 120 made of aAs
13A, the (0,1, −1) _C plane of the substrate in the [0,1, −1] _S direction and the [0, −1] of the substrate are grown as shown in FIG. , 1] has a (0, -1, 1) _C plane in the _S direction and (-1, -1, -1) _{C in the} substrate vertical direction.
The compound semiconductor crystal layer 120 having a plane is crystal-grown.
On the other hand, the compound semiconductor crystal layer 120 is, as shown in the schematic sectional view of FIG. 13B, obtained by cutting the compound semiconductor crystal layer along the [2, -1, -1] _S direction of the substrate. of substrate [2, -1, -1] _S direction (0, -1, -1) has a _C-plane, the [-2,1,1] _S direction of the substrate (0,1,
1) It has a _C side. In FIG. 13B, the length of the compound semiconductor crystal layer 120 is shortened and drawn. The (0, 1, −1) _C plane of the compound semiconductor crystal layer 120 and the (0,
-1, 1) _C plane is perpendicular to the substrate 110,
The (0, -1, -1) _C- plane and the (0,1,1) _C- plane form an angle of about 35 ° with the substrate. Then, as shown in FIG. 13A, the compound semiconductor crystal layer 120 is grown only on the window 114, and the compound semiconductor crystal layer 120 is not grown on the mask layer 112. still,
Thus, the growth of the compound semiconductor crystal layer 120 exclusively in the film thickness direction is called the growth of the compound semiconductor crystal layer in the substrate vertical direction or the vertical growth mode.

On the other hand, when the crystal growth conditions in the MOCVD method are changed, not only the compound semiconductor crystal layer 120 grows in its film thickness direction, but also on the mask layer 112, as shown in FIG. Then, the compound semiconductor crystal layer 12
0 overhangs and grows on the mask layer 112. Such growth of the compound semiconductor crystal layer is referred to as growth of the compound semiconductor crystal layer in the horizontal direction of the substrate or horizontal growth mode.
Even in such a horizontal growth mode, the compound semiconductor crystal layer 120 is shown in (B) of FIG. 13 in the [2, -1, -1] _S direction and the [-2,1,1] _S direction of the substrate. As shown in the schematic cross-sectional view, it has a (0, -1, -1) _C plane and a (0,1,1) _C plane.

In the prior art, trimethylgallium (TMG) is used as a Ga raw material and arsine (AsH ₃ ) is used as an As raw material in order to grow a GaAs compound semiconductor crystal layer by MOCVD. M
In order to obtain the vertical growth mode in the OCVD method, the GaAs substrate 110 is usually heated to about 800 ° C.
MG about 2.3 × 10 ^-6 atmosphere, arsine about 3 × 10 ^-5
Atmospheric pressure (arsine / TMG gas partial pressure ratio = about 13) is used.
The heating temperature of the GaAs substrate 110 is lowered and arsine /
As the TMG gas partial pressure ratio is increased, the horizontal growth mode comes to be recognized. For example, GaAs substrate 110
Heating temperature is about 600 ° C, TMG is about 2.3 × 10 ^-6
Atmospheric pressure, arsine approximately 2 × 10 ^-4 atm (arsine / TMG
When the gas partial pressure ratio = about 87), the crystal growth rate in the horizontal direction of the substrate is approximately 23 times the crystal growth rate in the vertical direction of the substrate, and a substantially horizontal growth mode can be achieved.
The substrate horizontal direction means a direction parallel to the surface of the GaAs substrate 110, and the substrate vertical direction means the GaAs substrate 110.
Means the direction perpendicular to the surface of the.

As described above, by combining the vertical growth mode and the horizontal growth mode, a plurality of compound semiconductor crystal layers (for example, a buffer layer, a first cladding layer, an active layer,
It is possible to form a compound semiconductor device (for example, a compound semiconductor device having a semiconductor laser structure) including a second clad layer and a cap layer) on a compound semiconductor substrate. By forming these compound semiconductor crystal layers based on the above method, it is possible to form a compound semiconductor device having a semiconductor laser structure composed of, for example, a refractive index waveguide structure, by a single epitaxial growth, and to separate the devices. Done.

[0008]

When the compound semiconductor crystal layer 120 thus formed has a normal semiconductor laser structure, it protrudes from the surface of the compound semiconductor substrate 110 by about 2 μm. Usually, an electrode is formed on the top surface of the compound semiconductor crystal layer 120, and the compound semiconductor substrate 110 is formed.
A contact portion is formed on the mask layer 112 formed above. Then, it is necessary to electrically connect the electrode and the contact portion with a wiring layer.

As described above, when there is a large step between the top surface of the compound semiconductor crystal layer 120 and the mask layer 112,
A technique for filling the step is required to form the wiring layer. That is, when a conventional method for forming electrodes, contact portions and wiring layers is applied to a compound semiconductor element manufactured based on a selective epitaxial growth technique for a compound semiconductor crystal on a compound semiconductor substrate, first, a coating method or the like is used. For example, a planarization film 130 made of polyimide or the like is formed on the entire surface of the mask layer 112 including the compound semiconductor crystal layer 120 (see FIG. 14A). Then, the flattening film 13
0 is entirely etched to leave the flattening film 130 on the side surface of the compound semiconductor crystal layer 120, and the mask layer 1
The flattening film 130 is removed from above 12 and on the top surface of the compound semiconductor crystal layer 120 (see FIG. 14B). After that, the electrode 140A, the contact portion 140B, and the wiring layer 1
A metal wiring material for forming 40C is formed by, for example, a vacuum evaporation method or a sputtering method, and the electrode 140A, the contact portion 140B, and the wiring layer 140 are formed by using a lift-off method or the like.
Pattern C into a desired shape (see FIG. 14C).

However, when such a conventional method is applied to the above-mentioned compound semiconductor device, the reliability of the wiring layer 140C at the edge of the top surface of the compound semiconductor crystal layer 120 is reduced, and the wiring layer on the mask layer 112 is reduced. The decrease in reliability of 140C and the contact portion 140B becomes a problem.

Further, since the light emitting end face of the compound semiconductor element is buried in the flattening film 130, it is extremely difficult to remove the flattening film 130 near the light emitting end face.

As shown in FIG. 15, there is also a method of forming electrodes, contact portions and wiring layers by an oblique vapor deposition method without forming a flattening film. However, in such an oblique deposition method, the compound semiconductor crystal layer 12
0, the reliability of the wiring layer at the edge of the top surface of 0, the wiring layer 140C at the lower side surface of the compound semiconductor crystal layer 120
The decrease in reliability is a problem.

Therefore, an object of the present invention is to provide a compound semiconductor device having a highly reliable wiring structure, which is manufactured based on the selective epitaxial growth technique of a compound semiconductor crystal on a compound semiconductor substrate, and a manufacturing method thereof. To do.

[0014]

The above object is to provide a compound semiconductor substrate, a compound semiconductor crystal layer formed on the {111} B plane of the compound semiconductor substrate, and a mask layer formed on the compound semiconductor substrate. A compound semiconductor element comprising a contact portion provided on the top surface of the compound semiconductor crystal layer is composed of {-1, -1, -1} planes,
An electrode is formed on the top surface, and at least one slope is formed in the compound semiconductor crystal layer, and the slope is mainly composed of {0, -1, -1} planes and is used as a contact portion. This can be achieved by the compound semiconductor device of the present invention, which is electrically connected to the electrode by a wiring layer extending on the slope.

The above objects are further (a) a step of forming a mask layer on the {111} B plane of the compound semiconductor substrate and then forming an opening in the mask layer; A compound semiconductor crystal is selectively grown on the {111} B plane of the compound semiconductor substrate exposed at the bottom, and {−1, −
A step of forming a compound semiconductor crystal layer having at least a top surface composed of 1, -1} planes and a slope mainly composed of {0, -1, -1} surfaces; and (c) an electrode on the top surface. And forming a contact portion on the mask layer, and at the same time, forming a wiring layer extending on this slope for electrically connecting the contact portion and the electrode. This can be achieved by the method for producing a compound semiconductor device of.

In the compound semiconductor device and the method of manufacturing the same of the present invention, the materials constituting the electrodes, wiring layers and contact portions depend on the composition and conductivity type of the compound semiconductor crystal layer on which the electrodes are to be formed. When the compound semiconductor crystal layer on which the electrode is to be formed is n-type GaAs, the electrode,
As a material for forming the wiring layer and the contact portion, Au-
Ge-Ni, Au-Ge-Pt, Ag-In-Ge, N
Examples thereof include i-Ge, Au-Te-Ni, and Au-Ge / Au. Among them, Au-Ge / Au (Au-G
e and Au) are preferably used. When the compound semiconductor crystal layer on which the electrode is to be formed is p-type GaAs,
As materials for the electrodes, wiring layers and contact parts,
Although Au-Zn, Au-Zn / Au, and Au-Mg can be mentioned, it is preferable to use Au-Zn / Au (Au-Zn and Au) especially. When the compound semiconductor crystal layer on which the electrode is to be formed is n-type InP, the electrode,
As a material for forming the wiring layer and the contact portion, Au-
Ge-Ni can be mentioned. When the compound semiconductor crystal layer on which the electrode is to be formed is p-type InP, the electrode,
As a material for forming the wiring layer and the contact portion, Au-
Zn can be mentioned. When the compound semiconductor crystal layer on which the electrode is to be formed is n-type AlGaAs, the electrode,
As a material for forming the wiring layer and the contact portion, Au-
Ge-Ni can be mentioned. When the compound semiconductor crystal layer on which the electrode is to be formed is p-type AlGaAs,
As materials for the electrodes, wiring layers and contact parts,
Au-Zn and Au-Mg can be mentioned. The compound semiconductor crystal layer on which the electrode is to be formed is n-type InGa
In the case of As, Au-Ge-Ni can be cited as a material forming the electrode, the wiring layer and the contact portion.
The compound semiconductor crystal layer on which the electrode is to be formed is p-type I
In the case of nGaAs, Au-Zn / Au can be cited as a material forming the electrodes, the wiring layer and the contact portion.

It is preferable that the step of forming the electrode, the wiring layer and the contact portion includes the step of forming the above-mentioned materials by a vacuum deposition method or a sputtering method. As a method for forming an electrode, an alloying method such as a furnace alloy method, an electron beam alloy method, a laser alloy method, an infrared lamp alloy method, in which a furnace is used to raise and lower the temperature in a hydrogen gas or nitrogen gas atmosphere Etc. can be mentioned.

[0018]

In the present invention, by selectively growing the compound semiconductor crystal, the compound semiconductor crystal layer is formed with the inclined surface mainly composed of the {0, -1, -1} plane, and the compound semiconductor crystal layer is contacted with the contact portion. The electrodes are electrically connected by a wiring layer extending on the slope. The slope formed by the {0, -1, -1} plane is mainly about 3 with respect to the compound semiconductor substrate.
Since the electrodes are only inclined by 5 °, the electrodes and the contact portions formed on the compound semiconductor substrate can be electrically connected by a wiring layer having high reliability. In the present invention, since the slope formed on the compound semiconductor crystal layer has the same function as the flattening film, it is not necessary to form the flattening film as in the conventional technique. Further, the electrodes and the contact portions can be electrically connected without using the oblique deposition method.

Further, a compound semiconductor device can be manufactured by one-time crystal growth, and a light emitting surface (for example, a laser resonance surface) can be formed without requiring any special device isolation technology, cleavage technology, or etching technology. Since it can be formed, the process can be simplified and a high quality light emitting surface can be formed.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will now be described based on embodiments with reference to the drawings.

Example 1 FIG. 1 shows a schematic plan view of a compound semiconductor device of Example 1 having a semiconductor laser structure. 2A, 2B, and 2C are schematic cross-sectional views of the compound semiconductor element taken along line AA, line BB, and line CC in FIG. The examples will be described below based on the specific crystal planes and directions, but it goes without saying that the specific crystal planes and directions in these descriptions can be extended to their families. Also, in the plan view,
In order to clarify the difference in the crystal planes, some diagonal lines are added.

As shown in FIGS. 1 and 2, the compound semiconductor device of Example 1 includes a compound semiconductor substrate 10, a compound semiconductor crystal layer 20 formed on the (111) _SB plane of the compound semiconductor substrate, and The contact portion 44 is provided on the mask layer 12 formed on the compound semiconductor substrate 10. Then, the top surface 22A of the compound semiconductor crystal layer 20
Is composed of a (-1, -1, -1) _C plane, and an electrode 40 is formed on the top surface 22A. On the other hand, at least one slope 22B is formed in the compound semiconductor crystal layer 20, and the slope 22B is (0, -1, -1).
It is composed of the _C side. The other side surface of the compound semiconductor crystal layer 20 is a first side surface 22C composed of a (0,1, -1) _C plane, a second side surface 20D composed of a (0,1,1) _C plane, Third (0, -1, 1) _C plane
It is the side surface 20E. Top surface 2 of compound semiconductor crystal layer 20
2A, slope 22B, first, second and third side surfaces 20C,
20D and 20E are formed based on the selective epitaxial growth technique of the compound semiconductor crystal on the compound semiconductor substrate. The mask layer 12 is made of, for example, SiO ₂ or SiN.

The (0, -1, -1) _C plane which is the slope 22B of the compound semiconductor crystal layer 20 and the (0,1,1) _C plane which is the second side surface 22D of the compound semiconductor crystal layer 20 include 2, -1, -1,]] is formed in a direction perpendicular to the _S direction. These (0, -1, -1,) _C planes and (0,1,
1) The _C plane is a plane having an angle of about 35 ° with respect to the compound semiconductor substrate 10. The first and third side faces 20C and 20E composed of the (0,1, -1) _C plane and the (0, -1,1) _C plane are [0,1] of the compound semiconductor substrate 10.
It is formed in a direction perpendicular to the [-1] direction. Then, these side surfaces 20C and 20E of the compound semiconductor crystal layer 20.
Is a surface perpendicular to the compound semiconductor substrate 10. In the compound semiconductor device of Example 1 having the semiconductor laser structure, the (0,1, -1) _C plane and the (0, -1,1) _C plane are used.
The first and third side surfaces 20C and 20E formed by the surface correspond to the laser resonance surface, and the laser light is emitted from this side surface.

The contact portion 44 and the electrode 40 are electrically connected to each other by a wiring layer 42 extending from the top surface 22A of the compound semiconductor crystal layer 20 over the slope 22B and over the mask layer 12. In the first embodiment, the material forming the electrode 40, the wiring layer 42, and the contact portion 44 is Au—Zn / Au. Reference numeral 46 is a dummy contact portion that is formed at the same time when the electrode 40 and the like are formed, and has no function.

In Example 1, the compound semiconductor substrate 1
0 consists of n-type GaAs. In addition, the compound semiconductor crystal layer 20 has an n-type structure as shown in FIG.
Type GaAs buffer layer 30, n-type AlGaAs
First clad layer 32 made of GaAs, active layer 34 made of GaAs, second clad layer 3 made of p-type AlGaAs
6 and a cap layer 38 made of p-type GaAs.

Hereinafter, with reference to FIGS. 3 and 4, the compound semiconductor substrate 10 is formed on the (111) _S B plane by the selective epitaxial growth technique of the compound semiconductor crystal.
A method for manufacturing the compound semiconductor device of Example 1 will be described.

[Step-100] First, the mask layer 12 is formed on the (111) _S B surface of the compound semiconductor substrate 10 made of n-type GaAs. The mask layer 12 is made of SiO ₂ or SiN having a thickness of about 0.1 μm, and is formed by ordinary CVD.
It can be formed by a method or the like.

[Step-110] Next, an opening is formed in the mask layer 12 by using a photolithography technique and an etching technique. In Example 1, the planar shape of the opening was rectangular. The opening has two sides 16A in a direction parallel to the [2, -1, -1] _S direction of the compound semiconductor substrate 10.
With 16C. Further, the opening has two sides 16B, 1 in a direction parallel to the [0, 1, -1] _S direction of the compound semiconductor substrate.
With 6D. The compound semiconductor substrate 10 is provided on the bottom of the opening.
Is exposed, and this portion is the window 14. Such an opening is shown in the schematic plan view of FIG. 3A and the schematic partial cross-sectional view of FIG. 3B. Incidentally, FIG.
3B is a partial cross-sectional view taken along the line BB of FIG.

[Step-120] Thereafter, the compound semiconductor crystal layer 20 is selectively grown on the (111) _S B surface of the compound semiconductor substrate 10 corresponding to the window 14 exposed at the bottom of the opening. . In the first embodiment, the compound semiconductor substrate 10 is made of n-type GaAs. On the other hand, the compound semiconductor crystal layer 20 includes a buffer layer 30 made of n-type GaAs and a first cladding layer 3 made of n-type AlGaAs.
2, an active layer 34 made of GaAs, a second cladding layer 36 made of p-type AlGaAs, and a cap layer 38 made of p-type GaAs. Each layer is MOCV.
Using device D, selective growth is performed by MOCVD. The conditions for forming each layer are illustrated below. Further, FIG. 4 shows a schematic cross-sectional view of the compound semiconductor crystal layer according to the formation stage of each layer. The cross-sectional views of FIGS. 4A, 4B, and 4C correspond to the cross-sectional view taken along the line BB of FIG. 1, but the compound semiconductor substrate 10 [0, 1, -1 ] The length along the _S direction was drawn extremely short. The sectional view of FIG. 4D corresponds to the sectional view taken along the line AA of FIG. The supply amount of the raw material gas was expressed by the partial pressure in the MOCVD reactor. The total pressure inside the MOCVD reactor was set to 0.1 atm.

[Step-120A] (Formation of Buffer Layer 30) First, the buffer layer 30 made of n-GaAs and having a thickness of 0.2 μm was formed in the window 14 of the compound semiconductor substrate 10 under the following conditions. Under the following conditions, the growth of the buffer layer 30 is exclusively in the vertical growth mode. The electron concentration of the buffer layer 30 was set to 1 × 10 ¹⁸ / cm ³ . Substrate heating temperature: 800 ° C Ga source gas: TMG (trimethylgallium) supply amount: 2.3 × 10 ⁻⁶ atm As source gas: arsine source gas partial pressure ratio: 20 n-type dopant: Si ₂ H ₆ supply amount: 1 × 10 ^-8 atmosphere Here, the source gas partial pressure ratio means the partial pressure ratio of group V source gas / group III source gas.

[Step-120B] (Formation of First Cladding Layer 32) Next, n-Al _0.3 Ga is formed on the buffer layer 30 and on the side wall.
_A first cladding layer 32 made of _0.7 As was formed (see FIG. 4A). The first cladding layer 32 under the following conditions
, The first cladding layer 32 grows in the horizontal growth mode. As a result, the first cladding layer 32 having a thickness of 0.8 μm was formed on the buffer layer 30, and the first cladding layer 32 having a width of 0.4 μm was formed on the sidewall of the buffer layer 30. The electron concentration of the first cladding layer 32 was set to 3 × 10 ¹⁷ / cm ³ . Substrate heating temperature: 800 ° C Ga raw material gas: TMG supply amount: 2.3 × 10 ⁻⁶ atm As raw material gas: arsine raw material gas partial pressure ratio: 200 Al raw material gas: TMAl (trimethylaluminum) supply amount: 0.35 × 10 ⁻⁶ atm n-type dopant: Si ₂ H ₆ supply amount: 1 × 10 ⁻⁸ atm

[Step-120C] (Formation of Active Layer 34) Next, an active layer 34 made of GaAs and having a thickness of 0.08 μm was formed on the first cladding layer 32. Under the following conditions, the growth of the active layer 34 is exclusively in the vertical growth mode. The active layer 34 is not doped. Substrate heating temperature: 800 ° C Ga raw material gas: TMG supply amount: 2.3 × 10 ⁻⁶ atm As raw material gas: arsine raw material gas partial pressure ratio: 20

[Step-120D] (Formation of Second Cladding Layer 36) Next, p-type Al _0.3 Ga _0.7 As is formed on the active layer 34 and on the sidewalls of the active layer 34 and the first cladding layer 32. The second cladding layer 36 was formed (see FIG. 4B). The growth of the second cladding layer 36 is in the horizontal growth mode under the following conditions. As a result, the second clad layer 36 having a thickness of 0.8 μm is formed on the active layer 34, and the second clad layer having a width of 0.4 μm is formed on the sidewalls of the active layer 34 and the first clad layer 32. 36 was formed. still,
The hole concentration of the second cladding layer 36 is set to 5 × 10 ¹⁷ / cm ³
And Substrate heating temperature: 750 ° C Ga raw material gas: TMG supply amount: 2.3 × 10 ⁻⁶ atmospheric pressure As raw material gas: arsine raw material gas partial pressure ratio: 600 Al raw material gas: TMAl supply amount: 0.35 × 10 ⁻⁶ atmospheric pressure p-type dopant: DMZn supply amount: 1 cc / min

[Step-120E] (Formation of Cap Layer 38) After that, p-type-G is formed on the second cladding layer 36 and on the sidewalls.
A cap layer 38 made of aAs was formed. Under the following conditions, the growth of the cap layer 38 is in the horizontal growth mode. As a result, a thickness of 0.
A cap layer 38 having a thickness of 4 μm was formed, and a cap layer 38 having a width of 0.2 μm was formed on the sidewall of the second cladding layer 36. The hole concentration of the cap layer 38 is 3 × 10 ¹⁸ / c
It was m ^3. Substrate heating temperature: 750 ° C. Ga source gas: TMG supply rate: 2.3 × 10 ⁻⁶ atm As source gas: arsine source gas partial pressure ratio: 600 p-type dopant: DMZn (dimethylzinc) supply rate: 1 cc / min

Thus, (-1,-) is formed on the (111) _S B surface of the compound semiconductor substrate 10 exposed at the bottom of the opening.
1, -1) a top surface 22A composed of a _C plane, and (0, -1,-
1) It is possible to form the compound semiconductor crystal layer 20 having at least the slope 22B composed of the _C- plane.

Undesired crystal planes (-1, 0, -1) _C- plane 22F and (0, -1, -1) _C- plane 22C and (0, -1, 1) _C- plane 22E are provided at the ends. (-1, -1, 0) _C
The surface 22G may be formed (see FIGS. 1 and 2C).

[2, -1,-of the compound semiconductor substrate 10
1] With respect to the _S direction, the compound semiconductor crystal is [0,-
1, -1] _C direction, [0,0, -1] _C direction, and [0,
-1,0] Crystal growth in the _C direction. However, the growth rate of the compound semiconductor crystal is [0, 0, -1] _C direction and [0, 0
The -1,0] _C direction is faster than the [0, -1, -1] _C direction. As a result, the compound semiconductor substrate 10 [2, -1,
−1] In the _S direction, the (0, −1, −1) _C plane 22B is finally formed in the compound semiconductor crystal layer.

On the other hand, the compound semiconductor substrate 10 [-2,
1, 1] For the _S direction, the compound semiconductor crystal
Crystals grow in the [0,1,1] _C direction, the [0,0,1] _C direction, and the [0,1,0] _C direction. However, the growth rate of the compound semiconductor crystal is higher in the [0,0,1] _C direction and the [0,1,0] _C direction than in the [0,1,1] _C direction. As a result, the compound semiconductor substrate 10 [-2, 1,
1] In the _S direction, the (0,1,1) _C plane 22D is finally formed in the compound semiconductor crystal layer.

[0, 1, 1 of the compound semiconductor substrate 10
−1] For the _S direction, the compound semiconductor crystal is [0,
1, −1] _C direction, [−1, 0, −1] _C and [0, 0,
-1] Crystal growth in the _C direction. However, the growth rate of the compound semiconductor crystal is [0, 0, -1] in the _C direction [0,
1, -1] _C direction and [-1,0, -1] _C direction earlier. As a result, the compound semiconductor substrate 10 [0, 1,-
1] In the _S direction, the (0,1, -1) _C plane and the (-1,0, -1) _C plane are mainly formed in the compound semiconductor crystal layer.

However, in the region indicated by "X" in FIG. 1, the crystal growth in the [0,1, -1] _C direction of the compound semiconductor crystal hardly progresses, and the compound semiconductor crystal [-1,
0, -1] Crystal growth in the _C direction becomes dominant. On the other hand, with respect to the [−2,1,1] _S direction of the compound semiconductor substrate 10, the compound semiconductor crystal grows in the [0,1,1] _C direction. As a result of such crystal growth of the compound semiconductor crystal, in the region “X”, as shown in the schematic cross-sectional view of FIG. 2C, (0, 1, 1) _C plane 22D and (−
1,0, -1) A complex crystal plane in which the _C plane 22F is compounded is formed. In regions other than the region X in the [0,1, -1] _C direction of the compound semiconductor crystal layer, the crystal growth in the [0,1, -1] _C direction of the compound semiconductor crystal becomes dominant. As shown in FIG. 7B, the (0,1, -1) _C plane 22C is formed.

[0, -1, 1] of the compound semiconductor substrate 10
Similarly, in the _S direction, [0,
Crystal growth in the -1,1] _C direction and the [-1, -1,0] _C direction is dominant. As a result, in the region indicated by “Y” in FIG. 1, as in the schematic cross-sectional view shown in FIG. 2C, the (0,1,1) _C plane 22D and (−1, −1) , 0) _C
A complex crystal face in which the face 22G is compounded is formed. Also,
In regions other than the region Y, the crystal growth of the compound semiconductor crystal in the [0, -1,1] _C direction becomes dominant, and as a result, as shown in FIG. ) _C- face 22E is formed. The size of these regions X and Y is approximately the same as the thickness of the compound semiconductor crystal layer 20.

(-1, 0, -1) _C plane 22F and (-
When these undesired crystal planes such as the (-1, -1,0) _C- plane 22G are formed, the entire (0,1, -1) _C- plane 22C and the (0, -1, -1) _C- plane 22E become It does not become the laser resonance plane. In order to remove such an undesired surface, ion implantation may be performed on the compound semiconductor crystal layer on the outer side (lower side in FIG. 1) of the dotted line in FIG. As a result, the current flowing through the active layer 34 is narrowed and the influence of the unwanted crystal plane is eliminated. Alternatively, the outside of the dotted line in FIG.
Then, the lower side) compound semiconductor crystal layer may be selectively removed by a vapor phase etching method.

[Step-120B], [Step-120]
D] or [step-120E] in the horizontal growth mode, depending on the conditions of MOCVD, as shown in the schematic partial sectional view of FIG. ] In the direction perpendicular to the _S direction, (0,-
1, -1) with _C-plane (1, -1, -1) _C plane is grown,
The (-1,1,1) _C plane may grow together with the (0,1,1) _C plane. The angle formed by the (1, -1, -1) _C plane and the (-1,1,1) _C plane with the compound semiconductor substrate 10 is about 70 °. As described above, even when the slope 22B formed in the compound semiconductor crystal layer 20 is composed of the (0, -1, -1) _C plane and the (1, -1, -1,) _C plane, In the present invention, the slope 22B is mainly composed of {0,
It is assumed to be composed of a -1, -1} plane.

[Step-130] After that, an n-type electrode (not shown) is formed on the bottom surface of the compound semiconductor substrate 10 by a usual method. Then, the p-type electrode 40 is formed on the top surface 22A of the compound semiconductor crystal layer 20 (specifically, on the cap layer 38), the contact portion 44 is formed on the mask layer 12, and the contact portion 44 and the electrode are also formed. A wiring layer 42 extending from the top surface 22A of the compound semiconductor crystal layer to the slope 22B and the mask layer 12 is formed to electrically connect the wiring layer 40 to the wiring layer 40 (see FIGS. 1 and 2 (A) and (B)). reference). Therefore, first, for example, Au—Zn is formed on the entire surface in a direction perpendicular to the compound semiconductor substrate 10 by a vacuum evaporation method, and an Au—Zn layer is deposited on the entire surface. Then, heat treatment is performed at 450 ° C. for 1 minute in a forming gas composed of a mixed gas of nitrogen gas and hydrogen gas to form an alloy. Next, an Au layer is formed on the entire surface by, for example, a vacuum vapor deposition method. Then, using, for example, an ion milling method or a photolithography technique and an etching technique, Au-Z
The n / Au layer is patterned into a desired shape. The Au—Zn / Au layer can also be patterned into a desired shape by using the lift-off method. Thus, the cap layer 38
A p-type electrode 40 is formed on top.

Simultaneously with the formation of the electrode 40, the contact portion 44 can be formed on the mask layer 12 formed on the surface of the compound semiconductor substrate 10 from the same material as the electrode constituent material. The electrode 40 and an external power source can be easily electrically connected via the contact portion 44. Further, the electrode 40 and the contact portion 44 are formed simultaneously with the formation of the electrode 40 by the wiring layer 42 made of the same material as the electrode constituent material.
Electrically connected with. The wiring layer 42 has a slope 22B formed by the (0, -1, -1) _C plane of the compound semiconductor crystal layer.
Extending above. (0, -1,-of the compound semiconductor crystal layer
1) Since the slope 22B composed of the _C plane is mainly inclined by about 35 ° with respect to the compound semiconductor substrate 10, the electrode 40 formed on the cap layer 38 and the contact on the compound semiconductor substrate 10 are contacted. The portion 44 can be electrically connected to the wiring layer 42 having high reliability.

Further, as shown in the schematic sectional view of FIG. 6, when a plurality of compound semiconductor elements are formed on a compound semiconductor substrate, and when performing vacuum deposition or the like of an electrode constituent material, the compound semiconductor substrate 10 [ -2,1,1] The so-called shadow effect is generated by the portion of the compound semiconductor crystal layer 20 that projects in the _S direction. As a result, electrical conduction between the electrode 40 formed on the cap layer of a certain compound semiconductor element and the contact portion 44 of the adjacent compound semiconductor element can be surely suppressed, and the element of the compound semiconductor element can be surely suppressed. The separation can be done by itself.

By forming the first cladding layer 32 on the side wall of the buffer layer 30, it is possible to prevent the generation of a leak current from the second cladding layer 36 to the buffer layer 30. In addition, the active layer 34 and the first cladding layer 32
The second cladding layer 36 on the sidewall of the
And a cap layer 38 is grown on the side wall of the second cladding layer 36, whereby a stable compound semiconductor device (for example, a semiconductor laser) with little change over time can be manufactured.

When the compound semiconductor crystal layer is formed by the MOCVD method, the (0,1, -1) _C plane 2 which is the light emitting surface is formed.
2C (first side surface) and (0, -1,1) _C surface 22E
Since the (third side surface) is formed by itself, no special element isolation technique, cleavage technique, or etching technique is required. Therefore, it is possible to suppress the occurrence of light scattering and defects on the light emitting surfaces 22C and 22E, and it is possible to give high reliability to the light emitting surface corresponding to the laser resonance surface, for example. Furthermore, according to the method for manufacturing the compound semiconductor device of Example 1,
A compound semiconductor device can be manufactured by performing crystal growth once.

Example 2 Example 2 is a modification of the compound semiconductor device of Example 1. FIG. 7A shows a schematic plan view of a compound semiconductor device of Example 2 having a semiconductor laser structure. 7B is a schematic partial cross-sectional view of the compound semiconductor element taken along the line BB in FIG. 7A.

The compound semiconductor device of Example 2 differs from that of Example 1 in that the planar shape of the compound semiconductor device is a substantially "T" shape rotated by 90 °. The compound semiconductor crystal layer 20 includes a top surface 24A, four side surfaces 24B, 24.
C, 24D and 24E are formed. Side face 24C,
24E is a crystal plane naturally formed by selective epitaxial growth of a compound semiconductor crystal.
-1) _C plane and (0, -1, 1) _C plane. On the other hand, the side surfaces 24B and 24D are surfaces formed by the vapor phase etching technique and correspond to light emitting surfaces. As described in Example 1, the compound semiconductor substrate 10 [2, -1,-
1] In the _S direction, the (0, -1, -1) _C plane is formed in the compound semiconductor crystal layer 20, and in the [-2,1,1] _S direction of the compound semiconductor substrate 10, the compound semiconductor crystal is formed. Layer 20 has (0,1,1) _C- plane, (-1,0,-)
1) _C- plane and (-1, -1,0) _C- plane are formed. Such a crystal plane is shown by a dotted line in FIG. After the compound semiconductor crystal layer 20 is formed, a part of the compound semiconductor crystal layer including these crystal planes is removed by using the vapor phase etching technique, so that the side faces (end faces) 20B and 20D which are the light emitting faces.
Can be formed.

In the compound semiconductor crystal layer 20, from the side surface 24E of the compound semiconductor crystal layer 20, which is, for example, the (0, -1,1) _C plane, the [0, -1,
1] A protrusion region 26 extending in the _S direction is formed. In the portion of the protruding region 26 in the [2, -1, -1] _S direction of the compound semiconductor substrate 10, (0, -1, -1) _C
An inclined surface 26B composed of a surface is formed. on the other hand,
A side surface 26D composed of a (0,1,1) _C plane is formed in the portion of the protruding region 26 in the [−2,1,1] _S direction of the compound semiconductor substrate 10. In addition, a side surface 26E constituted by a (0, -1,1) _C plane is formed in a portion of the protruding region 26 in the [0, -1,1,] _S direction of the compound semiconductor substrate 10.

An electrode 40 is formed on the top surface 24A of the compound semiconductor crystal layer 20. On the other hand, compound semiconductor substrate 1
On the mask layer 12 formed on the
4 are formed. The electrode 40 and the contact portion 44 are electrically connected by the wiring layer 42 extending from the electrode 40 on the top surface of the projection region 26 and on the slope 26B in the projection region.

In the method of manufacturing the compound semiconductor device of Example 2, the planar shape of the opening to be formed in the mask layer 12 is different from that of Example 1, and the vapor phase etching technique after forming the compound semiconductor crystal layer 20. Side face (end face) using
Since it can be manufactured by the same method as the compound semiconductor device of Example 1 except that B and 20D are formed, detailed description thereof will be omitted. The plane shape of the opening may be a substantially "T" shape rotated by 90 °.

(Embodiment 3) The compound semiconductor device of Embodiment 3 is composed of a lateral pin photodiode. As shown in the schematic partial cross-sectional view of FIG. 8C, the compound semiconductor device of Example 3 has the same structure as (11) of the compound semiconductor substrate 10.
1) n-type layer 50 made of n ⁺ -GaAs formed on the _S- plane, i-layer (light absorption layer) 51 made of i-GaAs formed on the side wall of the n-type layer 50, side wall of the i-layer 51 A p-type layer 52 made of p-GaAs and a light transmitting layer 53 made of i-AlGaAs formed on the entire surface. These n-type layer 50, i-layer (light absorbing layer) 51, p-type layer 52,
The light transmitting layer 53 constitutes a compound semiconductor crystal layer. Further, in the compound semiconductor device of Example 3, the p-type electrode 54 and the p-type layer 52 formed on the top surface of the compound semiconductor crystal layer.
A wiring layer 56 formed on the inclined surface 52A (consisting of (0, -1, -1) _C plane) formed on the mask layer 12 formed on the compound semiconductor substrate 10. Contact portion 55. The material forming the electrode 54, the contact portion 55, and the wiring layer 56 is Au—Zn /
It is Au.

A method of manufacturing a compound semiconductor element composed of a lateral pin photodiode will be described below with reference to FIG. 8. The supply amount of the raw material gas is represented by the partial pressure in the MOCVD reactor. The total pressure inside the MOCVD reactor was set to 0.1 atm.

[Step-300] (Preparation of Substrate) First, (11) of the compound semiconductor substrate 10 made of GaAs is prepared.
1) The window 14 is formed on the _S B surface by the same method as in [Step-100] of the first embodiment.

[Step-310] (Formation of n-Type Layer 50) Next, on the window 14 of the compound semiconductor substrate 10, an n ⁺ -GaAs layer having a thickness of 1.5 μm was formed under the following conditions.
The mold layer 50 was formed. This n-type layer 50 was grown exclusively in the vertical growth mode. Substrate heating temperature: 700 ° C. Ga source gas: TEG (triethylgallium) supply amount: 2.6 × 10 ⁻⁶ atm As source gas: arsine source gas partial pressure ratio: 200 n-type dopant: Si ₂ H ₆ supply amount: 1 × 10 ^-8 bar

[Step-320] (Formation of i-layer 51) Next, an i-layer (light absorption layer) 51 made of i-GaAs was formed on the upper and side walls of the n-type layer 50. The i layer 51 was grown in the horizontal growth mode. As a result, an i layer 51 having a thickness of 0.5 μm is formed on the n-type layer 50, and the n-type layer 5 is formed.
An i layer 51 having a width of 2 μm was formed on the side wall of 0. Substrate heating temperature: 700 ° C Ga source gas: TMG supply amount: 2.6 × 10 ^-6 atmospheres As source gas: Arsine and TMAs (trimethylarsenic) source gas partial pressure ratio: 50 (Arsine / TMG) 150 (TMAs / TMG) By simultaneously introducing arsine and TMAs as As source gases in this way, the carrier concentration of the i layer 51 can be made low.

[Step-330] (Formation of p-type layer 52) After that, the p-type layer 52 made of p-GaAs was formed on the i-layer 51 and on the side wall (see FIG. 8A). This p
The mold layer 52 was grown in the horizontal growth mode. As a result, the p-type layer 52 having a thickness of 0.2 μm is formed on the i-layer 51, and the p-type layer 52 having a width of 0.5 μm is formed on the sidewall of the i-layer 51.
Was formed. The p-type layer 52 has an inclined surface 52A formed of a (0, -1, -1) _C plane. Substrate heating temperature: 700 ° C. Ga source gas: TMG supply amount: 2.6 × 10 ⁻⁶ atm As source gas: TMAs (trimethylarsenic) source gas partial pressure ratio: 200

[Step-340] Next, each compound semiconductor crystal layer above the plane including the top surface of the n-type layer 50 is etched with a normal alkaline solution (see FIG. 8B). . As a result, a lateral pin photodiode is formed.

[Step-350] (Formation of Light Transmission Layer 53) Thereafter, the light transmission layer 53 made of i-AlGaAs is formed on the entire surface.
To form. The growth of the light transmission layer 53 was performed exclusively in the vertical growth mode. As a result, a light transmitting layer 53 having a thickness of 0.3 μm was formed on the entire surface. Substrate heating temperature: 700 ° C Ga raw material gas: TEG supply amount: 2.6 × 10 ⁻⁶ atmospheric pressure As raw material gas: arsine raw material gas partial pressure ratio: 200 Al raw material gas: TMAl supply amount: 0.6 × 10 ⁻⁶ atmospheric pressure

[Step-360] Next, an Au-Ge / Au electrode (not shown) is formed on the back surface of the compound semiconductor substrate 10. On the other hand, after forming an opening for forming an electrode in the light transmitting layer 53 by using a normal lithography technique and an etching technique, Au—Zn and Au are deposited on the entire surface by a vacuum deposition method or a sputtering method. And 45
After the alloying treatment by the annealing treatment of 0 ° C. × 20 seconds, the slope formed by the (0, −1, −1) _C plane of the p-type layer 52 is formed by using the ordinary lithography technique and the etching technique. Wiring layer 5 made of Au-Zn / Au on 52A
6 is formed, and at the same time, the contact portion 55 is formed on the mask layer 12.
And a p-type electrode 54 is formed on the p-type layer 52. The formation of the p-type electrode 54 may be omitted depending on the case.

Thus, the compound semiconductor element shown in FIG. 8C, which is composed of a lateral pin photodiode which is a highly sensitive photodetector having a large light absorption layer in the horizontal direction on the mask layer 12, is manufactured. You can

Example 4 The compound semiconductor device of Example 4 is composed of a vacuum transistor. A compound semiconductor device composed of the vacuum transistor of Example 4 is schematically shown in FIG.
FIG. 9A is a schematic partial plan view of the vacuum transistor, and FIG. 9B is a diagram when the vacuum transistor is cut along the line BB in FIG. 9A. It is a typical partial cross section figure. In FIG. 9A, the mask layer region is shaded.

The vacuum transistor of the fourth embodiment is, for example, G
a compound semiconductor substrate 10 made of aAs and having a (111) _S B plane, strip-shaped first, second, third and fourth mask layer regions 60, 61, 62 and 63, and an emitter section 6.
4, a base portion 65, and a collector portion 66.

The strip-shaped first, second, third and fourth mask layer regions 60, 61, 62 and 63 are made of, for example, SiO ₂ or SiN, and are formed of (11) of the compound semiconductor substrate 10.
1) It is formed on the _S B surface, the longitudinal direction thereof coincides with the [0, -1, 1] _S direction of the compound semiconductor substrate 10, and the width direction thereof is [2, -1,-) of the compound semiconductor substrate 10. 1] It coincides with the _S direction (see FIG. 9).

The emitter section 64 is made of a compound semiconductor crystal (for example, GaAs crystal) and has a first mask layer region 60.
And the second mask layer region 61 are exposed on the (111) _S B surface of the compound semiconductor substrate 10. Then, the shape when cut by a vertical plane parallel to the width direction of the first or second mask layer region is a parallelogram, and the upper side of the parallelogram is (−1, −) of the compound semiconductor crystal layer.
1, -1) Corresponds to the _C plane 64B. On the other hand, the hypotenuse corresponds to the (0, -1, -1) _C plane 64A and the (0,1,1) _C plane 64D of the compound semiconductor crystal layer (enlarged partial cross-sectional view of FIG. 9C). reference). In addition, the slope 64A
It corresponds to a slope composed of (0, -1, -1) _C plane.

The base portion 65 is also made of a compound semiconductor crystal (for example, GaAs crystal), and is exposed between the second mask layer region 61 and the third mask layer region 62, and the (111) _{SB of} the compound semiconductor substrate 10 is exposed. It is formed on the surface. The shape when cut by a vertical plane parallel to the width direction of the second or third mask layer region is a parallelogram, and the upper side of the parallelogram is (-1, -1 of the compound semiconductor crystal layer. ，
-1) Corresponds to the _C plane. On the other hand, the hypotenuse is the (0, -1, -1) _C plane 65A and (0,1,1) _{C of the} compound semiconductor crystal layer.
Equivalent to a face. That is, the slope 65A is (0, -1,-)
1) Corresponds to a slope composed of the _C plane.

The collector portion 66 is also made of a compound semiconductor crystal (for example, GaAs crystal) and has a third mask layer region 62.
And the fourth mask layer region 63 are exposed on the (111) _S B surface of the compound semiconductor substrate 10. Then, the shape when cut by a vertical plane parallel to the width direction of the third or fourth mask layer region is a parallelogram, and the upper side of the parallelogram is (−1, −) of the compound semiconductor crystal layer.
1, -1) Corresponds to the _C plane. On the other hand, the hypotenuse is the (0, -1, -1) _C plane 66A and (0, 1, -1) of the compound semiconductor crystal layer.
1) Corresponds to the _C side. That is, the slope 66A is (0,-
1, -1) Corresponds to a slope composed of the _C plane.

Under a vacuum atmosphere, a positive potential is applied to the base portion 65 with an appropriate voltage applied to the emitter portion 64. As a result, the electrons emitted from the edge portion 64C of the emitter portion 64 (see FIG. 9C) are transferred to the base portion 65C.
It reaches the collector section 66 by being controlled by the potential applied to the collector section 66. Therefore, the collector portion 66 to the emitter portion 64
The current flowing to can be controlled by the potential applied to the base portion 65.

The edge portion 64C of the emitter portion 64 is composed of a ridge where the (-1, -1, -1) _C plane 64B and the (0, 1, 1) plane 64D of the compound semiconductor crystal layer intersect. . Therefore, the edge portion 64C of the emitter portion 64 is accurately defined. Incidentally, the (0, 1, 1) plane 64D and the (0,
-1, -1) The angle formed by the inclined surface 64A composed of the _C plane and the surface of the compound semiconductor substrate 10 is about 35 degrees.

The angle between the slope 65A of the base portion 65 and the slope 66A of the collector portion 66 and the surface of the compound semiconductor substrate 10 is also about 35 degrees. Therefore, the distance between the first mask layer region 60 and the second mask layer region 61, the distance between the second mask layer region 61 and the third mask layer region 62, and the distance between the third mask layer region 62 and the fourth mask layer region 62. By accurately defining the distance between the mask layer regions 63, the distance between the emitter portion 64, the base portion 65 and the collector portion 66 can be controlled accurately and with good reproducibility.

Electrodes 67 are provided on the top surfaces of the emitter portion 64, the base portion 65 and the collector portion 66, respectively.
A wiring layer 68 is formed on each of the slopes 64A, 65A, 66A.
Is extended. Each of the wiring layers 68 is connected to the contact portion 69 formed in the mask layer region. In FIG. 9A, illustration of electrodes, wiring layers, and contact portions is omitted. In addition, in FIG. 9B, illustration of a part of the contact portions is omitted.

Hereinafter, a method of manufacturing the vacuum transistor of Example 4 will be described with reference to FIG. The emitter 6
4, the so-called selective epitaxial growth technique based on the MOCVD method is applied to the formation method of the base portion 65 and the collector portion 66, as in the first embodiment. Also, MOCVD
The supply amount of the raw material gas in the method is represented by the partial pressure in the MOCVD reactor. The total pressure inside the MOCVD reactor was 0.1 atm.

[Step-400] (Compound semiconductor substrate 1
Preparation of 0) First, on the (111) _S B plane of the compound semiconductor substrate 10 made of, for example, GaAs, SiO _{2 having} a thickness of about 0.1 μm is formed.
Alternatively, a mask layer made of SiN is deposited by the CVD method or the like. Next, the mask layer is selectively removed by using a normal photolithography technique and an etching technique to form strip-shaped first, second, third, and fourth mask layer regions 60, 61,
62 and 63 are formed. In these mask layer regions, the longitudinal direction coincides with the [0, -1, 1] _S direction of the compound semiconductor substrate 10 and the width direction thereof is [2, 2 of the compound semiconductor substrate 10.
-1, -1] It matches with the _S direction.

[Step-410] (Formation of Emitter Section 64, Base Section 65, and Collector Section 66) Next, the emitter section 64, the base section 65, and the collector section 66 made of a compound semiconductor crystal (for example, GaAs crystal).
Of the compound semiconductor substrate 1 exposed between the mask layer regions
Epitaxial growth is performed on the (111) _S B plane of 0 by the MOCVD method. The conditions of MOCVD are illustrated below. Substrate heating temperature: 800 ° C. Ga source gas: TMG (trimethylgallium) supply amount: 3 × 10 ⁻⁶ atm As source gas: arsine source gas partial pressure ratio: 200

Under such conditions, the compound semiconductor crystal (for example, GaAs crystal) is formed into (111) of the compound semiconductor substrate 10.
_{By the} selective epitaxial growth on the SB plane, the compound semiconductor grows only on the compound semiconductor substrate 10 and in a direction (or an oblique direction) perpendicular to the compound semiconductor substrate 10, and a crystal is grown on the mask layer region. Does not grow. Alternatively, even if the compound semiconductor grows on the mask layer region, the crystal grows only in the vicinity of the edge of the mask layer region. Therefore, so-called selective epitaxial growth can be achieved.

On the (111) _S B surface of the compound semiconductor substrate 10 exposed between the mask layer regions, the emitter section 64,
The base portion 65 and the collector portion 66 are formed by epitaxial growth by MOCVD. At this time, Ga
(0, -1, -1) _{C of} compound semiconductor crystal composed of As
The compound semiconductor crystal is epitaxially grown so that the planes become the inclined planes 64A, 65A, 66A and the (-1, -1, -1) _C plane becomes the top plane. As a result, when the emitter section 64, the base section 65, and the collector section 66 are cut along the vertical plane including the width direction of the mask layer region, the cross-sectional shape becomes a parallelogram.

[Step-420] After that, the emitter section 6
4. An electrode 67 is formed on the top surface of each of the base portion 65 and the collector portion 66. At the same time, each slope 64
A wiring layer 68 extending to A, 65A, 66A is formed. Further, a contact portion 69 electrically connected to each of the wiring layers 68 is formed on the mask layer region. The material forming the electrode 67, the wiring layer 68, and the contact layer 69 can be Au-Ge / Au, for example. In some cases, the formation of the electrodes 67 on the top surfaces of the emitter section 64, the base section 65, and the collector section 66 may be omitted. Electrode 67, wiring layer 68 and contact layer 6
Since the formation of 9 can be performed by using a usual vacuum vapor deposition method, a sputtering method, a photolithography technique, and an etching technique, detailed description thereof will be omitted.

Although the present invention has been described based on the preferred embodiments, the present invention is not limited to these embodiments. The various conditions, numerical values, and the like described in the embodiments are examples, and can be changed as appropriate. Also, the planar shape of the opening to be formed in the mask layer can be appropriately changed depending on the required crystal plane of the compound semiconductor crystal layer.

The n-type and p-type conductivity types of the compound semiconductor element may be reversed. In this case, the conductivity type of the compound semiconductor crystal layer on which the electrode is formed is n-type,
As materials for the electrodes, wiring layers and contact parts,
Au-Ge / Au (Au-Ge and Au) or the like may be used. Although the compound semiconductor substrate made of GaAs is exclusively used in the embodiments, a compound semiconductor element having a semiconductor laser structure can also be produced by using a compound semiconductor substrate made of InP. In this case, the active layer is made of GaInAs and the clad layer is made of AlGaInA.
It may be composed of s. When a compound semiconductor substrate having a semiconductor laser structure is manufactured using a compound semiconductor substrate made of GaAs, the active layer may be made of GaInP and the clad layer may be made of AlGaInP.
In growing the compound semiconductor crystal layer in the horizontal direction of the substrate, trimethylgallium was used as a Ga source gas,
Then, TDMAAs (tris-dimethylaminoarsenic) and tert-butylarsenic can be used as the As source gas.

In the embodiments, the present invention has been described by taking a semiconductor laser, a lateral pin photodiode and a vacuum transistor as an example of the compound semiconductor element, but the compound semiconductor element of the present invention is not limited to these elements. Any compound semiconductor device can be used as long as it is a compound semiconductor device that can be manufactured using the selective epitaxial growth technique. For example, the compound semiconductor device is
You may comprise from the photodetector which has the structure similar to the structure demonstrated in Example 1. Such photodetectors 70, 80
10 and 11 are schematic plan views of FIG.

In the photodetector 70 shown in FIG. 10,
The light enters the photodetector 70 from the (1, -1,0) plane 70A. The (1, -1,0) plane 70A is perpendicular to the compound semiconductor substrate 10. (1, -1,
0) When the surface 70A is projected onto the compound semiconductor substrate 10,
The angle formed by the compound semiconductor substrate 10 and the [0,1, -1] _S direction was 30 °. With such an angle, and when light enters the (1, -1,0) plane 70A of the photodetector 70 from a direction parallel to, for example, [0,1, -1] of the compound semiconductor substrate, (1 , -1,0) surface 70A can be effectively prevented from returning to the light emitting element or the like.

The photodetector 80 shown in FIG. 11 is substantially the same as the compound semiconductor device described in the first embodiment. Light enters the photodetector 80 from, for example, the (0, -1,1) plane 80A. In addition, (-1, 0, -1) plane and (-
The existence of the (-1, -1,0) plane does not have any adverse effect on the operation of the photodetector 80.

[2, -1,-of the compound semiconductor substrate 10]
1] The photodetectors 70 and 80 in the _S direction have (0,-
Slopes 72 and 82 formed of (1, -1) plane are formed. Then, the contact portions 78, 88 and the electrodes 74, 84
Are electrically connected to each other by wiring layers 76 and 86 extending on the slopes 72 and 82.

The sectional structures of the photodetectors 70 and 80 are substantially the same as the sectional structure of the compound semiconductor device of the first embodiment. Therefore, it can be manufactured by the same method as the compound semiconductor device described in the first embodiment. Photodetector 70,8
The light incident on 0 is absorbed by the active layer, and as a result, a current flows through the photodetectors 70 and 80. Light can be detected by detecting this current. The compound semiconductor device including such a photodetector has the same structure as the compound semiconductor device described in the first embodiment, and can be manufactured by the same method as the manufacturing method described in the first embodiment. Therefore,
Detailed description is omitted. Although the number of steps is increased, a photodetector having a rectangular planar shape is manufactured, and then vapor phase etching or the like is performed to detect a light incident surface having an appropriate angle with respect to the light emitted from the compound semiconductor element. It can also be formed into a container.

The compound semiconductor device of the present invention can be applied to an LED. In this case, the structure of the LED may be the same as the structure of the compound semiconductor device of Example 1 shown in FIG.

[0088]

According to the present invention, by selectively growing a compound semiconductor crystal, a slope mainly composed of {0, -1, -1} planes is formed in the compound semiconductor crystal layer, and a contact is formed. The portion and the electrode are electrically connected by a wiring layer extending on the slope. Therefore, the electrode and the contact portion formed on the compound semiconductor substrate can be electrically connected by the wiring layer having high reliability. In addition, depending on the form of the compound semiconductor device, a special device isolation technique is unnecessary in some cases. Furthermore, conventional MO
No special process is required in the CVD technique or the electrode forming technique, and the integration of the compound semiconductor element can be easily achieved.

In addition, a compound semiconductor element can be manufactured by one-time crystal growth, and in a compound semiconductor element having a semiconductor laser structure, a light emitting surface (for example, a laser resonance surface) can be obtained without the need of cleaving technology. ) Can be formed, so that the process can be simplified and a high quality light emitting surface can be formed.

[Brief description of drawings]

FIG. 1 is a schematic plan view of a compound semiconductor device of Example 1.

2 is a schematic partial cross-sectional view of the compound semiconductor device of Example 1. FIG.

FIG. 3 is a schematic view of a mask layer for explaining a method for manufacturing the compound semiconductor device of Example 1.

FIG. 4 is a schematic cross-sectional view of a compound semiconductor crystal layer or the like for explaining a method for manufacturing the compound semiconductor device of Example 1.

FIG. 5 is a schematic cross-sectional view of a compound semiconductor crystal layer or the like for explaining the formation state of crystal planes by the method for manufacturing the compound semiconductor device of Example 1.

FIG. 6 is a cross-sectional view schematically showing a separated state of the compound semiconductor element in Example 1.

FIG. 7 is a schematic plan view of a compound semiconductor device of Example 2.

FIG. 8 is a schematic partial cross-sectional view of a compound semiconductor device of Example 3.

FIG. 9 is a schematic plan view and a partial cross-sectional view of a compound semiconductor device of Example 4.

FIG. 10 is a schematic plan view of a compound semiconductor device of the present invention including a photodetector.

11 is a schematic plan view of a compound semiconductor device of the present invention including a photodetector having a form different from that of FIG.

FIG. 12 is a diagram for explaining a crystal growth method of a compound semiconductor crystal layer using a selective epitaxial growth technique.

FIG. 13 is a diagram for explaining a crystal growth method of a compound semiconductor crystal layer using a selective epitaxial growth technique.

FIG. 14 is a diagram for explaining a wiring layer forming process when a conventional wiring layer forming technique is applied to a compound semiconductor element using the selective epitaxial growth technique.

FIG. 15 is a diagram for explaining a wiring layer forming step when a conventional wiring layer forming technique different from that of FIG. 14 is applied to a compound semiconductor element using the selective epitaxial growth technique.

[Explanation of symbols]

10 Compound Semiconductor Substrate 12 Mask Layer 14 Window 20, 70, 80 Compound Semiconductor Crystal Layer 22B, 26B, 52A, 64A, 65A, 66A, 7
2,82 Slope 30 Buffer layer 32 First clad layer 34 Active layer 36 Second clad layer 38 Cap layer 40, 54, 67, 74, 84 Electrode 42, 56, 68, 76, 86 Wiring layer 44, 55, 68,78,88 Contact part

Claims (6)

[Claims] 1. A compound semiconductor substrate, a compound semiconductor crystal layer formed on a {111} B plane of the compound semiconductor substrate, and a contact portion provided on a mask layer formed on the compound semiconductor substrate. In the compound semiconductor device, the top surface of the compound semiconductor crystal layer is composed of {-1, -1, -1} planes, and electrodes are formed on the top surface. Has at least one slope, and the slope is mainly composed of {0, -1, -1} planes, and the contact portion and the electrode are electrically connected by a wiring layer extending on the slope. A compound semiconductor device characterized by being connected. 2. The compound semiconductor device according to claim 1, wherein the materials forming the electrodes, the wiring layer and the contact portion are Au—Zn and Au. 3. The compound semiconductor device according to claim 1, wherein the materials forming the electrodes, the wiring layer and the contact portion are Au—Ge and Au. 4. A step of: (a) forming a mask layer on the {111} B plane of the compound semiconductor substrate and then forming an opening in the mask layer; and (b) exposing the bottom of the opening. A compound semiconductor crystal is selectively grown on a {111} B plane of a compound semiconductor substrate, and a top surface composed of {-1, -1, -1} planes and mainly {0, -1, -1} planes. A step of forming a compound semiconductor crystal layer having at least a slanted surface composed of (c) an electrode is formed on the top surface, a contact portion is formed on the mask layer, and a contact portion and an electrode are also And a step of forming a wiring layer extending on the slope for electrical connection. 5. The compound according to claim 4, wherein the step of forming the electrode, the wiring layer and the contact portion includes the step of forming Au—Zn and Au by a vacuum deposition method or a sputtering method. Manufacturing method of semiconductor element. 6. The compound according to claim 4, wherein the step of forming the electrode, the wiring layer, and the contact portion includes the step of forming Au—Ge and Au by vacuum deposition or sputtering. Manufacturing method of semiconductor element.