JPS63229743A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS63229743A JPS63229743A JP62062386A JP6238687A JPS63229743A JP S63229743 A JPS63229743 A JP S63229743A JP 62062386 A JP62062386 A JP 62062386A JP 6238687 A JP6238687 A JP 6238687A JP S63229743 A JPS63229743 A JP S63229743A
- Authority
- JP
- Japan
- Prior art keywords
- film
- oxide film
- thickness
- trench
- nitride film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 23
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 22
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 15
- 239000003990 capacitor Substances 0.000 claims abstract description 14
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 6
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 6
- 239000010703 silicon Substances 0.000 claims abstract description 6
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 230000015556 catabolic process Effects 0.000 abstract description 9
- 150000004767 nitrides Chemical class 0.000 abstract description 7
- 230000003647 oxidation Effects 0.000 abstract description 7
- 238000007254 oxidation reaction Methods 0.000 abstract description 7
- 230000007774 longterm Effects 0.000 abstract description 6
- 230000001590 oxidative effect Effects 0.000 abstract description 5
- 238000009413 insulation Methods 0.000 abstract description 4
- 229910052681 coesite Inorganic materials 0.000 abstract 2
- 229910052906 cristobalite Inorganic materials 0.000 abstract 2
- 239000000377 silicon dioxide Substances 0.000 abstract 2
- 229910052682 stishovite Inorganic materials 0.000 abstract 2
- 229910052905 tridymite Inorganic materials 0.000 abstract 2
- 230000036962 time dependent Effects 0.000 abstract 1
- 238000005259 measurement Methods 0.000 description 5
- 238000000034 method Methods 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000001186 cumulative effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/37—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は、半導体装置、特に、トレンチキャパシタ（Ｃ
ＣＣ（Ｃｏｒｒｕｇａｔｅｄ ｃａｐａｃｉｔｏｒ ｃ
ｅｌｌ））における絶縁膜の構造に関するものである。Detailed Description of the Invention (Field of Industrial Application) The present invention relates to semiconductor devices, particularly trench capacitors (C
CC (corrugated capacitor c)
The present invention relates to the structure of an insulating film in ELL)).
（従来の技術）
従来、このような分野の技術としては、例えば、以下に
示すようなものがあった。(Prior Art) Conventionally, as technologies in this field, there have been, for example, the following.
第３図は係るトレンチＭＯＳキャパシタの断面図である
。FIG. 3 is a cross-sectional view of such a trench MOS capacitor.
この図において、ＭＯＳキャパシタは、Ｐ型シリコン基
板１上に形成されたトレンチ（間口は狭いが深い溝：
ｔｒｅｎｃｈ ） ２に沿って形成されたシリコン酸化
膜３、ＬＰＣＶＤ法によって堆積されたシリコン窒化膜
４、及びシリコン窒化膜４を酸化したシリコン酸化１ｌ
Ｉ５をゲート膜として多結晶シリコン電極６で挟む構造
を有している。なお、７はトレンチを埋める多結晶シリ
コン又はシリコン酸化膜、８は上部コーナ一部のエツジ
、９は下部コーナ一部のエツジである。In this figure, a MOS capacitor is formed in a trench (a narrow but deep trench) formed on a P-type silicon substrate 1.
a silicon oxide film 3 formed along the trench ) 2, a silicon nitride film 4 deposited by the LPCVD method, and a silicon oxide film 1l obtained by oxidizing the silicon nitride film 4.
It has a structure in which I5 is used as a gate film and sandwiched between polycrystalline silicon electrodes 6. Note that 7 is a polycrystalline silicon or silicon oxide film filling the trench, 8 is an edge of a portion of the upper corner, and 9 is an edge of a portion of the lower corner.
従来、この種の半導体装置は、主にＭＯ５型ダイナミッ
クランダムアクセスメモリ （ＤＲＡＭ）のメモリセル
部の容量として用いられてきた。ゲート膜は重要な絶縁
膜であるが、反応性イオンエツチング（ＲＩＥ ）によ
るトレンチ形成時のダメージ及び上部コーナ一部のエツ
ジ８、下部コーナ一部のエツジ９での電界集中やシリコ
ン酸化膜３の薄膜化のだめに、耐圧リーク電流の劣化が
発生する。これを防ぐため、高温（１１００℃以上）で
の酸化及び酸化膜の除去による各コーナ一部のエツジの
丸め処理（丸め酸化）及び上記したような絶縁膜の多層
膜化によって、耐圧、リーク電流等の初期特性の改善が
行われている。Conventionally, this type of semiconductor device has been mainly used as a capacitor of a memory cell portion of an MO5 type dynamic random access memory (DRAM). The gate film is an important insulating film, but it can be damaged by reactive ion etching (RIE) during trench formation, electric field concentration at edges 8 in the upper corner and edges 9 in the lower corner, and damage to the silicon oxide film 3. As the film becomes thinner, the withstand voltage leakage current deteriorates. In order to prevent this, the edges of some corners of each corner are rounded (rounding oxidation) by oxidation and removal of the oxide film at high temperatures (1100°C or higher), and the insulation film is made into a multilayer film as described above to reduce the breakdown voltage and leakage current. Improvements have been made to initial characteristics such as:
（発明が解決しようとする問題点）
しかしながら、以上述べた従来の方法では、丸め酸化の
場合、高温処理による不純物の再分布が行われ、又、多
層膜化しても経時絶縁破壊（ＴＯＤＢ（ＴｉＩＩｅ
Ｄｅｐｅｎｄｅｎｔ Ｄｉｅｌｅｃｔｒｉｃ Ｂｒ
ｅａｋｄｏｗｎ） ） 測定による長期信頼性が劣
化するという問題があった。(Problems to be Solved by the Invention) However, in the conventional method described above, in the case of rounding oxidation, impurities are redistributed due to high temperature treatment, and even in the case of multilayer film formation, dielectric breakdown over time (TODB (TiIIe
Dependent Dielectric Br
eakdown) ) There was a problem in that the long-term reliability of measurements deteriorated.
この点について第４図を参照しながら説明する。This point will be explained with reference to FIG.
この図は、定電圧における経時絶縁破壊特性を示す図で
あり、トレンチ数１ｏｏｏｏ個、キャパシタ面積１ ｘ
ｍ” 、５ｉ（ｈ（１５０人） ／５ｉＮ（１５０人
）／５ｉＯｚ（２０人）の条件で、横軸は印加電界（Ｍ
Ｖ／（Ｊ）、縦軸は経時絶縁破壊の累積不良率が５０％
に至る時間（秒）を示しており、この図から明らかなよ
うに、プレーナーキャパシタａに比べて、トレンチキャ
パシタｂの場合は約２桁寿命が短いということがわかる
。This figure shows the dielectric breakdown characteristics over time at constant voltage, and the number of trenches is 1oooo, and the capacitor area is 1 x
m'', 5i (h (150 people) / 5iN (150 people) / 5iOz (20 people), and the horizontal axis is the applied electric field (M
V/(J), the vertical axis is the cumulative failure rate of dielectric breakdown over time of 50%
As is clear from this figure, the lifespan of trench capacitor b is about two orders of magnitude shorter than that of planar capacitor a.
本発明は、上記問題点を除去し、簡単な構成で、ＴＤＤ
Ｂ測定における長期信頼性を向上し得る半導体装置を提
供することを目的とする。The present invention eliminates the above problems, has a simple configuration, and provides TDD
An object of the present invention is to provide a semiconductor device that can improve long-term reliability in B measurements.
（問題点を解決するための手段）
本発明は、上記問題点を解決するために、トレンチＭＯ
Ｓキャパシタにおいて、トレンチを形成した後、熱酸化
膜（Ｂ−３ｉＯ□） 、ＣＶＤ窒化膜及び窒化膜の酸化
による酸化膜の３層絶縁膜の形成において、熱酸化膜（
Ｂ−Ｓｉ（ｈ）とＣＶＤ窒化膜（Ｓｉ３Ｎｍ ）との膜
厚比（Ｔｈｉｃｋｎｅｓｓ ＳｉＪ＊／Ｔｈ１ｃｋｎｅ
ｓｓ ５ｉＯｚ）を１．５以上にするように構成したも
のである。(Means for Solving the Problems) In order to solve the above problems, the present invention provides trench MO
In the S capacitor, after forming a trench, a thermal oxide film (B-3iO□), a CVD nitride film, and an oxide film formed by oxidizing the nitride film are formed to form a three-layer insulating film.
Film thickness ratio of B-Si (h) and CVD nitride film (Si3Nm) (Thickness SiJ*/Th1ckne
ss 5iOz) of 1.5 or more.
（作用）
本発明によれば、上記のように構成したので、従来のよ
うに、高温（１１００℃以上）によるトレンチのコーナ
一部の丸め酸化を行う必要がなく、絶縁膜の構成比を変
えるだけでＴＤＤＢ測定による長期信頼性の向上を図る
ことができる。(Function) According to the present invention, with the above structure, there is no need to round off and oxidize a part of the corner of the trench at high temperature (1100° C. or higher) as in the conventional method, and the composition ratio of the insulating film can be changed. It is possible to improve the long-term reliability by TDDB measurement only by this method.
（実施例）
以下、本発明の実施例について図面を参照しながら詳細
に説明する。(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.
第１図は本発明の実施例を示す半導体装置の製造工程断
面図である。FIG. 1 is a cross-sectional view of the manufacturing process of a semiconductor device showing an embodiment of the present invention.
まず、第１図（ａ）に示されるように、Ｐ型シリコン基
板１１上に熱酸化法によりシリコン酸化膜１２を２００
〜５００人程度成長させ、その上に、ＬＰＣＶＤ法によ
りシリコン窒化膜１３を１００〜４００人成長させる。First, as shown in FIG. 1(a), a silicon oxide film 12 with a thickness of 200 mm is deposited on a P-type silicon substrate 11 by thermal oxidation.
The silicon nitride film 13 is grown on the silicon nitride film 13 by 100 to 400 people using the LPCVD method.
更に、その上に、ＣＶＤ法によりシリコン酸化膜１４を
３０００〜１００００ 大成長する。この後、ホトレジ
スト１５を塗布し、ホトリソグラフィーを行う。Furthermore, a silicon oxide film 14 with a thickness of 3,000 to 10,000 times is grown thereon by the CVD method. After this, a photoresist 15 is applied and photolithography is performed.
次に、第１図（ｂ）に示されるように、ＲＴＥ法により
、ホトレジスト１５をマスクとして、シリコン酸化膜１
４／シリコン窒化膜１３／シリコン酸化膜１２をエツチ
ングし、ホトレジストを除去する。Next, as shown in FIG. 1(b), using the photoresist 15 as a mask, the silicon oxide film 1 is
4/Etch the silicon nitride film 13/silicon oxide film 12 and remove the photoresist.
この後、第１図（ｃ）に示されるように、ＲＩＢ法によ
り、ＣＣ２４等のガスを用いてシリコン基板１１をエツ
チングしてエツチングマスクのシリコン酸化膜１４、窒
化膜１３、酸化膜１２を除去する。Thereafter, as shown in FIG. 1(c), the silicon substrate 11 is etched by the RIB method using a gas such as CC24 to remove the silicon oxide film 14, nitride film 13, and oxide film 12 of the etching mask. do.
この後、熱酸化法（９００〜ｔｏｏｏ℃）により、シリ
コン酸化膜を５００〜１０００人形成し、エツチングに
よるダメージを除去し、この酸化膜を除去する。Thereafter, 500 to 1,000 silicon oxide films are formed by a thermal oxidation method (900 DEG to 1,000 DEG C.), damage caused by etching is removed, and this oxide film is removed.
次に、９００〜９５０℃の熱酸化によりシリコン酸化膜
（Ｂ−５ｉＯｚ） １６、その上ニＬＰＣＶＤ法により
シリコン酸化膜（ＳｉｓＬ ） １７、そのシリコン窒
化膜を９００〜９５０℃で酸化することにより、シリコ
ン酸化膜１８を形成する。この時、Ｂ−ＳｉＯｚと５ｉ
Ｊｓの膜厚比が重要である。Next, a silicon oxide film (B-5iOz) 16 is formed by thermal oxidation at 900 to 950°C, a silicon oxide film (SisL) 17 is formed by LPCVD, and the silicon nitride film is oxidized at 900 to 950°C. A silicon oxide film 18 is formed. At this time, B-SiOz and 5i
The film thickness ratio of Js is important.
即ち、その膜厚比Ｔｈ１ｃｋｎｅｓｓ ５ｉｓＮｓ／Ｔ
ｈ１ｃｋｎｅｓｓＢ−５ｉ（ｈ）が１．５以上になるよ
うに構成する０例えば、シリコン酸化膜（Ｂ−３ｉＯ□
）の膜厚が９０人に対してシリコン窒化膜（ｓｔ３Ｎ４
）の膜厚を１５０人にする。That is, the film thickness ratio Th1ckness 5isNs/T
For example, a silicon oxide film (B-3iO□
) film thickness for 90 people, silicon nitride film (st3N4
) to 150 people.
また、シリコン窒化膜の酸化によって形成されるシリコ
ン酸化膜の膜厚を２０人にする。Further, the thickness of the silicon oxide film formed by oxidizing the silicon nitride film is set to 20.
その後、多結晶シリコン電極１９を形成して、第１図（
ｄ）に示されるように、本発明に係る半導体装置（トレ
ンチＭＯＳキャパシタ）を得ることができる。Thereafter, a polycrystalline silicon electrode 19 is formed, and as shown in FIG.
As shown in d), a semiconductor device (trench MOS capacitor) according to the present invention can be obtained.
第２図は、全体の絶縁膜の膜厚を誘電率を考慮して酸化
ｌＩｕ換算で１８０〜２２０人にした時の定電流でのＴ
ＤＤＢ測定による経時絶縁破壊特性図である。Figure 2 shows the T at constant current when the total insulating film thickness is 180 to 220 in terms of lIu oxide considering the dielectric constant.
It is a diagram of dielectric breakdown characteristics over time obtained by DDB measurement.
なお、この時の条件として、トレンチ数１００００個、
キャパシタ面積Ｌ ｍｍ” 、５ Ｘ １０−’ Ａ
／ ｍｕ”の定電流で、横軸はシリコン窒化膜（Ｓｉｚ
Ｎａ）厚／シリコン酸化膜（Ｂ−５ｉＯ７）厚、縦軸は
経時絶縁破壊の累積不良率が５０％に至る時間（秒）を
示している。The conditions at this time are 10,000 trenches,
Capacitor area L mm", 5 x 10-' A
/ mu” constant current, and the horizontal axis is the silicon nitride film (Siz
Na) thickness/silicon oxide film (B-5iO7) thickness, the vertical axis indicates the time (seconds) for the cumulative failure rate of dielectric breakdown over time to reach 50%.
この図によれば、５ｉＪａ ／Ｂ−５ｉＯ１の膜厚比が
、１．５以上になると、急激に蓄積不良率の５０％に至
る時間、つまり、寿命が長くなり、長期信頼性が改善さ
れることが明らかである。According to this figure, when the film thickness ratio of 5iJa/B-5iO1 becomes 1.5 or more, the time to reach 50% of the accumulated failure rate, that is, the life span, increases and the long-term reliability improves. That is clear.
なお、本発明は上記実施例に限定されるものではなく、
本発明の趣旨に基づいて種々の変形が可能であり、これ
らを本発明の範囲から排除するものではない。Note that the present invention is not limited to the above embodiments,
Various modifications are possible based on the spirit of the present invention, and these are not excluded from the scope of the present invention.
（発明の効果）
以上、詳細に説明したように、本発明によれば、従来の
ように、高温（１１００℃以上）によるトレンチのコー
ナ一部の丸め酸化を行うことなく、絶縁膜の構成比を変
えるだけでＴＤ［ｌＢ測測定よる長３ＩＪｌ信頼性を大
幅に改善することができる。(Effects of the Invention) As described above in detail, according to the present invention, the composition ratio of the insulating film can be improved without rounding off and oxidizing a part of the corner of the trench at high temperature (1100° C. or higher) as in the conventional method. It is possible to greatly improve the reliability of long 3IJl measured by TD [lB measurement] by simply changing .
第１図は本発明の実施例を示す半導体装置の製造工程断
面図、第２図は定電流における半導体装置の経時絶縁破
壊特性図、第３図は従来のトレンチＭＯＳキャパシタの
断面図、第４図はその定電圧における経時絶縁破壊特性
図である。
１１・・・Ｐ型シリコン基板、１２．１４．１６．１８
・・・シリコン酸化膜、１３．１７・・・シリコン窒化
膜、１５・・・ホトレジスト、１９・・・多結晶シリコ
ン電極。FIG. 1 is a cross-sectional view of the manufacturing process of a semiconductor device showing an embodiment of the present invention, FIG. 2 is a diagram of dielectric breakdown characteristics over time of the semiconductor device at constant current, FIG. 3 is a cross-sectional view of a conventional trench MOS capacitor, and FIG. The figure shows the dielectric breakdown characteristics over time at constant voltage. 11...P-type silicon substrate, 12.14.16.18
... silicon oxide film, 13.17 ... silicon nitride film, 15 ... photoresist, 19 ... polycrystalline silicon electrode.
Claims (1)
リコン酸化膜、シリコン窒化膜、第２のシリコン酸化膜
を順次形成し、前記溝の側壁を含む領域に設けたキャパ
シタ部と、スイッチ用素子部とを有する半導体装置にお
いて、 前記第１のシリコン酸化膜の膜厚に対して前記シリコン
窒化膜の膜厚が１．５倍以上になるように構成すること
を特徴とする半導体装置。[Scope of Claims] A first silicon oxide film, a silicon nitride film, and a second silicon oxide film are sequentially formed as insulating films in a trench formed in a silicon substrate, and a capacitor is provided in a region including the sidewalls of the trench. A semiconductor device having a switching element section and a switching element section, characterized in that the silicon nitride film has a thickness 1.5 times or more greater than the thickness of the first silicon oxide film. semiconductor devices.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62062386A JPS63229743A (en) | 1987-03-19 | 1987-03-19 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62062386A JPS63229743A (en) | 1987-03-19 | 1987-03-19 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63229743A true JPS63229743A (en) | 1988-09-26 |
Family
ID=13198632
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62062386A Pending JPS63229743A (en) | 1987-03-19 | 1987-03-19 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63229743A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02263461A (en) * | 1989-04-03 | 1990-10-26 | Nec Yamaguchi Ltd | Manufacture of semiconductor integrated circuit device |
| US6469345B2 (en) | 2000-01-14 | 2002-10-22 | Denso Corporation | Semiconductor device and method for manufacturing the same |
| US6521538B2 (en) | 2000-02-28 | 2003-02-18 | Denso Corporation | Method of forming a trench with a rounded bottom in a semiconductor device |
| US6864532B2 (en) | 2000-01-14 | 2005-03-08 | Denso Corporation | Semiconductor device and method for manufacturing the same |
-
1987
- 1987-03-19 JP JP62062386A patent/JPS63229743A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02263461A (en) * | 1989-04-03 | 1990-10-26 | Nec Yamaguchi Ltd | Manufacture of semiconductor integrated circuit device |
| US6469345B2 (en) | 2000-01-14 | 2002-10-22 | Denso Corporation | Semiconductor device and method for manufacturing the same |
| US6864532B2 (en) | 2000-01-14 | 2005-03-08 | Denso Corporation | Semiconductor device and method for manufacturing the same |
| US7354829B2 (en) | 2000-01-14 | 2008-04-08 | Denso Corporation | Trench-gate transistor with ono gate dielectric and fabrication process therefor |
| US6521538B2 (en) | 2000-02-28 | 2003-02-18 | Denso Corporation | Method of forming a trench with a rounded bottom in a semiconductor device |
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