JPS6036111B2 - Manufacturing method of semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and specifically relates to a method of manufacturing a double electrode such as a double gate nonvolatile memory.

Double gated non-volatile memory in general, especially Snecked
GateAvalanche lnjenCtiont
ypeM○S transistor memory (hereinafter referred to as SAMOS)
Abbreviated as transistor.

), as shown in FIGS. 1A, B, and C, a P-type source region 2 and a P-type drain region 3 are formed in an N-type semiconductor substrate 1 by openings (hereinafter referred to as active regions) in a field oxide film 4. )
5 with a predetermined interval, and between the source region 2 and drain region 3, the first and second regions have a thickness of about 1000A.
Insulating films 6 and 8 are formed, and a floating gate 7 made of polycrystalline silicon is formed between them. On the upper surface of the second insulating film 8, a control gate 9 overlapping the floating gate 7 is formed of, for example, polycrystalline silicon. In addition, source electrodes 1 are provided in the source region 2 and drain region 3, respectively.
0, the drain electrode 11 is made of aluminum. In particular, the gate electrode structure of these SAMOS transistors is formed by a process as shown in FIG. That is, as shown in A, on the removed portion 5 of the field oxide film 4 of the N-type semiconductor substrate 1, a first insulating film 6 to be used as a gate insulating film is thermally oxidized to a thickness of about 1000 Å. A polycrystalline silicon film 7 is formed on the upper surface by chemical vapor deposition (Chemical Vapor Deposition).
n me ratio od: Hereinafter abbreviated as CVD method. ) and then photo-etched into a floating gate section of the desired shape. After the formation of the floating gates 7 is completed, as shown in FIG. It is formed on the surface of the substrate with a certain thickness. Next, as shown in C, the control gate 9 and the polycrystalline silicon layer are
The control gates 9 are formed over the entire surface of the device by the VD method, and the control gates 9 to be formed are as described above. - Photo-etching is performed so as to overlap the ting gate 7 to divide it into a predetermined shape. In this way, the double gate electrode structure of the SAMOS transistor is largely completed. However, the SAM as shown in Fig. 1 manufactured by such a manufacturing method
In the OS transistor, when a voltage is applied to the control electrode 9, local electric field concentration occurs particularly at the end G of the floating gate 7 that reaches the field oxide film 4, that is, a portion called a fringe. This was recognized.

The fact that a local electric field concentration occurs in a part of the floating gate 7 in this way means that the electrons charged on the floating gate 7 escape from the electric field concentration part to the control gate 9. Therefore, a problem arises in that the memory retention characteristics of the SAMOS transistor are deteriorated. Furthermore, assuming that the relationship between the floating gate 7 and the control gate 9 is replaced by a first wiring electrode and a second wiring electrode, the withstand voltage between these wirings becomes very low in the electric field concentration part G.
Leakage current is likely to occur, and the characteristics of the device are greatly deteriorated. By the way, if we consider the reason why these electric field concentrations occur, that is, the reason why electric field concentration occurs at the SAMOS transistor gate part, as is clear from the partially enlarged view of FIG. 3, the control electrode 9 is
A second gate is placed on the floating gate 7 divided into a predetermined shape.
An insulating film 8 is formed and a control layer is formed thereon. Since the control gate 9 is formed with a step S corresponding to the thickness b of the floating gate 7, the control gate 9 is provided with a step S corresponding to the thickness b of the floating gate 7. This is because the floating gate 9 forms an overhang form in close contact with the floating gate 7. Furthermore, these stages S are determined by the relationship c》d between the thickness C when the second insulating film 8 is formed by thermally oxidizing the floating gate layer 7 and the thickness d of the oxide film grown on the field oxide film 4. Therefore, the precise step S is d+(c-d), and the actual overhang is significant. When a voltage is applied to the control gate 9 overhanging the floating gate 7 in this manner, electric field concentration as described above occurs, which deteriorates the memory characteristics. Furthermore, if the second insulating film 8 formed between the floating gate 7 and the control gate 9 is unstable, dielectric breakdown may occur between the floating gate 7 and the control gate 9. As a result, the SAMOS transistor has completely lost its memory function. Moreover, the reason for the electric field concentration in the two-layer wiring electrode structure is clear from FIGS. 4A and 4B.

That is, the second insulating film 14 is formed on the first electrode wiring 13 running on the first insulating film 12 on the semiconductor substrate 1,
When the second electrode wiring 15 runs so as to cross the first electrode wiring 13, a step S is generated between the first electrode wiring 13 and the second electric distribution line 15, and the second electrode wiring 15 crosses the first electrode wiring 13. The second electrode wiring 15 takes the form of an overhang with respect to the first electrode wiring. Therefore, it is recognized that when a potential difference occurs between the first wiring 13 and the second wiring 15, electric field concentration occurs particularly at the end G of the intersection of the first electrode wiring 13 and the second electrode wiring. It was done. Normally, since the voltage used is small, the degree of electric field concentration is extremely small, so the leakage current is also very small, so this was not a big problem, but the first electrode wiring 13
If a larger potential difference is generated between the second electrode wirings 15 for some reason, the electric field becomes large, and the leakage current in the electric field concentration portion G has a negative effect on the device. Further, when the potential between the first and second electrode wirings 13 and 15 reached a point where the insulation between the electrode wirings was broken down, the wirings were short-circuited and the devices became unusable. Therefore, the present invention relates to a method for manufacturing a semiconductor device that eliminates the above-mentioned drawbacks, and its purpose is to eliminate the local electric field generated between the floating gate fringe portion and the control gate of a SAMOS transistor, for example. The present invention provides a method for manufacturing a semiconductor device having a structure that prevents concentration.

In addition, in a semiconductor device having a two-layer electrode wiring structure,
The present invention provides a method for manufacturing a semiconductor device that can completely prevent electric fields from concentrating on the lower electrode edge portion of a wiring cross section. According to the present invention, a first insulating film is formed on the upper surface of the semiconductor substrate, and a first electrode film is formed on the upper surface of the first insulating film so that the entire thickness thereof becomes an oxide film by thermal oxidation. a step of forming a second insulating film on the upper surface of the first electrode film; a step of forming an oxidation-resistant insulating film in a predetermined shape on the upper surface of the second insulating film; etching the second insulating film using the oxidation-resistant insulating film as a mask to expose the first electrode surface; and etching the exposed surface of the first electrode using the oxidation-resistant insulating film as a mask. a step of thermally oxidizing the entire film thickness in the direction to form a thermally oxidized film continuous to the second insulating film; a step of removing the oxidation-resistant insulating film; and a step of removing the oxidation-resistant insulating film; and forming a second electrode layer continuous on the upper surface of the thermal oxide film. In order to better understand the purpose and structure of the present invention,
An embodiment of the present invention will be described using FIGS. 5A and 5B and FIG. 6. 5 and 6, the same members as those in FIG. 1 are given the same reference numerals for ease of explanation.

Figure 5A. The completed device according to the present invention shown in FIG. A first electrode film layer (floating gate) 7 made of a polycrystalline silicon film partitioned into a predetermined shape and formed on top of the floating gate is formed for the purpose of completely insulating the first electrode film layer 7 from the outside. a second insulating film 8 on the top surface of the first electrode film layer 7 and a thermal oxide film 1 on the side surface of the first electrode layer 7;
7, and a second electrode film (control gate) 9 formed continuously on the upper surface of the second insulating film 8 and the thermal oxide film 17.

What is particularly noteworthy about these devices is that the thermal oxide film 17 is formed to cover the side surface of the first electrode film layer 7.
It is in. That is, forming the thermal oxide film 17 on the side surface of the first electrode film layer 7 means that the second electrode film layer 9 to be formed later
In order to prevent breakage of the first electrode film layer end G
This is also very good in terms of preventing the second electrode film layer from forming an overhung pattern. In particular, those structures that do not form an overhang form are the first
The electric field is no longer forced locally in the electrode film layer 7, for example, electric field concentration at the end G of the first electrode film layer no longer occurs, and electrons are locally forced from the first electrode film layer 7. There are no more leakage problems. It goes without saying that the same effect can be obtained even if the first electrode film layer 7 and the second electrode film layer 9 are in the form of electrode wiring layers. Next, an example of a method for manufacturing these SAMOS transistors will be explained in detail with reference to FIGS. 6A to 6G.

To form a SAMOS transistor, first, as shown in A, a field oxide film 4 is formed by partially re-burying an N-type semiconductor substrate 1 and opening an active region. Next, a first insulating film 6 to be used as a gate insulating film is formed on the surface of the base in the active region. Next, on the surface of the substrate 1 on which these are formed, a first electrode film layer 7 of about 0.2 microns is formed, which is a polycrystalline silicon film whose film thickness in the thickness direction easily becomes an oxide film due to heat. Make it conductive. Next, on the substrate 1 on which the first electrode films 7 are formed, as shown in B, a second insulating film 8 made of a silicon dioxide film is formed for the purpose of insulating the first electrode films 7 from the outside. do. Next, as shown in C, an oxidation-resistant insulating film 16 is formed on the upper surface of the second insulating film 7 using, for example, a silicon nitride film (Si3N4), and then as shown in D, The film 16 is formed using Freon gas (CF4) plasma etching or the like so as to have a desired floating gate mask structure.

Next, using the silicon nitride film 16 as a mask, the second insulating oxide film 8 is removed using a hydrofluoric acid-based etching solution to expose the first electrode film layer 7. Next, by leaving these substrates 1 in an oxidizing atmosphere, the source/drain regions (not shown) and the polycrystalline silicon film 7 formed on the field oxide film 4 are covered with silicon nitride as shown in E. Membrane 1
6 as a mask, oxidize everything in the thickness direction, and then
The oxide film 17 is continuous with the insulating film 8. Then, the first electrode film layer 7 is completely insulated from the outside. Next, as shown in F, the silicon nitride film 16 is removed using phosphoric acid or the like, and then, as shown in G, the second electrode film 9 is removed as a control electrode of the SAMOS transistor, and the first electrode film 9 is removed as shown in G. It is continuously formed on the second insulating film 8 and the thermal oxide film 17 so as to overlap the layer (floating gate) 7. Of course, these second electrode films 9 may be polycrystalline silicon films, which are treated to become P-type or N-type conductors. As described above, according to such a manufacturing method, it is possible to provide a transistor that can prevent electric field concentration occurring in the SAMOS transistor, floating gate, and fringe portion. In addition, especially in Figure 5, SAMO
Except for the S transistor, I would like to state that it was manufactured by modifying the manufacturing method shown in Figure 6, as its structure is different.
That is, outside the SAMOS transistors shown in FIGS. 5A and 5B, during the manufacturing process shown in FIG. , the thermal oxide film 17 can be formed only on the upper surface of the field oxide film 4. This has the effect that electrodes can be easily taken out from the source region 2 and drain region 3 because the oxide films on the surfaces of the source region 2 and drain region 3 are thin. Also, these SAM
Since it is clear that the two-layer electrode configuration method for the OS transistor exhibits the same effect even when replaced with multilayer wiring, the explanation will be omitted.

Hereinafter, according to the present invention, the conventional method will be explained.

The floating gate, fringe, and electric field concentration caused by the control gate overhang that had occurred between the controlling gate and the control gate could be completely prevented because an insulating film was interposed in the electric field concentration area. That is, the overhang of the control gate that causes electric field concentration is eliminated by forming an oxidation-resistant insulating film on the floating gate that causes the overhang, and using this as a mask to oxidize the other parts. A thermal oxide film is formed around the floating gate to eliminate overhang. Furthermore, if these thermal oxide films are formed by thermal oxidation of a polycrystalline silicon film as shown in FIGS. 6D and E, a relatively thick thermal oxide film can be formed in a short time, making the effects of the present invention very advantageous. Therefore, the control gate underhangs in the thermal oxide film portion. Therefore, electric field concentration does not occur at all in the floating gate fringe portion, and as a matter of course, disconnections in the wiring can be drastically reduced. Furthermore, since the field oxide film is a field oxide film with a thermal oxide film added thereto, problems such as parasitic MOS in the field portion can be alleviated at the same time. As described above, it has been possible to provide a method for manufacturing a semiconductor device that exhibits various effects.

It goes without saying that the present invention can be modified not only to the embodiments presented here, but within the scope of the "claims."

For example, the second electrode layer of the SAMOS transistor may be a metal wiring, and in particular, the source/drain formation process may be performed before or after formation.

[Brief explanation of the drawing]

FIG. 1A is a plan view of a conventional SAMOS transistor,
B is a cross-sectional view of the SAMOS transistor in FIG. 1A taken along the line 1-1, C is a cross-sectional view of the top view of FIG. 1A taken along the row 0' line, and FIG. ,B,C are
Figure 1 is a schematic manufacturing process diagram of the SAMOS transistor shown in A, B, and C, Figure 3 is an enlarged view of the main part of Figure 1B, and Figure 4A
is a plan view of a known two-layer cross wiring, B is a cross-sectional view of the two-layer cross wiring shown in FIG. 4A taken along the line m-m', and FIG. Completed SA
A plan view of a MOS transistor, B is the SAMO of FIG. 5A.
A cross-sectional view of the S transistor taken along the line W-W',
6A to 6G are manufacturing process diagrams showing another embodiment of the present invention. 1... Semiconductor substrate, 2... Source region, 3
...Drain region, 4...Field insulating film, 5...Active region, 6...First insulating film, 7...First electrode film layer (floating gate), 8... second insulating film, 9...
...Second electrode film (control gate), 10...
... Source electrode, 11 ... Drain electrode, 1
7...Thermal oxide film. Figure 4 Figure 1 Figure 2 Figure 3 Figure 5 Figure 6

Claims (1)

[Claims] 1 forming a first insulating film on the upper surface of the semiconductor substrate;
forming a first electrode film layer on the top surface of the first insulating film, in which the entire film in the thickness direction becomes an oxide film by thermal oxidation; and forming a second insulating film on the top surface of the first electrode film layer. a step of forming;
forming an oxidation-resistant insulating film in a predetermined shape on the upper surface of the second insulating film; and etching the second insulating film using the oxidation-resistant insulating film as a mask to form a surface of the first electrode layer. exposing the first layer using the oxidation-resistant insulating film as a mask;
a step of thermally oxidizing the entire exposed surface of the electrode layer in the thickness direction to form a thermally oxidized film continuous to the second insulating film; and a step of removing the oxidation-resistant insulating film. and a second insulating film that is continuous with the second insulating film and the top surface of the thermal oxide film.
1. A method for manufacturing a semiconductor device, comprising the steps of: forming an electrode film.