JPS63177546A - Semiconductor device - Google Patents

Abstract

PURPOSE:To avoid problems on current leakage and breakdown strength deterioration and the like, by forming a groove with sidewalls which are perpendicular to a prescribed main surface and parallel or perpendicular to an orientation flat surface and forming a semiconductor element inside this groove. CONSTITUTION:A field oxidizing film 24 is formed selectively on a surface of a P type silicon wafer 21 which has a (100) crystal face as its main surface and has an orientation flat 22 formed on this (100). A groove 23 is formed in an element region. Next, a PSG film 25 is formed and piled on the whole surface, and heat diffusion of phosphorus is performed in the silicon substrate 21 so as to form a N<+> type impurity region 26. Successively, the PSG film 25 is peeled, and a heat oxidation film 27, polycrystalline silicon layers 28 and 29 are formed and piled thereon. The N<+> type impurity region 26 and the polycrystalline silicon layer 28 are respectively used as electrodes so as to form a capacitive element with the heat oxidation film 27 serving as a dielectric. Since all sidewalls of the groove 23 have (100) crystal faces, the heat oxidation film 27 can be formed with a uniform thickness.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a trench-type method in which a groove is formed in the main surface of a semiconductor substrate, and a semiconductor element or an element isolation region is formed in the groove. Related to semiconductor devices.

(Prior Art) Conventionally, in this type of semiconductor device, a silicon wafer is used in which the (100) plane is the main surface and the 110) plane is the orientation flat, and the plane parallel or perpendicular to the orientation flat is used as the side wall. After forming a groove and performing heat treatment to form an oxide film, semiconductor elements such as a MOS transistor, a capacitor element, and a high resistance element, or an element isolation region are formed in the groove. The reason why a plane parallel or perpendicular to the orientation flat is used is that it is easy to increase the degree of integration in terms of pattern layout, and it is easy to input coordinates by a computer (digitizer).

However, in the manufacturing method described above, although pattern layout and coordinate input processing by a computer are easy, the exposed surface of the trench used to form the semiconductor element and element isolation region is ), while the sidewall perpendicular to this bottom has a crystal plane of (1
10), there were the following problems.

The first problem is due to the fact that there are more fixed charges generated on the (110) plane than on the (100) plane at the interface between silicon and insulation II (for example, silicon oxide film). The 0MO8 structure shown in FIG. 2(a) will be explained as follows.

In FIG. 2(a), 1 is an N-type silicon substrate, 2 is a P-type well region, 3 is an element isolation region (silicon oxide film) formed in the trench, 4 is an N-channel type MoS transistor, Reference numeral 5 indicates a P-channel type MOS transistor. However, in this structure, a large amount of fixed charges are generated at the interface between the silicon oxide film 3 and the P well region 2, as shown in FIG. 2(b). As a result, an inversion layer due to accumulation of electrons is likely to be formed in the P-well region 2, as shown by the dashed line in the figure. For this reason, a leakage current shown by an arrow in the figure flows through the inversion layer, and this leakage current becomes a trigger, causing latch-up.

Note that even in the case of a normal (single channel type) MO8 type semiconductor device using a P-type silicon substrate, a similar current can be achieved if element isolation is performed using a silicon oxide film formed in the trench as described above. This will cause a leak.

The second problem is caused by the fact that when thermally oxidizing the surface of a silicon substrate, the oxidation rate is faster on the (110) plane than on the (100) plane. This problem can be explained for the passenger car element (trench type capacitor) shown in FIG. 3 (a) as follows. FIG. mold silicon substrate,
12 is a field oxide film, 13 is a silicon oxide film, 14
15 is an N+ type diffusion layer that is the other electrode of the capacitor; 16 is an N-channel MOS transistor for transfer. When forming a memory cell having such a trench type capacitor, since the oxidation rate is different between the (100) plane and the (110) plane as described above, the trench type capacitor is The silicon oxide film (thermal oxide film) 13 covering the inner surface becomes thinner at the bottom and thicker at the vertical sidewalls, resulting in non-uniform film thickness. As a result, a problem arises in that the withstand voltage decreases at the portion X marked with a circle in the figure.

Incidentally, neither the first nor the second problem has been considered a problem in the past. This is because the above-mentioned problem itself has only recently been recognized as the integration has progressed further. In addition, the advantage of higher integration through the use of grooves was significantly greater, and as mentioned above, convenience in mask creation was a major premise, which was a major reason why little attention was paid to the above problem. be.

(Problems to be Solved by the Invention) As described above, conventional trench type semiconductor devices have the disadvantage that problems such as current leakage and reduction in breakdown voltage occur due to the difference in crystal plane between the bottom and sidewalls of the trench. was there.

This invention was made in view of the above-mentioned circumstances, and its purpose is to utilize grooves having sidewalls perpendicular to the main surface of a silicon substrate for forming semiconductor elements, isolating elements, etc. To provide a trench type semiconductor device which aims to achieve high integration by avoiding problems caused by different crystal planes between the bottom and sidewalls of the trench, such as current leakage and breakdown voltage deterioration. be.

[Structure of the invention] (Means and effects for solving the problem) In other words, in this invention, in order to achieve the above object, (100)
Using a silicon wafer with a main surface and a (100) plane as an orientation flat, a groove is formed with side walls perpendicular to the main surface and parallel or perpendicular to the orientation flat surface. After forming an element isolation region within the groove or forming a thermal oxide film to cover the inside of the groove, a semiconductor element such as a MOS transistor, a capacitor element, or a high-resistance element is placed in the groove with the sidewall of the groove as a channel region. We are trying to form a

By doing this, since the crystal planes of the bottom and sidewalls of the groove are both (100) planes, problems caused by differences in crystal planes can be avoided, and since the (110) plane, which has a large number of fixed charges, is not used, the fixed charges can be reduced. It is also possible to avoid problems caused by

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings. FIGS. 1(a) to (f) show that the present invention is applied to a capacitive element (
The manufacturing process when applied to trench type capacitors is being sequentially performed. First, (a) as shown in figure (100)
A field oxide film is selectively formed on the surface of a P-type silicon wafer (silicon substrate) 21 having the (100) crystal plane as its main surface and an orientation flat 22 formed on the (100) crystal plane. Subsequently, RIE is selectively performed using the resist pattern as a mask to form a groove 23 for forming a capacitive element in the element region. At this time, the planar shape of the groove 23 is rectangular, and the orientation flat 22
formed in a direction parallel or perpendicular to. As a result,
The side walls (perpendicular to the main surface) of the groove 23 all have (100) crystal planes, as shown in FIG. Moreover, the groove bottom parallel to the main surface of the silicon substrate 21 is naturally (1
Since it has a (00) crystal plane, all the groove walls forming the groove 23 have a (100) crystal plane. Note that the groove 23 in the figure (a) is shown only for the purpose of showing its direction, and is completely different from its actual size.

A cross-sectional configuration diagram of the element region in which the groove 23 for the capacitive element is formed in this manner is shown in FIG.

Next, a PSG film (phosphorus-doped silicon oxide film) 25 having a thickness of about 3,000 thick is deposited on the entire surface using the CVD method, as shown in FIG. As a result, phosphorus is thermally diffused from the PSG film 25 into the silicon substrate 21 to form an N+ type impurity region 26.

Next, the PSG film 25 is peeled off, and the silicon substrate 21 is removed.
The surface is thermally oxidized to form a thermal oxide film 27 having a thickness of approximately 100 mm. Subsequently, a polycrystalline silicon layer 28 having a thickness of about 3,500 wafers is deposited by the CVD method, and the polycrystalline silicon layer 28 is deposited at a temperature of 900°C.
After 0 minutes of phosphorus diffusion, polycrystalline silicon@29 is again deposited on the entire surface by the CVD method to fill in the grooves 23, thereby obtaining the structure shown in FIG. 3(e).

After that, by removing unnecessary portions of thermal oxidation 1I27 and polycrystalline silicon layers 28 and 29 by RIE (f)
As shown in the figure, a capacitive element is formed using the N+ type impurity region 26 and the polycrystalline silicon layer 28 as electrodes, and the thermal oxide film 27 as a dielectric.

In the capacitive element formed according to the above embodiment, the groove 2
Since all the side walls of 3 have (100) crystal planes,
A thermal oxide film 27 is formed with a uniform thickness. Therefore, problems such as deterioration of breakdown voltage due to non-uniform thickness of the oxide film 27 do not occur, and excellent characteristics can be obtained.

Note that the above embodiment is an example in which the present invention is applied to a capacitive element, but it is also possible to separate a well region in 0MO8 or form an element isolation region, form a high resistance element on a thermal oxide film in a trench, and furthermore, It goes without further explanation that if this invention is applied to the formation of a MOS transistor in which the sidewalls of the trench are used as channel regions, the effect of suppressing current leakage caused by fixed charges generated at the interface with the insulating film can be obtained. it is obvious.

[Effects of the Invention] As explained above, according to the present invention, high integration can be achieved by utilizing trenches having sidewalls perpendicular to the main surface of a silicon substrate for forming semiconductor elements, separating elements, etc. In a trench-type semiconductor device, it is possible to obtain a semiconductor device that can avoid problems caused by the difference in crystal plane between the bottom and sidewalls of the trench, such as current leakage and breakdown voltage deterioration.

[Brief explanation of the drawing]

FIG. 1 is a diagram for explaining a semiconductor device according to an embodiment of the present invention, and FIGS. 2 and 3 are sectional views for explaining a conventional semiconductor device, respectively. 21... P type silicon wafer, 22... Orientation flat, 23... Groove, 24... Field oxide film, 25... PSGI1126... N" type impurity region, 27... Thermal oxidation Film, 28.29...polycrystalline silicon layer. Applicant's representative Patent attorney Takehiko Suzue Figure 1 Q 0 -ノ
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Claims (4)

[Claims] (1) A silicon wafer with the (100) plane as the main surface and an orientation flat formed on the (100) plane;
A groove formed in the main surface of the silicon wafer and having sidewalls perpendicular to the main surface and parallel to the orientation flat, and an element isolation region formed in the groove, or along the sidewalls and bottom of the groove. What is claimed is: 1. A semiconductor device comprising: a semiconductor element having a thermally oxidized film formed thereon; (2) The semiconductor device according to claim 1, wherein the semiconductor element is a MOS transistor having a channel region along the sidewall of the trench. (3) The semiconductor device according to claim 1, wherein the semiconductor element is a capacitor whose dielectric is a thermal oxide film formed on the side wall of the trench. (4) The semiconductor device according to claim 1, wherein the semiconductor element is a high resistance element formed in the groove via a thermal oxide film formed on the sidewall of the groove. .