JPS63229595A - Article discriminating system - Google Patents

Abstract

PURPOSE:To efficiently transmit electric power and data and to efficiently send the data even when a main body and an ID unit are at a large distance by providing an oscillator which oscillates at the same frequency continuously, a resonance circuit, a rectifying and smoothing circuit, etc. CONSTITUTION:The oscillator 18 of the read/write control unit 3 continues the oscillation at the same frequency and its oscillation signal is sent to an amplifier 24 through an amplifier 22 and an inverting circuit 23 and sent to the ID unit 2 from the transmission coil L2 of the resonance circuit. Therefore, the unit 2 fitted to an article approaches the head part 5 of the unit 3, the coil 2L sends the high frequency signal to the resonance circuit of the unit 2. Consequently, the signal is converted into a DC voltage through the rectifying and smoothing circuit of the unit 2 to supply currents to the respective blocks of the unit 2, which begins to operate and send data to the unit 3. Further, the data can securely be sent even when the main body 4 of the unit 3 and unit 2 are at a long distance.

Description

[Detailed Description of the Invention] [Field of the Invention] The present invention relates to an article identification system used for the management of tools of machine tools, parts in factories, products, or logistics systems, and is particularly characterized by the signal format during data transmission. The present invention relates to an identification system having the following features.

[Prior art and its problems]

(Prior art) In order to mechanize the tool management of conventional machine tools and the identification of parts and products on assembly lines in factories, tools 1
A system is needed to identify and manage various items such as parts and products. Conventional management systems of this type include a method of attaching a label consisting of a barcode or the like to the object to be detected, and a method of attaching a group of magnets that represent data in binary values to an object for identification. A management system is known that retains data by inverting it. However, such a management system has problems in that it takes time to rewrite data, the reliability of the data is low, and the amount of information that can be held is small. Therefore, we have proposed an article identification system in which a memory is installed in the object to be identified, the necessary information is written in such memory using contact type or baseband data transmission, and the information is read out as needed. has been done.

(Problem to be solved by the invention) However, according to such a conventional identification system,
It required a backup battery to retain the contents of the memory, which was time-consuming to manage and had the disadvantage of poor shock resistance and vibration resistance.In addition, there are contact and non-contact data transmission methods. A contact type system is considered, but in the case of a contact type, it is necessary to perform accurate positioning, and there is a problem that poor contact tends to occur at the contact point, making it impossible to write data reliably. . Furthermore, in the case of a non-contact type, a conventional baseband system is used to directly transmit a digital signal intermittently using electromagnetic waves or the like to provide the signal to a memory unit attached to an article, but this method has the problem of low reliability.

In addition, in baseband transmission, the signal is intermittent depending on the data, so it is difficult to transmit power using the carrier, and if the distance between the transmission device itself and the memory unit is short, power transmission becomes difficult. was there.

In order to solve this problem, it may be possible to transmit data using a so-called frequency shift keying (FSK) method, in which carriers are continuous and their frequencies are changed in accordance with the data. However, according to the FSK method, it is necessary to select the resonant circuit of the tuning circuit provided in the memory unit near the center of these different frequencies.
When outputting a signal at any frequency, the power efficiency becomes lower than the peak value. Therefore, there is a drawback that power transmission efficiency is poor and data transmission is not reliable if the distance between the control device main body and the memory unit is large.

[Purpose of the invention]

The present invention was made in view of the problems of the conventional article identification system, and is capable of transmitting power and data with high efficiency, and even when the distance between the main body and the ID unit is increased. The technical challenge is to ensure that data can be transmitted reliably.

[Structure and effects of the invention]

(Means for Solving the Problems) The present invention provides an article identification system that includes an ID unit attached to an article to be identified, and a write/read control unit that writes data to and reads data from the ID unit. FIG. 1 shows a system.

As shown in FIGS. 2 and 4, the ID unit includes a resonant circuit including a coil, data receiving means for receiving data based on a signal obtained from the resonant circuit, and identification data of the article to which the ID unit is attached. a non-volatile memory that stores data, and a memory that controls writing and reading of data into the memory based on a signal obtained from the data receiving means, and also changes the resonant frequency of a resonant circuit based on the read data signal. It has a control means and a rectification/smoothing circuit that supplies DC power to each part of the ID unit by rectifying and smoothing the output obtained from the resonant circuit, and the write/read control unit has a constant frequency. an oscillator that oscillates a signal; and data sending means that transmits data to the ID unit based on the oscillation output of the oscillator.
A coil to which the output of the oscillator is applied, an adder that adds the signals of the same level with the phases reversed to the output of the oscillator and the coil, and a resonant frequency of the resonant circuit when the ID unit approaches. a phase gate means that generates a gate signal with a changing phase of the addition output of the adder based on a change in the phase gate means; and a data processing means that supplies serial data to be sent to the data sending means and converts the data obtained from the phase detector into a parallel signal for processing. This is a characteristic feature.

(Operation) According to the present invention having such characteristics, the oscillation circuit of the write/read control unit always continues to oscillate at the same frequency. The ID unit rectifies and smoothes the signal obtained by the resonant circuit, and supplies power to each part. A signal is transmitted by changing the resonant frequency based on data read from the ID unit at a predetermined timing determined every predetermined period of a high frequency wave obtained by the resonant circuit of the ID unit. Then, the write/read control unit detects a signal based on the change in coil inductance at a predetermined phase of the adder, demodulates the sent data, and transmits it to the data processing means. ing.

(Effects of the Invention) As described above, according to the present invention, the baseband method and FSK
Unlike other systems, it always oscillates continuously at the same frequency, and uses electromagnetic coupling to supply power to the ID Uni-Node. Therefore, by providing the ID unit with a resonant circuit tuned to that frequency, it is possible to stably supply power to the ID unit with high efficiency. Therefore, power efficiency is improved and data transmission can be performed even when the write/read control unit and the ID unit are far apart. In addition, when transmitting a signal to the write/read control unit, the ID unit changes the resonant frequency of the resonant circuit at a predetermined timing, and by detecting the presence or absence of this change, the write/read control unit transmitting signals to the side. Therefore, since the resonant frequency of the resonant circuit changes in an extremely short period of time, it has almost no adverse effect on the efficiency of power transmission (power transmission and signal transmission can be performed with high efficiency).

[Explanation of Examples]

FIG. 1 is a block diagram showing the structure of an article identification system according to an embodiment of the present invention. In this figure, the article identification system includes an ID unit 2 that is directly attached to an article 1 such as a tool, part, or product to be identified, and a write/read control unit 3 that writes and reads data to and from the ID unit 2. There is. The write/read control unit 3 is provided in a position close to the write/read control device main body 4 and the ID unit 2, and includes a head section 5 for writing and reading data to and from the ID unit 2. The ID unit 2 and the write/read control unit 3 constitute an article identification system. The write/read control unit 3 is connected to, for example, a higher-level control device 6, and configured to write and read data from the higher-level control device 6 to the ID unit 2 via the write/read control unit 3. There is.

(Configuration of the write/read control unit) The write/read control unit 3 is a microprocessor (MPU) that controls writing and reading of data to the ID unit 2, as shown in a detailed block diagram in FIG. 1
1, a read only memory (ROM) 12 for storing the system program, a random access memory (RAM) 13 for temporarily holding data, and a serial interface 14 for serial data transmission with the ID unit 2. It has an external interface 15 and a display section 16 for interfacing with the host control device 6. The MPUI l connects the ID unit 2 via the serial interface 14 according to a predetermined processing program.
The digital data is sent to the switching circuit 17 as a serial signal of NRZ.
given to.

Now, as shown in the figure, the head section 5 has an oscillator 18 that oscillates a high frequency wave of a constant frequency, and its oscillation output is transmitted to the frequency divider 19 and counters 20 and 2 of the write/read control device main body 4.
1 is given. The counters 20 and 21 output pulses corresponding to the positive and negative half cycles of the oscillator at predetermined intervals, for example, every nine cycles, by shaping and counting the high frequency signals. The respective outputs of counters 20 and 21 are applied to switching circuit 17. Further, the output of the oscillator 18 is applied to an amplifier 24 via an amplifier 22 and an inverting circuit 23. The switching circuit 17 switches the output of the counter 20.21 based on the signal from the serial ink-face 14 and applies it to the amplifiers 22.24 through terminals 17a and 17b, respectively, to change the amplification factor. amplifier 22.24
The outputs of are connected to both ends of coil L1 and capacitors C1 and C, respectively.
2 to both ends of the coil L2.

Now, the midpoint of the coil L2 is connected to one input terminal of the adder 25. The output of the oscillator 18 is then output to the phase shift circuit 2.
given to 6. The phase shift circuit 26 is the ID unit 2
This is to finely adjust the phase of the output of the oscillator 18 so that the signal has the same phase as one input terminal of the adder 25 when the two input terminals are not close to each other. It is adjusted to have the same amplitude as the amplitude obtained from the coil L2 and is applied to the adder-25. Adder 25 adds these signals, and its output is given to phase detector 28. The output of the oscillator 18 is also provided to a phase gate 29. Phase gate 29 is oscillator 1
The 0 phase detector 28 generates a minute time gate signal at a predetermined phase of each period of the output of the 8, for example, the phase of 0 or 90 degrees, and the output thereof is given to the phase detector 28.
The presence or absence of the output of the adder 25 is detected by determining the output of the adder 25 at the timing of this gate signal, and the output is transmitted to the code converter 31 via the amplifier 30. The code converter 31 converts the data sent from the ID unit 2 into an NRZ signal based on the output from the frequency divider 19, and provides the signal to the serial interface 14. Here MPUI 1. ROMI 2. RAMI
3 and the serial interface 14 constitute a data processing means 32 that sends serial data to be transmitted to the ID unit 2 and receives and processes serial data obtained from the ID unit. Furthermore, the switching circuit 17, counters 20, 21, inverting circuit 23, and amplifier 22 are
It constitutes a data sending means for sending data to the unit 2.

Next, the detailed structure of the head section 5 will be explained with reference to FIG. As described above, both ends of the coil L2 are connected to the amplifiers 22 and 24 via the coil L1 and capacitors CL and C2. The coil L2 is a transmission coil L2a that is provided opposite to the D unit 2, supplies power to the ID unit 2, and performs data transmission, and a comparison coil L2a that has the same inductance and is built into the head unit 5.
It consists of b. A capacitor C3 is connected in parallel to the coil L1 as shown.

Capacitors C1 and C2 are used to block direct current components, and are sufficiently larger than capacitor C3 and have low impedance relative to the oscillation frequency. These coils LL and L2 and capacitor C3 form a resonant circuit. Ru. The aforementioned oscillator 18 generates a signal having a frequency substantially equal to the resonant frequency of this resonant circuit.

The output from the oscillator 18 is applied to an amplifier 22 via a capacitor C4, and is further applied to an amplifier 24 via an inverting circuit 23 and a capacitor C5.

The amplifier 22 includes a transistor Tri that amplifies the signal given from the oscillator 18 and a transistor Tr2 that becomes conductive when a gain conversion signal is applied to increase the excitation current of the resonant circuit, thereby increasing the amplification factor. The output of the oscillator 18 is amplified by changing it continuously.

Similarly, the amplifier 24 includes a transistor Tr3 that amplifies the signal applied via the inversion circuit 23, and a transistor Tr4 that becomes conductive when a gain conversion signal is applied to increase the excitation current of the resonant circuit. Thereby, the amplification factor is changed discontinuously to amplify the output of the oscillator 18.

(Configuration of ID unit) As shown in FIG. 4, the ID unit 2 is a resonant circuit including a coil, for example, an LC consisting of a coil L3 and a capacitor C6.
It has a resonant circuit 41. The LC resonance circuit 41 includes a coil L3. The capacitor C6 has the same resonant frequency as the oscillator 18 of the write/read control unit 3, and the resonant frequency can be varied by connecting and connecting the capacitor C7 in parallel to the resonant circuit. Both ends thereof are connected to a rectifying/smoothing circuit 42. The rectification/smoothing circuit 42 performs full-wave rectification of the high frequency signal obtained by the detection coil L3 and supplies a constant DC voltage to each block of the ID unit 2. Also coil L3
A pair of voltage detectors 43 and 44 are connected to both ends of the .

The voltage detectors 43 and 44 detect large amplitude pulses (giant pulses) in the positive direction and in the negative direction superimposed on the carrier, respectively, and their detection outputs are given to the demodulator 45, respectively. The demodulator 45 converts the NRZ signal provided by the write/read control unit 3 from the provided pulse signal.
For example, the output from the voltage detectors 43 and 44 is applied to the cent and reset terminals, respectively, and the clock is the logical sum of these outputs.
It is composed of 3T flip-flops and the like. Demodulator 4
The output of 5 is given to the memory control section 46. Also coil L
A carrier extraction circuit 47 composed of a Schmitt trigger circuit, a frequency divider, etc. is provided at one end of the carrier extraction circuit 47, and the frequency-divided output is given to the memory control section 46 as a clock signal. The memory control unit 46 converts the serial digital signal obtained from the demodulator 45 into a parallel signal, determines the command included in the data, and converts the data into a non-volatile memory 48, such as an electrically writable and erasable programmable ROM (EEPROM). It controls writing of data to and reading of data from the memory 48. Further, the data and clock signal read from the memory control section 46 are given to the LC resonant circuit 41 as a control signal for changing the resonant frequency of the LC resonant circuit 41.

FIG. 5 is a circuit diagram showing the detailed configuration of the LC resonance circuit 41 and the rectification/smoothing circuit 42 in the ID unit 2. As shown in this figure, the LC resonance circuit 41 includes coil L3. A capacitor C7 is further connected in parallel with an analog switch 49 to the parallel circuit of the capacitor C6. A full-wave rectifier circuit consisting of diodes D1 to D4 and a rectifier circuit consisting of capacitors C8 and C9 are connected to both ends of the LC resonant circuit 41 via resistors R1 and R2. The voltages at both ends are further connected in common through resistors R3 and R4, and the ID
A DC voltage is supplied to each block within the unit 2. Both ends of the smoothing capacitors C8 and C9 are connected to transistors Tr5 and Tr5 of voltage detectors 43 and 44, respectively. The detection coil L3 is connected to the base of each transistor Tr6, and both ends of the detection coil L3 are connected to the base of each transistor Tr5. Connected to the emitter end of Tr6. Transistor Tr5. Tr6 is a PNP transistor whose collector detects a positive or negative giant pulse superimposed on carriers.

(Configuration of Memory Control Unit) FIG. 6 is a block diagram showing the detailed configuration of the memory control unit 46. In this figure, the memory controller 46 is a demodulator 45
S to convert the serial digital signal obtained from
It has a /P converter 51 and a command decoder 52 that decodes commands of parallel signals output from the converter 51. S
A serial input control section 53 is connected to the /P converter 51. The serial input control section 53 converts the applied serial signal into parallel data at a necessary time by applying a clock signal to the S/P converter 51 at a predetermined timing. The command decoder 52 includes a command register 52a that temporarily holds commands given from the write/read control unit 3, an address register 52b that temporarily holds addresses, a data register 52C that temporarily holds data, and the number of bytes of successive data. A byte number counter 52d is provided. The command decoder 52 includes a status control section 54 that controls execution of commands. A memory control circuit 55 is connected, and an address generation circuit 57 is further connected via an address bus 56. The status control section 54 controls each block to execute a given command based on a clock signal given from the carrier extraction circuit 47. Further, the memory control circuit 55 controls the writing/reading of data in the memory 48, that is, the EEPROM, based on the write and read signals from the status control section 54.

Further, the output of the data register 52c of the command decoder 52 is provided to the memory 48 via the data bus 58. A data buffer 59 that temporarily holds data read from the memory 48 is connected to the data bus 58 .

The address generation circuit 57 sequentially generates addresses based on the step signal given from the status control section 54 based on the address value from the address register 52b of the command decoder 52, and the address signal is sent to the memory 48 and the status register. given to 60.

The status register 60 is a register that holds transmission/reception commands, execution completion, and error information, and is
8 is located in the same part of the address space. Further, the parallel output of the data buffer 59 is connected to a P/S converter 61.

Further, the status control section 54 is a sequential circuit that advances the control of each section when a predetermined condition is satisfied, and provides an output start signal to the serial output control section 62 when outputting data. The serial output control unit 62 provides the P/S converter 61 with a clock signal corresponding to the timing of transmission, and
This adds start and stop bits. P/S
The converter 61 converts the data held in the data buffer during data reading into a serial signal and provides it to the LC resonance circuit 41 described above.

(Operation of Example) Next, the operation of this example will be explained with reference to waveform diagrams. FIGS. 7 and 8 are waveform diagrams showing waveforms at various parts of this embodiment. Now, the oscillator 18 of the write/read control unit 3
continues to oscillate at a constant frequency as shown in FIG. 7(a). Although this oscillation waveform is shown in a simplified manner in the figure, it actually has a single frequency component, and the signal is passed through the amplifier 22 and the inverting circuit 23 to the amplifier 24.
The signal is transmitted to the ID unit 2 through the transmission coil L2a of the resonance circuit. Therefore, when the ID unit 2 attached to the article 1 approaches the head section 5 of the write/read control unit 3, the transmission coil L of the write/read control unit 3
A high frequency signal is transmitted to the LC resonance circuit 41 from 2a. Since the oscillator 18 continues to oscillate without interruption, L
The high frequency signal obtained by the C resonance circuit 41 is converted into a DC voltage by the rectifier/smoothing circuit 42, and power is supplied to each block of the ID unit 2. Therefore, ID unit 2
starts operation and becomes ready for data transmission with the write/read control unit 3. Here, the output of the oscillator 18 is given to the counters 20, 21, and the counters 20, 21 are sent to the counters 20, 21 in positive half cycles at regular intervals as shown in FIGS. 7(b) and 7(c), respectively. The counter 21 outputs a pulse waveform that rises in the negative half cycle.

These outputs are then given to the switching circuit 18.

As shown in FIGS. 7(d) and 7(f), the switching circuit 18 switches this signal using the NRZ signal given from the serial interface 14, for example, rl 101J as shown in the figure, and outputs it as a gain conversion signal from the output terminals 17a and 17b. to amplifiers 22 and 24.

Therefore, the oscillation output shown in FIG. 7(a) is intermittently amplified at a high amplification factor by this signal, and a waveform containing a giant pulse in the positive or negative direction is transmitted to the ID unit 2 as shown in FIG. 7fgl. It happens.

The ID unit 2 uses voltage detectors 43 and 44 to detect the pulse waveforms superimposed on the normal carrier and supplies them to the demodulator 45. Therefore, from the demodulator 45, FIG. 7(h)
An NRZ signal as shown in can be obtained. This signal is transmitted to the memory control section 46 as a serial signal.

On the other hand, when transmitting a signal from the ID unit 2 to the write/read control unit 3, a gain conversion signal is applied to only one amplifier 22 at a predetermined period so that a giant pulse is applied only in the positive direction, as shown in FIG. (A signal as shown in al is given to the ID unit 2. In the ID unit 2, a signal read out from the memory control section 46 is given to the resonance circuit 41 as shown in FIG. 8(b) at every predetermined cycle of the clock. ,
During this time, the analog switch 49 becomes conductive. Then, the successive signals from the ID unit 2 will cause the LC resonant circuit 4 to
1 has a different resonance frequency, and the transmission coil L of the head section 5 has a different resonance frequency.
The voltage generated at the comparison coil L2a and the voltage generated at the comparison coil L2b become different. FIG. 8C shows an enlarged view of the time axis from time t to time t2, and shows the output of the adder 25 when the ID unit 2 approaches the head section 5. I
When the D unit 2 approaches the head part 5, the voltage generated in the transmission J coil L2a is different from the voltage generated in the comparison coil L2b, so the input of the adder 25 is not completely lost as shown in FIG. 8 (dl). However, if the inductance of the coil L2a does not change, the output of the adder 25 at the time when the gate signal, which is the output of the phase gate 29 shown in FIG. However, as shown in FIGS. 8(d) to 8(f), at the time when the analog switch 49 becomes conductive (ti~1
In 1), since the inductance of the transmission coil L2a is different, when the gate signal of the phase gate 29 is applied, the adder 2
The output obtained from 5 is no longer at zero level. Therefore, this signal is applied to amplifier 30 and amplified as shown in FIG. 8(g). This signal is applied to the code converter 31, converted to an NRZ signal, and sent to the serial interface 14.
It is further converted into a parallel signal and sent to the MPU 11.
given to. In this way, half-duplex data transmission can be performed between the write/read control unit 3 and the ID unit 2.

Note that this embodiment shows a transmission data method using giant pulses in the positive and negative directions to transmit data from the write/read control unit to the ID unit.
A transmission method may be applied in which a timing signal is given at every predetermined period using giant pulses in the forward direction only, and giant pulses are superimposed corresponding to data to be transmitted during that period.

In addition, in this embodiment, electrically writable and erasable EE is used as a memory.
Although PROM is used, various electrically programmable and erasable nonvolatile memories can be used.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the overall structure of an article identification system according to an embodiment of the present invention, FIG. 2 is a block diagram showing the structure of a write/read control unit of this embodiment, and FIG. 3 is a block diagram showing the structure of a write/read control unit of this embodiment. FIG. 4 is a block diagram showing the configuration of the ID unit. FIG. 5 is a circuit diagram showing the detailed configuration of the readout control unit's head/node section 5. FIG. 5 shows the LC resonance circuit, rectification/smoothing circuit, and voltage detection inside the ID unit. 6 is a program diagram showing the detailed structure of the memory control section, and FIG. 7 is a circuit diagram showing the detailed structure of the memory control unit. FIG. 7 is a circuit diagram showing the detailed structure of the memory control unit. FIG. 8 is a waveform diagram showing the waveforms of each part when transmitting data from the ID unit to the write/read control unit. 1-・-Goods 2-・-・-ID unit 3-・
・-Writing/reading control unit/nod 4-----Writing/reading control device body 5--------Head section
11--MPU14--Serial interface 17--) Switching circuit 18--
・−・Oscillator 20.21・・・−・−Counter
22.24--Amplifier 23--One inversion circuit 26--Phase shift circuit 27-
--- Level adjuster 29 --- Phase gate 3
2.--Data processing means 41--Resonance circuit 42--Rectification/smoothing circuit 43.44-
・−・−Voltage detector 45−・−・−Demodulator 46
-・-Memory control unit 48-・-・-Memory patent applicant Tateishi Electric Co., Ltd. agent Patent attorney Yoshiki Kaimoto (and 1 other person) 1st +A 3----Includes 1/side b4I+3 Figure 3 Figure 4 Figure 5 Figure 7 (j) Fi-key i4s

Claims (1)

[Claims] (1) An article identification system comprising an ID unit attached to an article to be identified, and a write/read control unit that writes data to and reads data from the ID unit, the ID unit comprising: a resonant circuit including a coil; a data receiving means that receives data based on a signal obtained from the resonant circuit; a nonvolatile memory that stores identification data of an article to which an ID unit is attached; and data obtained from the data receiving means. a memory control means for controlling writing of data to and reading of data from the memory based on a signal, and changing a resonant frequency of the resonant circuit based on the read data signal; and an output obtained from the resonant circuit. Rectifier and smoother that supplies DC power to each part of the ID unit by rectifying and smoothing.
a smoothing circuit, and the write/read control unit includes: an oscillator that oscillates a signal at a constant frequency; and data sending means that transmits data to the ID unit based on the oscillation output of the oscillator. a coil to which the output of the oscillator is applied; an adder to which the output of the oscillator and the signal of the same level with inverted phases obtained by the coil are applied; and an adder for adding the respective signals; phase gate means for generating a gate signal with a changing phase of the addition output of the adder based on a change in the resonant frequency of the circuit; and presence or absence of a signal of the adder when the gate signal of the phase gate means is applied. a phase detector that detects a data signal sent out from the ID unit based on the data, and a data processor that provides serial data to be sent to a data sending means and converts the data obtained from the phase detector into a parallel signal for processing. An article identification system comprising: means.