JPS63221950A - Article discriminating system - Google Patents

Abstract

PURPOSE:To dispense with a power source for a unit to be attached to an article in a noncontact manner as well as to improve the reliability of data transmission, by using a fixed memory large in capacity as a memory means to be attached to the article, and making the data transmission and signal transmission so as to be done at the same time. CONSTITUTION:When the identification card 2 attached to an article 1 to be discriminated comes nearer to a head part 5 of a write/read control unit 3, a high frequency signal to be obtained in a resonance circuit is smoothed and rectified, whereby DC power is fed to the ID unit 2. And, oscillation frequency of an oscillating circuit of the unit 3 is altered to discontinuity, and necessary data are transmitted to the ID unit 2 which reads necessary data from a memory, making resonance frequency of a resonance circuit alter. Since load of the oscillation circuit varies with a variation in the resonance frequency, the unit 3 receives these data on the basis of variations in the load, and it demodulates the data, thereby reproducing the read data.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of the Invention] The present invention relates to an identification system for tools for machine tools, parts in factories, products used in product management, distribution systems, and the like.

[Prior art and its problems]

(Prior art) In order to mechanize the tool management of conventional machine tools and the identification of parts and products on assembly lines in factories, tools 1
A system is needed to identify and manage various items such as parts and products. Conventional management systems of this type include a method of attaching a label consisting of a barcode or the like to the object to be detected, and a method of attaching a group of magnets that represent data in binary values to an object for identification. A management system is known that retains data by inverting it. However, such a management system has problems in that it takes time to rewrite data, the reliability of the data is low, and the amount of information that can be held is small. Therefore, we have proposed an article identification system in which a memory is installed in the object to be identified, the necessary information is written in such memory using contact type or baseband data transmission, and the information is read out as needed. has been done.

(Problems to be Solved by the Invention) However, such conventional identification systems require a bank-up battery to retain the contents of the memory, which requires time and effort to manage, and is not shock resistant. sex,
It had the disadvantage of poor vibration resistance.

In addition, contact and non-contact systems can be considered as data transmission systems, but in the case of a contact system, it is necessary to perform accurate alignment, and problems with poor contact tend to occur at the contact points, so it is difficult to ensure that data is transmitted reliably. There was a problem that it was not possible to write. Furthermore, in the case of a non-contact type, a conventional baseband system is used to directly transmit a digital signal intermittently using electromagnetic waves or the like to provide the signal to a memory unit attached to an article, but this method has the problem of low reliability.

Furthermore, transmission using the baseband method has the drawback that power cannot be supplied along with the signal, and the memory itself requires a power source.

[Purpose of the invention]

The present invention was made in view of the problems of the conventional article identification system, and uses a large-capacity nonvolatile memory as a storage means of a unit attached to an article, and simultaneously transmits data and signals. A technical problem is to eliminate the need for a power source for a unit that is attached to an article in a non-contact manner and to improve the reliability of data transmission.

[Structure and effects of the invention]

(Means for Solving the Problems) The present invention provides an article that includes an ID unit attached to an article to be identified, and a write/read control unit that writes data to and reads data from an 8i 1 D unit. An identification system, FIG.

As shown in FIGS. 2 and 4, the ID unit includes a resonant circuit including a coil, data demodulation means for demodulating a signal based on the frequency of the output obtained from the resonant circuit, and an object to which the ID unit is attached. An electrically writable and erasable non-volatile memory that stores identification data, controls writing and reading of data to the memory based on the demodulated signal, and controls the resonant circuit based on the read out data. I
A rectifier/smoothing circuit that supplies DC power to each part of the D unit, and a write/read control unit,
An oscillation circuit that includes an oscillation coil and is energized based on a data signal to be sent to the ID unit and discontinuously changes its oscillation frequency, and data given by the ID unit based on the frequency change of the signal obtained from the oscillation circuit. It is characterized by having a data demodulation means for demodulating a signal, and a data processing means for supplying serial data to be sent to an oscillation circuit and converting the data given by the data demodulation means into a parallel signal for processing. It is something.

(Function) According to the present invention having such characteristics, an ID unit including a resonant circuit and a memory is attached to an article to be identified. The oscillation circuit of the write/read control unit constantly oscillates, and when the ID unit reaches a predetermined position, it smooths and rectifies the inter-frequency signal obtained in the resonant circuit, providing a stable signal to the ID unit. DC power is supplied to the

By discontinuously changing the oscillation frequency of the oscillation circuit of the write/read control unit, necessary data is transmitted to the ID unit by FSK modulation. ID
The unit receives and demodulates the data to identify the signal and write the required data to the memory or read the required data from a predetermined address in the memory to change the resonant frequency of the resonant circuit. In this way, the load on the oscillation circuit changes as the resonant frequency changes on the write/read control unit side, so data can be received based on changes in the load, and the data can be demodulated and read out. I'm trying to reproduce the data.

(Effects of the Invention) As described above, according to the present invention, power is supplied to the ID unit using electromagnetic coupling, and unlike the baseband method, the FSK method is used. Therefore, oscillation continues at all times, and DC power can be stably supplied to the ID unit. Also, half-duplex data transmission between the ID UNISO 1- and the write/read control unit can be performed without contact. In addition, electrically writable and erasable non-volatile memory is used as the memory of the ID unit, and power is not supplied to the ID unit when it is not close to the write/read control unit, but the contents of the data are It is held as it is, and data transmission can only be performed when it is in close proximity to the write/read control unit. Furthermore, since data is transmitted using the FSK method, which has a low transmission error rate, signal reliability can be improved.

[Explanation of Examples]

FIG. 1 is a block diagram showing the structure of an article identification system according to an embodiment of the present invention. In this figure, the article identification system includes an ID unit 2 that is directly attached to an article 1 such as a tool, part, or product to be identified, and a write/read control unit 3 that writes and reads data to and from the ID unit 2. There is. The write/read control unit 3 is provided in a position close to the write/read control device main body 4 and the ID unit 2, and includes a head section 5 for writing and reading data to and from the ID unit 2. The ID unit 2 and the write/read control unit 3 constitute an article identification system. The write/read control unit 3 is connected to, for example, a higher-level control device 6, and configured to write and read data from the higher-level control device 6 to the ID unit 2 via the write/read control unit 3. There is.

(Configuration of the write/read control unit) The write/read control unit 3 is a microprocessor (MPU) that controls writing and reading of data to the ID unit 2, as shown in a detailed block diagram in FIG. 1
1, a read only memory (ROM) 12 for storing the system program, a random access memory (RAM) 13 for temporarily holding data, and a serial interface 14 for serial data transmission with the ID unit 2. It has an external interface 15 and a display section 16 for interfacing with the upper system device 6. The MPU II communicates with the ID unit 2 via the serial interface 14 according to a predetermined processing program.
The digital data is sent to the encoder circuit 1 as an NRZ serial signal.
7 is given. The encoding circuit 17 converts the serial signal into a pi-phase signal and is composed of an exclusive OR circuit, the output of which is given to the LC oscillator 18 of the head section 5 as a control signal. The LC oscillator 18 always continues oscillating wf, and the encoding circuit 17
An oscillator whose oscillation frequency is changed by a control signal from the ID unit 2 via an oscillation coil L1.
At the same time, the oscillation output is provided to the frequency divider 19 and the PLL circuit 20. Frequency divider 19 is LC oscillator 18
A clock signal is provided to the encoding circuit 17 and the serial interface 14 by shaping the output of the waveform and dividing the frequency. Further, the PLL circuit 20 is a well-known phase-locked loop circuit, and the LC oscillator 18 has an I
A signal is received from the ID unit 2 by detecting a change in the oscillation frequency when the resonant circuits of the D unit 2 are close to each other and have different loads. PLL circuit 20
The output of is applied via a low-pass filter 21 to an amplifier 22 that amplifies the AC component. The output of the amplifier 22 is then given to a decoding circuit 23. The decoding circuit 23 is an ID
Since the signal from the UNI 71.2 is pie-phase coded as described later, the pie-phase code obtained from the amplifier 22 is converted into an NRZ serial signal. That is, the decoding circuit 23 includes a clock extractor 23a that extracts a clock, and an exclusive OR circuit (hereinafter referred to as an EOR) that receives the clock signal and the high phase code as input.
It consists of a decoding section 23b by a circuit (referred to as a circuit),
The input high-phase code is converted into an NRZ code and the output is sent to the MPU II via the serial interface 14.
give to Here, MPUII, ROM12. RAM13
The serial interface 14 constitutes a data processing means 24 that sends serial data to be transmitted to the ID unit 2 and receives and processes serial data obtained from the ID unit, and the PLL circuit 20. Low pass filter 21. The amplifier 22 and the decoding circuit 23 are data demodulating means 25 that converts the high frequency signal into serial data.
It consists of

Next, FIG. 3 is a circuit diagram showing the detailed configuration of the LC oscillator 18 of the head section 5. As shown in FIG. As shown in the figure, the LC oscillator 18 is an oscillator in which a resonance circuit consisting of an oscillation coil L1 and capacitors CI and C2 is connected to a transistor Tri, and a transistor Tr2 and a coil L2 are further connected in parallel to the LC resonance circuit. There is. A transistor T controlled by the encoding circuit 17 is connected to the base of the transistor Tr2.
r3 is connected. Switching transistor T r2
．． Since the coil L2 is connected in parallel to the resonant circuit by opening and closing the T r3, the oscillation frequency can be changed discontinuously. Further, a frequency divider 19. is connected to the hot end side of the coil L2 via a capacitor C3. A PLL circuit 20 is connected.

(Configuration of ID unit) As shown in Fig. 4, the 1D unit 2 is a resonant circuit including a coil, for example, an LC consisting of a coil L3 and a capacitor C4.
It has a resonant circuit 31. The LC resonance circuit 31 is configured such that its oscillation frequency can be varied by, for example, connecting and connecting a capacitor C5, and one end of the circuit is provided to a level converter 32 and a rectification/smoothing circuit B33.

The level converter 32 converts the DC level of the high frequency signal obtained from the LC resonance circuit 31, and its output is given to the PLL circuit 34. The PLL circuit 34 performs frequency shift keying (
It demodulates the FSX modulated signal and converts it into the original serial digital signal (bi-phase encoded signal).

The output of the PLL circuit 34 is applied via a low-pass filter 35 to an amplifier 36 that amplifies the AC component. The output of amplifier 36 is given to decoding circuit 37. The decoding circuit 37 has a clock extraction section 37a that extracts a clock from the output of the amplifier 36, and a decoding section 37b consisting of an exclusive OR circuit, and converts the pi-phase encoded digital signal into the original NRZ digital signal. It converts it into a signal.

This NRZ digital serial signal is then given to the memory control section 38. Connected to the memory control section 38 are a memory 39 consisting of a programmable read-only memory (hereinafter referred to as EEPROM), which is a nonvolatile memory that can be electrically written and erased, and a frequency divider 40 . The frequency divider 40 divides the high frequency signal obtained from the LC resonant circuit 31 via the level converter 32 to
It provides a clock signal to the Memory control unit 38
Converts the serial digital signal obtained from the decoding circuit 37 into a parallel signal, determines the command included in the data, and writes the data to the memory 39.

It controls data reading from the memory 39.

Further, the data and clock signal read out from the memory control section 38 are given to the encoding circuit 41. Encoding circuit 4
1 performs pi-phase encoding on this NRZ serial digital signal, and consists of an EOR circuit that calculates the exclusive OR of the clock signal and the NRZ signal.
It is given as a control signal to change the resonance frequency of the C resonance circuit 31. Here, the PLL circuit 34. Low pass filter 35. The amplifier 36 and the decoding circuit 37 constitute a data demodulating means 42 for demodulating the high frequency signal applied from the head section 5 of the write/read control unit node 3.

FIG. 5 shows the LC resonant circuit 31 and level converter 32 in the ID unit 2. 3 is a circuit diagram showing a detailed configuration of a rectification/smoothing circuit 33. FIG. As shown in this figure, the LC resonant circuit 31 includes coils ①, 3. In addition to the parallel circuit of capacitor C4, a capacitor C5 is connected in parallel to switching transistor Tr4.
It is connected via a Zener diode D1. A rectifier/smoothing circuit 33 having a resistor R1, a diode D2, and a capacitor C6 is connected to the LC resonant circuit 31, and its output is supplied as a power source to each part of the D unit.

Further, a level converter 32 consisting of a resistor R2, a diode D3 and a Zener diode D4 is connected to the resistor R1, and the LC
The DC level of the output signal of the resonant circuit 31 is converted to PL
The signal is applied to the L circuit 34. The aforementioned encoding circuit 41 drives the switching I transistor Tr4, and discontinuously changes the resonant frequency by turning on/off the transistor Tr4, which connects the capacitor C5 in parallel at high frequency.

(Configuration of Memory Control Unit) FIG. 6 is a block diagram showing the detailed configuration of the memory control unit 38. In this figure, the memory control unit 38 includes an S/P converter 51 that converts the serial digital signal obtained from the decoding circuit 37 into a parallel signal, and a command decoder 52 that decodes the command of the parallel signal output from the S/P converter 51. There is. A serial input control section 53 is connected to the S/P converter 51 .

The serial input control section 53 converts the applied serial signal into parallel data at a necessary time by applying a clock signal to the S/P converter 51 at a predetermined timing. The command decoder 52 includes a command register 52a that temporarily holds commands given from the write/read control unit 3, an address register 52b that temporarily holds addresses, a data register 52c that temporarily holds data, and the number of bytes of successive data. A byte number counter 52d is provided. Command decoder 5
2 includes a status control unit 54 that controls execution of commands;
．． A memory control circuit 55 is connected, and an address bus 5
An address generation circuit 57 is connected via 6. The status control section 54 controls each block to execute a given command based on a clock signal given from the frequency divider 40. Further, the memory control circuit 55 controls writing/reading of data in the memory 39, that is, the EBPROM, based on write and read signals from the status control section 54. Further, the output of the data register 52c of the command decoder 52 is given to the memory 39 via the data bus 58. A data buffer 59 that temporarily holds data read from the memory 39 is connected to the data bus 58 . The address generation circuit 57 sequentially generates addresses based on the step signal given from the status control section 54 based on the address value from the address register 52b of the command decoder 52, and the address signal is sent to the memory 39 and the status register. 6
given to 0. The status register 60 is a register that holds transmission/reception commands, execution completion, and error information, and is arranged in a part of the same address space as the memory 39. Further, the parallel output of the data buffer 59 is connected to a P/S converter 61. Further, the status control section 54 is a sequential circuit that advances the control of each section when a predetermined condition is satisfied, and provides an output start signal to the serial output control section 62 when outputting data. The serial output control section 62 provides the P/S converter 61 with a clock signal corresponding to the timing of transmission, and also adds start and stop bits. P/S converter 61
converts the data held in the data buffer into a serial signal when reading data, performs parity focus and start,
A stop pit is added to the signal and the signal is provided to the encoding circuit 41 described above.

(Operation of Example) Next, the operation of this example will be explained with reference to waveform diagrams. FIGS. 7 and 8 are waveform diagrams showing waveforms at various parts of this embodiment. First, when the ID unit 2 attached to the article 1 to be detected approaches the head section 5 of the write/read control unit 3, the coil L1 of the 50 oscillator 18 of the write/read control unit 3 A high frequency signal is transmitted to the resonant circuit 31. Since the 50 oscillator 18 continues to oscillate without interruption, the high frequency signal obtained by the LC resonance circuit 31 is converted into a DC voltage by the rectifier/smoothing circuit 33, and power is supplied to each block of the ID unit 2. Ru. Therefore, ID unit 2 starts operating,
Data transmission with the write/read control unit 3 becomes possible. Now, when writing data from the write/read control unit 3, a write command and write data are given to the serial interface 14 from the MPU II. Serial interface, 14 is Fig. 7(a)
As shown in the figure, the signal from the MPU II is converted into a serial signal and transmitted to the encoding circuit 17. The encoding circuit 17 is supplied with a clock signal obtained by frequency-dividing the oscillation output supplied from the 50 oscillator 18, and converts the NRZ signal into a biphase code as shown in Fig. 7(a) and (bl). do.

Therefore, the high phase code is conveyed as a control signal to the 50 oscillator 18 and the 50 oscillator 1 is transmitted as a control signal as shown in FIG.
The oscillation frequency of 8 changes intermittently, and FSK modulation is performed. This FSK modulated output is the L of ID unit l-2.
Since the signal is transmitted to the C resonance circuit 31, the same signal is obtained from the LC resonance circuit 31. And this output is level converter 3
2 to the PLL[l path 34 and demodulated. Then, as shown in FIG. 7(e), a signal from which high frequency components have been removed is passed through a low-pass filter 35 and is applied to a decoding circuit 37 from an amplifier 36. Since the decoding circuit 37 extracts the clock from this signal and decodes it, it is possible to restore the NRZ signal similar to that shown in FIG. 7 (al), as shown in FIG.

This signal is transmitted to the memory control section 38 as a serial signal.

On the other hand, the serial NRZ signal and clock signal read from the memory control section 38 are transmitted to the encoding circuit 41. As shown in FIGS. 8(a) and 8(b), the encoding circuit 41 converts the applied NRZ signal into a biphase code and turns on and off the transistor Tr4, thereby converting the LC resonance circuit 31.
change the resonant frequency of

This change in resonance frequency causes the L of the write/read control unit 3 to
Since the load on C oscillator 18 changes, 50 oscillator 1
The oscillation frequency of 8 will change slightly. Therefore, the oscillation frequency of the 50 oscillator 18 changes as shown in FIG. 8(C). PLL circuit 20 demodulates this frequency change and provides its output to low-pass filter 21 . Then, high frequency components are removed by a low pass filter 21,
The signal that has been amplified and converted into a bi-phase code as shown in FIG. 8 (dl) is given to the decoding circuit 23. NR as shown in figure (el)
A Z signal can be obtained. This signal is then applied to the serial interface 14, converted into a parallel signal, and given to the MPU II. In this way, half-duplex data transmission can be performed between the write/read control unit 3 and the ID unit 2.

In this embodiment, in order to transmit data from the write/read control unit 3 to the ID unit 2, the NRZ signal is first converted into a biphase code, and then the signal is transmitted from the ID unit 2 to the write/read control unit 3. Similarly, in the case of NRZ
Although the signal is converted to a high-phase code and read out, the signal can be transmitted by directly performing FSK modulation using the NRZ code without performing such code conversion, or by changing the resonance frequency of the resonant circuit 31. Needless to say, it can be done.

In addition, in this embodiment, electrically erasable EEPR is used as a memory.
Although OM is used, various electrically writable and erasable nonvolatile memories can be used.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the overall structure of an article identification system according to an embodiment of the present invention, FIG. 2 is a block diagram showing the structure of a write/read control unit of this embodiment, and FIG. 3 is a block diagram showing the structure of a write/read control unit of this embodiment. A circuit diagram showing the configuration of the I, C oscillator 18 of the read control unit, FIG. 4 is a block diagram showing the configuration of the ID unit,
FIG. 5 is a circuit diagram showing the configuration of the LC resonant circuit and level converter in the ID unit, FIG. 6 is a block diagram showing the detailed configuration of the memory control section, and FIG. 7 is the article identification system of this embodiment. A waveform diagram showing the waveforms of each part when data is transmitted from the write/read control unit to the ID unit,
FIG. 8 is a waveform diagram showing waveforms at various parts when data is transmitted from the ID unit to the write/read control unit.

Claims (1)

[Claims] (1) An article identification system comprising an ID unit attached to an article to be identified, and a write/read control unit that writes data to and reads data from the ID unit, the ID unit comprising: a resonant circuit including a coil; a data demodulator that demodulates a signal based on the frequency of the output obtained from the resonant circuit; and an electrically writable and erasable nonvolatile memory that stores identification data of an article to which the ID unit is attached. and a memory control means for controlling writing of data to and reading of data from the memory based on the demodulated signal, and changing the resonant frequency of the resonant circuit based on the read out transmission data; A rectifier that supplies DC power to each part of the ID unit by rectifying and smoothing the output obtained from the circuit.
and a smoothing circuit, wherein the write/read control unit includes an oscillation circuit that includes an oscillation coil, is energized based on a data signal to be sent to the ID unit, and discontinuously changes its oscillation frequency. and data demodulation means for demodulating the data signal provided by the ID unit based on the frequency change of the signal obtained from the oscillation circuit; 1. An article identification system comprising: data processing means for converting the data into parallel signals and processing the data.