JPS63222283A - Article identification system - Google Patents

Abstract

PURPOSE:To achieve a higher reliability, by supplying power to an ID unit by an FSK system utilizing electromagnetic coupling to enable non-contact data transmission. CONSTITUTION:An article identification system has an ID unit 2 directly mounted on article 1 and a writing/reading control unit 3 to write and read a data to the ID unit 2. The writing/reading unit 3 comprises a writing/reading controller body 4 and a head section 5. The head section 5 is arranged at a position closer to the ID unit 2 and supplies power to the ID unit 2 by an FSK system utilizing electromagnetic coupling and writes and reads data. Moreover, the writing/reading control unit 3, for example, is connected to a higher-order control device 6.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of the Invention] The present invention relates to an identification system for tools for machine tools, parts in factories, products used in product management, distribution systems, and the like.

[Prior art and its problems]

(Prior art) In order to mechanize the tool management of conventional machine tools and the identification of parts and products on assembly lines in factories, tools 1
A system is needed to identify and manage various items such as parts and products. Conventional management systems of this type include a method of attaching a label consisting of a barcode or the like to the object to be detected, and a method of attaching a group of magnets that represent data in binary values to an object for identification. A management system is known that retains data by inverting it. However, such a management system has problems in that it takes time to rewrite data, the reliability of the data is low, and the amount of information that can be held is small. Therefore, we have proposed an article identification system in which a memory is installed in the object to be identified, the necessary information is written in such memory using contact type or baseband data transmission, and the information is read out as needed. has been done.

(Problem to be solved by the invention) However, according to such a conventional identification system,
It has the drawbacks of being time-consuming to manage and having poor impact resistance and vibration resistance.

In addition, contact and non-contact systems can be considered as data transmission systems, but in the case of a contact system, it is necessary to perform accurate alignment, and problems with poor contact tend to occur at the contact points, so it is difficult to ensure that data is transmitted reliably. There was a problem that it was not possible to write. In addition, in the case of a non-contact type, conventional baseband methods have been used to directly transmit digital signals intermittently using electromagnetic waves, etc., to give them as signals to the memory unit attached to the article, but oscillations occur especially when metal objects etc. are in close proximity. The problem was that the reliability was low because the frequency and received wave level fluctuated. Another disadvantage of baseband transmission is that it is not possible to supply power along with the signal.

(Object of the Invention) The present invention has been made in view of the problems of the conventional article identification system. At the same time as transmitting a signal, it gives a signal to the unit that is attached to the article in a non-contact manner, and
The technical problem is to enable data transmission to continue without deteriorating reliability even when metal objects or the like come close to each other during signal transmission.

[Structure and effects of the invention]

(Means for Solving the Problems) The present invention provides an article identification system that includes an ID unit attached to an article to be identified, and a write/read control unit that writes data to and reads data from the 110 units. FIG. 1.

As shown in FIGS. 2 and 4, the ID unit includes a resonant circuit including a coil, data demodulation means for demodulating a signal based on the frequency of the output obtained from the resonant circuit, and an object to which the ID unit is attached. A memory for storing identification data, a memory control means for controlling writing of data into the memory and continuous output of data based on demodulated signals, and an ID unit by rectifying and smoothing the output obtained from the resonant circuit. It has a rectifying/smoothing circuit that supplies DC power to each part, and an encoding circuit that encodes the transmission data read from the memory control means using a transmission code that does not have a DC component to change the resonant frequency of the resonant circuit. The write/read control unit includes an oscillator that includes an oscillation coil and changes its oscillation frequency based on an external signal, and an oscillator that oscillates at the same frequency as the oscillator when the data to be sent is given as a control signal. a voltage-controlled oscillator, which is supplied with the respective outputs of the voltage-controlled oscillator and the oscillator and compares their phases; and a signal with a frequency of a predetermined frequency or less of the phase comparison output of the phase comparator is given to the oscillator as a frequency control signal. A low-pass filter is provided with a control signal for the low-pass filter and has a pass band corresponding to the frequency of the coded data of the ID unit. a decoding circuit that decodes the code of the data, and a data processing means that provides the serial data to be sent to the voltage controlled oscillator and converts the data provided by the data decoding circuit into a parallel signal for processing. It is characterized by this.

(Function) According to the present invention having such characteristics, an ID unit including a resonant circuit and a memory is attached to an article to be identified. The oscillation circuit of the write/read control unit constantly oscillates, and when the ID unit reaches a predetermined position, the high-frequency signal obtained in the resonant circuit is smoothed and rectified to provide a stable signal to the ID unit. DC power is supplied to the

The write/read control unit then gives the data to be sent to the voltage controlled oscillator, compares the phase difference with the oscillation output of the oscillator including the coil using a phase comparator, and controls the oscillation frequency of the oscillator via a low-pass filter. There is. This locks the phase of the oscillator, allowing the oscillator to oscillate at the same frequency as the voltage controlled oscillator. At this time, even if a metal object approaches and the oscillator frequency attempts to change, the oscillator frequency is kept at the same frequency by phase locking, and synchronized with the oscillation frequency of the voltage controlled oscillator, which changes discontinuously depending on the transmitted data. can be changed and the change can be transmitted to the ID unit. On the other hand I
The D unit identifies this signal and writes necessary data into the memory, or sequentially outputs the necessary data from the memory and encodes it into a transmission code having no DC component, thereby changing the resonant frequency of the resonant circuit. Then, since the control signal level of the low-pass filter changes according to the change in the resonant frequency, the write/read control unit side extracts the frequency corresponding to the change through the band-pass filter and converts the received data. I'm trying to get it.

(Effects of the Invention) As described above, according to the present invention, power is supplied to the ID unit using electromagnetic coupling, which is different from the baseband method. /) FSK method is used. Therefore, oscillation continues at all times, and DC power can be stably supplied to the ID unit. Also, write to ID unit without contact/
Half-duplex data transmission with the read control unit is possible. The oscillation frequency of the oscillator does not change even if a metal object comes close to the write/read control unit and ID unit, so data sent to the ID unit can be stably transmitted without being encoded. can. In addition, the signal obtained from the ID unit changes as the load on the oscillator changes, and the signal obtained from the ID unit can be extracted based on the output of the low-pass filter that controls the oscillation frequency to be constant, resulting in highly reliable data. It becomes possible to perform transmission.

[Explanation of Examples]

FIG. 2 is a block diagram showing the structure of an article identification system according to an embodiment of the present invention. In this figure, the article identification system includes an ID unit 2 that is directly attached to an article 1 such as a tool, part, or product to be identified, and a write/read control unit 3 that writes and reads data to and from the ID unit 2. There is. The write/read control unit 3 is provided in a position close to the write/read control device main body 4 and the ID unit 2, and includes a head section 5 for writing and reading data to and from the ID unit 2. The ID unit 2 and the write/read control unit 3 constitute an article identification system. The write/read control unit 3 is connected to, for example, a higher-level control device 6, and configured to write and read data from the higher-level control device 6 to the ID unit 2 via the write/read control unit 3. There is.

(Configuration of write/read control unit) Now, as shown in the detailed block diagram in FIG. 1, the write/read control unit 3 is a microprocessor (MPU) that controls writing and reading of data to the ID unit 2. 1
1, a random access memory (RAM) 13 for temporarily storing data, and a serial interface 14 for serial data transmission with the ID unit 2. It has an external interface 15 and a display section 16 for interfacing with the host control device 6. The MPU II sends data and commands to the ID unit 2 via the serial interface 14 according to a predetermined processing program, and the digital data is given to the voltage controlled oscillator 17 as an NRZ serial signal. The voltage controlled oscillator 17 is an oscillator that oscillates a signal with a frequency corresponding to a given voltage,
Its output is given to phase comparator 18. Further, the aforementioned head portion 5 is provided with an LC oscillator 19 having a coil L1. The LC oscillator 19 always continues to oscillate, and its oscillation output is given to the phase comparator 18. The phase comparator 18 compares the phases by multiplying these signals, and provides the comparison output to a low pass filter (LPF) 20. The low-pass filter 20 removes high-frequency components from the applied signal and supplies only the components below a predetermined frequency to the LC oscillator 19 as a voltage control signal, and also to a band-pass filter 21 (BPF). Here, the phase comparator 18 and the LC oscillator 19. The low-pass filter 20 constitutes a phase control loop. The bandpass filter 21 is an active bandpass filter having a pass band corresponding to the frequency of the signal sent from the ID unit 2 and a constant amplification factor, and its output is given to the decoding circuit 22. Since the signal from the ID unit 2 is biphase encoded as described later, the decoding circuit 22 converts the biphase code into an NRZ serial signal. The decoding circuit 22 has a clock extracting section 22a and a decoding section 22b consisting of an exclusive OR circuit, and provides the converted output to the MPU II via the serial interface 14. Here MPUI 1. ROMI 2. The RAM 13 and the serial interface 14 constitute a data processing means 23 that sends serial data to be transmitted to the ID unit 2 and receives and processes serial data obtained from the ID unit 2.

Next, FIG. 3 is a circuit diagram showing the detailed configuration of the LC oscillator 19 of the head section 5. As shown in FIG. As shown in the figure, the LC oscillator 19 includes a transistor Tri, an oscillation coil L1, and a capacitor C.
An oscillator to which a resonant circuit consisting of I and C2 is connected, and a transistor Tr2 is further connected in parallel to the transistor Tri.
and a capacitor C3 and a resistor R between its collector and base.
1 is connected, and a resistor R is connected to the emitter of the transistor Tr2.
3 is connected. A voltage control signal from the low-pass filter 20 described above is applied to the base of the transistor Tr2, and the oscillation frequency of the LC oscillator 19 is changed by the voltage.

(Configuration of ID unit) As shown in Fig. 4, the ID unit 2 is a resonant circuit including a coil, for example, an LC consisting of a coil L3 and a capacitor C4.
It has a resonant circuit 31. The LC resonance circuit 31 is configured such that its oscillation frequency can be varied by, for example, connecting and connecting a capacitor C5, and one end of the circuit is provided to a level converter 32 and a rectifier/smoothing circuit 33.

The level converter 32 converts the DC level of the high frequency signal obtained from the LC resonance circuit 31, and its output is given to the PLL circuit 34. The PLL circuit 34 performs frequency shift keying (
The FSX modulated signal is demodulated and converted into the original serial digital signal. The output of the PLL circuit 34 is given to a memory control section 37 via a low-pass filter 35 and an amplifier 36. Connected to the memory control section 37 are a memory 38 and a frequency divider 39, which are, for example, a programmable read-only memory (hereinafter referred to as EEPROM) which is an electrically writable and erasable memory. Frequency divider 39 is LC
A clock signal is given to the memory control section 37 by frequency-dividing a high frequency signal obtained from the resonant circuit 31 via the level converter 32. The memory control unit 37 converts the serial digital signal obtained from the amplifier 36 into a parallel signal, determines the command included in the data, and controls writing of data to the memory 38 and reading of data from the memory 38. . Further, the output of the level converter 32 is applied to an encoding circuit 40 via a frequency divider 39.

Furthermore, data read out from the memory control section 37 is also provided to the encoding circuit 40. The encoding circuit 40 uses this NRZ
It bi-phase encodes the serial digital signal of
is given as a control signal that changes the resonant frequency of.

Here, the PLL circuit 34. The low-pass filter 35 and the amplifier 36 constitute a data demodulating means 41 that demodulates a high frequency signal applied from the head section 5 of the write/read control unit 3.

FIG. 5 shows the LC resonant circuit 31 and level converter 32 in the ID unit 2. 3 is a circuit diagram showing a detailed configuration of a rectification/smoothing circuit 33. FIG. As shown in the figure, the LC resonance circuit 31 includes coil L2. A capacitor C5 is further connected in parallel to the parallel circuit of the capacitor C4 and the switching transistor Tr3.
It is connected via a Zener diode Dl. A rectifier/smoothing circuit 33 having a resistor R3, a diode D2, and a capacitor C6 is connected to the LC resonant circuit 31, and its output is supplied to each part of the 10 units 2 as a power source. Further, a level converter 32 consisting of a resistor R4, a diode D3, and a Zener diode D4 is connected to the resistor R3.
The DC level of the output signal of the C resonance circuit 31 is converted to P
The signal is applied to the LL circuit 34. The aforementioned encoding circuit 40 drives the switching transistor Tr3, and discontinuously changes the resonant frequency by switching on/off the transistor Tr3, which connects the capacitor C5 in parallel at high frequency.

(Configuration of Memory Control Unit) FIG. 6 is a block diagram showing the detailed configuration of the memory control unit 37. In this figure, the memory control unit 37 is an amplifier 36
S to convert the serial digital signal obtained from
It has a /P converter 51 and a command decoder 52 that decodes commands of parallel signals output from the converter 51. S
A serial manual control section 53 is connected to the /P converter 51. The serial input control section 53 converts the applied serial signal into parallel data at a necessary time by applying a clock signal to the S/P converter 51 at a predetermined timing. The command decoder 52 includes a command register 52a that temporarily holds commands given from the write/read control unit 3, an address register 52b that temporarily holds addresses, a data register 52c that temporarily holds data, and the number of bytes of successive data. A byte number counter 52d is provided. The command decoder 52 includes a status control section 54 that controls execution of commands. A memory control circuit 55 is connected, and an address generation circuit 57 is further connected via an address bus 56. The status control section 54 controls each block to execute the contents of command data based on the clock signal given from the frequency divider 39. Further, the memory control circuit 55 controls the writing/reading of data in the memory 38, that is, the EEPROM, based on the write and continuation signals from the status control section 54. Also command decoder 5
The output of the second data register 52c is given to the memory 38 via the data bus 58. A data buffer 59 that temporarily holds data read from the memory 38 is connected to the data bus 58 . Address generation circuit 57
generates addresses sequentially based on the step signal given from the status control section 54 based on the address value from the address register 52b of the command decoder 52, and the address signal is given to the memory 38 and the status register 60. . The status register 60 is a register that holds transmission/reception commands, execution completion, and error information, and is arranged in a part of the same address space as the memory 38. Further, the parallel output of the data buffer 59 is connected to a P/S converter 61. Further, the status control section 54 is a sequential circuit that advances the control of each section when a predetermined condition is satisfied, and provides an output start signal to the serial output control section 62 when outputting data. The serial output control section 62 provides the P/S converter 61 with a clock signal corresponding to the timing of transmission, and also adds start and stop bits. The P/S converter 61 converts the data held in the data buffer into a serial signal when reading the data, adds a parity bit, start bit, and stop bit to the serial signal, and then converts the data held in the data buffer into a serial signal, and adds a parity bit, start bit, and stop bit to the encoder circuit 4 described above.
It is given to 0.

(Operation of Example) Next, the operation of this example will be explained with reference to waveform diagrams. FIGS. 7 to 9 are waveform diagrams showing waveforms at various parts of this embodiment. First, the I attached to the object 1 to be detected is
The D unit 2 is the head section 5 of the write/read control unit 3
When the coil L1 of the LC oscillator 19 of the write/read control unit 3 approaches, the LC resonant circuit 3 of the ID unit 2
A high frequency signal is transmitted to 1. Since the LC oscillator 19 continues to oscillate without interruption, the LC resonant circuit 3
The high frequency signal obtained in 1 is converted into a DC voltage by a rectifier/smoothing circuit 33, and power is supplied to each block of the ID unit 2. Therefore, the ID unit 2 starts operating and becomes ready for data transmission with the write/read control unit 3. Now, when writing data from the write/read control unit 3, a write command and write data are given to the serial interface 14 from the MPU II. The serial interface 14 is shown in FIG.
), the signal from the MPUII is converted into a serial signal and transmitted to the voltage controlled oscillator 17. Voltage controlled oscillator 17
provides the phase comparator 18 with a signal having a frequency corresponding to the given NRZ transmission signal as shown in FIG. 7(b).

On the other hand, since the output of the LC oscillator 19 is transmitted to the low-pass filter 20, the output of the low-pass filter 20 is as shown in FIG.
As shown in C1, the control signal changes in response to the NRZ signal.

Therefore, as shown in FIG. 7+d+, the LC oscillator 19 changes to have the same frequency as the voltage controlled oscillator 17, and continues to oscillate at a different frequency intermittently.
SK modulation is performed. This FSK modulated output is the ID
Since the signal is transmitted to the LC resonant circuit 31 of the unit 2, the same signal as that of the LC oscillator 19 is obtained from the LC resonant circuit 31.

This output is then transmitted to the PLL circuit 34 via the level converter 32 and demodulated. and low pass filter 3
5, the signal from which high frequency components have been removed is transmitted from the amplifier 36 to the memory control section 37 as a serial signal. Therefore, read or write commands and data for the memory 38 from the write/read control unit 3 are transmitted to the memory control section 37, and the memory 38 is controlled based on this.

As shown in Figure 8 (a), the serial NRZ signal read out from the memory control unit 37 is transmitted to the encoding circuit 4°. The encoding circuit 40 converts the applied NRZ signal into a biphase code as shown in FIG. 8(b) by performing an exclusive OR with the clock signal.
The resonance frequency of the LC resonance circuit 31 is changed by turning on and off the transistor Tr3. Since this change in the resonance frequency results in a change in the load on the LC oscillator 19 of the write/read control unit 3, its oscillation frequency tends to change. Since a phase control loop is formed in the head section of the write/read control unit 3, the oscillation frequency of the LC oscillator 19 does not change as shown in FIG. 8(C).
Continues oscillation at the same oscillation frequency. However, at that time, the phase changes slightly and the control output of the low-pass filter 20 becomes as shown in FIG. 8(d). The output of this low-pass filter 20 serves as a signal directly transmitted from the ID unit 2 to the write/read control unit 3. Therefore, by extracting the pie-phased clock signal and a signal having a frequency of % of this control signal through the bypass filter 21, a transmission signal can be obtained as shown in FIG. 8(e). This signal is given to the decoding circuit 22. The decoding circuit 22 can obtain an NRZ signal as shown in FIG. 8 (fl) by extracting the clock from the biphase code and decoding it. This signal is then applied to the serial interface 14 and converted into a parallel signal. In this way, half-duplex data transmission can be performed between the write/read control unit 3 and the ID unit 2.

and write/read control unit 3 and I during data transmission.
If a metal object etc. is close to the D unit 2,
Although the frequency of the LC oscillator does not change, the equivalent impedance of its coil L1 changes, so the oscillation frequency tends to change. FIG. 9 is a waveform diagram showing waveforms of various parts of the write/read control unit when a metal body approaches, and shows the time axis enlarged from FIGS. 7 and 8. Time 1.
Previously, as shown in Fig. 9 (al), the oscillation frequencies of the LC oscillator 19 and the voltage controlled oscillator 17 were the same, as shown in Fig. 9 (bl, (C)) because the metal bodies were not close to each other. The phase difference is also constant at each point in time -4o, t+. At this time, the phase comparator 18 is )
As shown in FIG.
The output is at zero level.

After time tl, as shown in FIG. 9(a), if a metal object approaches, the equivalent impedance of the coil L1 of the LC oscillator 19 changes. Therefore, the oscillation frequency changes to become high, but since there is a phase control loop in the write/read control unit 3, the frequency does not change as shown in FIG. 9(b), (C1) and the phase difference Only the time difference and the phase difference at t3 will change as θh + θt.
, then θj,>θ1. >θt, holds true. Therefore, the output of the phase comparator 21 has a large positive portion as shown in FIG.
7 oscillation frequencies match. In this way, when the metal bodies come close to each other, the DC level of the low-pass filter 20 changes, but the oscillation frequency itself does not change and data transmission can be continued. Therefore, the PLL circuit 34 of ID unit 2
The DC level of the output does not change even if a metal object approaches. Therefore, from write/read control uni-node 3 to ID
When transmitting a signal to the unit 2 side, there is no need to encode it using a transmission code that does not have a DC component, and there is no need to provide a demodulation circuit in the ID unit 2 (the circuit configuration can be simplified). On the other hand, since the signal given from the ID unit 2 to the write/read control unit 3 is encoded by a transmission code that does not have a DC component, only the DC component changes when a metal object approaches.Therefore, the bandpass filter By extracting only the signal component encoded through the 21 and decoding it, it is possible to continue data transmission without the influence of the metal body.

In this embodiment, a pi-phase code is used as a transmission code that does not have a DC component, but it goes without saying that various other codes such as an f/2f code, a bipolar code, and a dicode code can be used. do not have.

In addition, in this embodiment, electrically erasable EEFR is used as a memory.
OM, but with a variety of electrically writable and erasable memories, e.g. 0 backed up by a battery.
It is also possible to use MO3 type memory.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a write/read control unit of an article identification system according to an embodiment of the present invention, FIG. 2 is a block diagram showing the overall configuration of this embodiment, and FIG. 3 is a write/read control unit. 4 is a block diagram showing the structure of the ID unit. FIG. 5 is a circuit diagram showing the structure of the LC resonant circuit and level converter in the ID unit. FIG. 6 is a block diagram showing the detailed configuration of the memory control unit, and FIG. 7 is a waveform diagram showing waveforms of each part when data is transmitted from the write/read control unit to the ID unit in the article identification system of this embodiment. , Fig. 8 is a waveform diagram showing the waveforms of each part when data is transmitted from the ID unit to the write/read control unit, and Fig. 9 shows the waveforms of each part of the write/read control unit when a metal object is nearby. FIG. 1--- Goods 2-1-- ID unit
3--...-Write/read control unit 4--
-Writing/reading control device main body 5--Head section 1
1-...-MPU14---Serial interface 17---Voltage controlled oscillator 18-
・-Phase comparator 19・・・・・−・LCH5iH2
0--Low pass filter 21--Band pass filter 22--I encoding circuit 23
・−・・−・−Data processing means 31・−・・−LC
Resonant circuit 33--- Rectifier/smoothing circuit 37
−・−・・Memory control unit 38−・−・−Memory
40--Encoding circuit 41---1--Data demodulation means Patent applicant Tateishi Electric Co., Ltd. agent Patent attorney Yoshiki Okamoto (and one other person) 52 Figure 3--4 included/trap Figure 5 Figure 7 (d) 1 plate between L1 and 3 plates

Claims (1)

[Claims] (1) An article identification system comprising an ID unit attached to an article to be identified, and a write/read control unit that writes data to and reads data from the ID unit, the ID unit comprising: a resonant circuit including a coil; a data demodulator for demodulating a signal based on the frequency of the output obtained from the resonant circuit; a memory for storing identification data of an article to which the ID unit is attached; a memory control means for controlling writing of data to and reading of data from the memory; and a rectifier for supplying DC power to each part of the ID unit by rectifying and smoothing the output obtained from the resonant circuit.
a smoothing circuit; and an encoding circuit that encodes the transmission data read from the memory control means using a transmission code having no DC component to change the resonant frequency of the resonant circuit; /The readout control unit includes an oscillator that includes an oscillation coil and changes its oscillation frequency based on a signal applied from the outside, and a voltage-controlled oscillator that receives data to be sent as a control signal and oscillates at the same frequency as the oscillator. , a phase comparator that is provided with the outputs of the voltage controlled oscillator and the oscillator and compares their phases; and a low-pass device that supplies a signal with a frequency of a predetermined frequency or less of the phase comparison output of the phase comparator to the oscillator as a frequency control signal. a filter, a control signal for the low-pass filter is provided, and the ID
a bandpass filter having a passband corresponding to the frequency of the encoded data of the unit; a decoding circuit that is given the output of the bandpass filter and decodes the code of the encoded data sent out from the ID unit; An article identification device comprising: data processing means for providing serial data to be sent to the voltage controlled oscillator and converting data provided by the data decoding circuit into parallel signals for processing. system.