JP2560660B2 - Item identification system - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates to a tool for a machine tool, an article identification system used in a factory, article management, product management or physical distribution system, and the like.

[Prior art and its problems]

(Prior Art) Conventionally, in order to mechanize the management of tools of machine tools and the identification of parts and products in an assembly and conveyance line in a factory, a system for identifying and managing various articles such as tools, parts, and products is used. Will be needed. As a conventional management system like this, a method of sticking a label such as a bar code to a detection target to manage it, or attaching a magnet group that represents data in binary to an identification target and inverting the polarity of a predetermined magnet from the outside There is known a management system that retains data by making it. However, such a management system has problems that it takes time to rewrite data and the reliability of data is low and the amount of information that can be held is small. Therefore, there is also proposed an article identification system in which a memory is provided for an object to be identified and necessary information is written in such a memory by contact type or baseband data transmission, and the information is read out as needed. ing.

(Problems to be Solved by the Invention) However, according to such a conventional identification system, there are drawbacks that management is troublesome and impact resistance and vibration resistance are poor. Further, in the conventional identification system, a predetermined code is sent from the main body side and it is determined whether or not a position where data transmission with a memory unit attached to an article is possible is reached based on the presence or absence of a response thereto. Such a determination is not easy and takes a long time.

In addition, contact and non-contact systems can be considered as data transmission methods. However, in the case of the contact method, it is necessary to perform accurate alignment, and the problem of contact failure at the contact points tends to occur, ensuring reliable data There was a problem that it could not be written.

[Object of the Invention]

The present invention has been made in view of the above-mentioned problems of the conventional article identification system, and sends a status code indicating that data transmission is possible when the memory units are close to each other as well as the data transmission. It is a technical subject to perform non-contact data transmission by simultaneously performing signal transmission and improve its reliability.

[Constitution and effect of the invention]

(Means for Solving Problems) The present invention is an article identification including an ID unit attached to an article to be identified, and a writing / reading control unit for writing data to and reading data from the ID unit. In the system, as shown in FIGS. 1, 2 and 4, the ID unit includes a coil that shares the functions of power transmission and data transmission, and can be connected to the write / read control unit without contact. Data transmission means for performing data transmission in an appropriate direction, a memory for storing identification data of an article to which the ID unit is attached, and a write / read control command provided by the write / read control unit for decoding the data to the memory. DC power is supplied to each part of the ID unit by rectifying and smoothing the output obtained in the coil of the data transmission means and the memory control means for controlling writing and reading of data. A flow / smoothing circuit and a status code sending means for giving a read signal of a predetermined status code to the memory control means when the output of the rectifying / smoothing circuit is given and the data can be transmitted and received. And write /
The read control unit includes a coil that shares the functions of power transmission and data transmission, data transmission means for performing two-way data transmission in a contactless manner with the ID unit, and transmission when a predetermined status code is received from the ID unit. Data processing means for supplying serial data to be output to the data transmission means and for converting the data supplied from the data transmission means into a parallel signal.

(Operation) According to the present invention having such characteristics, the ID unit is attached to the article to be identified. The data transmission means of the writing / reading control unit continuously transmits electric power, and by rectifying and smoothing the AC power obtained in the coil when the ID unit reaches a predetermined position, the data is transmitted to each part of the ID unit. DC power is supplied. Then, the ID unit sends a status code indicating that transmission / reception is possible to the writing / reading control unit when the DC power supply reaches a predetermined level, whereby data transmission is started. At the time of data transmission, the ID unit identifies the signal given from the write / read control unit and writes the necessary data in the memory, or reads the necessary data from a predetermined address of the memory and gives it to the write / read control unit side. .

(Effect of the invention) As described above, according to the present invention, since the electric power is supplied to the ID unit by utilizing the electromagnetic coupling, the ID unit can be contactlessly written / read with the ID unit without requiring a DC power source. Half-duplex data transmission between control units is possible. The ID unit also sends a status code when the data transmission can be started. Therefore, it is possible to immediately start the data transmission with the unit without sending a special code from the writing / reading control unit to confirm the propriety of the data transmission.

[Explanation of Example]

FIG. 1 is a block diagram showing the structure of an article identification system according to an embodiment of the present invention. In this figure, the article identification system is an article 1 such as a tool, a part, or a product to be identified.
It has an ID unit 2 directly attached to and a writing / reading control unit 3 for writing and reading data to and from the ID unit 2. The writing / reading control unit 3 is provided at a position close to the writing / reading control device main body 4 and the ID unit 2,
The head unit 5 is for writing and reading data to and from the ID unit 2. The ID unit 2 and the writing / reading control unit 3 constitute an article identification system.
The writing / reading control unit 3 is connected to, for example, a higher-level control device 6, and is configured to write and read data to / from the ID unit 2 from the higher-level control device 6 via the writing / reading control unit 3. There is.

(Structure of Writing / Reading Control Unit) As shown in the detailed block diagram of FIG. 2, the writing / reading control unit 3 controls the writing and reading of data to and from the ID unit 2 by a microprocessor (MPU). 11 and a read-only memory (ROM) 12 that stores the system program, a random access memory (RAM) 13 that temporarily holds data, and a serial interface 14 that performs serial data transmission with the ID unit 2 and a host controller It has an external interface 15 and a display section 16 for interfacing with 6. The MPU 11 sends data and commands to the ID unit 2 via the serial interface 14 according to a predetermined processing program, and the digital data is given to the encoding circuit 17 as an NRZ serial signal. The encoding circuit 17 is for converting a serial signal into a bi-phase signal, is composed of an exclusive OR circuit, and its output is given to the LC oscillator 18 of the head unit 5 as a control signal.
The LC oscillator 18 is an oscillator that continuously oscillates and changes its oscillation frequency according to a control signal from the encoding circuit 17. The LC oscillator 18 transmits the signal to the ID unit 2 through the oscillation coil L1 and outputs its oscillation output. Divider 19 and PLL circuit 20
Give to. The frequency divider 19 applies a clock signal to the encoding circuit 17 and the serial interface 14 by shaping the frequency of the output of the LC oscillator 18 and dividing the output. Also PL
The L circuit 20 is a well-known phase-locked loop circuit.
A signal is received from the ID unit 2 by detecting a change in the oscillation frequency when the resonance circuit of the ID unit 2 is close to the C oscillator 18 and the loads thereof are different. PLL
The output of the circuit 20 is given to an amplifier 22 that amplifies an AC component via a low pass filter 21. The output of the amplifier 22 is given to the decoding circuit 23. Since the signal from the ID unit 2 is bi-phase encoded as described later,
The decoding circuit 23 converts the bi-phase code obtained from the amplifier 22 into an NRZ serial signal. That is, the decoding circuit 23 is composed of a clock extraction unit 23a that extracts a clock and a decoding unit 23b that is an exclusive OR circuit (hereinafter referred to as an EOR circuit) that inputs the clock signal and a biphase code, and the input biphase code. Is converted into an NRZ code and its output is given to the MPU 11 via the serial interface 14. Where MPU11, ROM12, R
The AM 13 and the serial interface 14 constitute a data processing means 24 which sends out serial data to be transmitted to the ID unit 2 and receives and processes the serial data obtained from the ID unit, and includes an encoding circuit 17 and an LC oscillator 18. The frequency divider 19, the PLL circuit 20, the low-pass filter 21, the amplifier 22 and the decoding circuit 23 constitute a data transmission means 25 for transmitting electric power and bidirectionally transmitting data.

Next, FIG. 3 is a circuit diagram showing a detailed configuration of the LC oscillator 18 of the head unit 5. As shown in this figure, the LC oscillator 18 is an oscillator in which a resonance circuit composed of an oscillation coil L1 and capacitors C1 and C2 is connected to a transistor Tr1, and a transistor Tr2 and a coil L2 are further connected in parallel to the LC resonance circuit. There is. A transistor Tr3 controlled by the encoding circuit 17 is connected to the base of the transistor Tr2. Since the coil L2 of the switching transistors Tr2 and Tr3 is opened and closed to connect the coil L2 in parallel to the resonance circuit, the oscillation frequency can be intermittently changed. A frequency divider 19 and a PLL circuit 20 are connected to the hot end side of the coil L2 via a capacitor C3.

(Structure of ID Unit) As shown in FIG. 4, the ID unit 2 has a resonance circuit including a coil, for example, an LC resonance circuit 31 including a coil L3 and a capacitor C4. The LC resonance circuit 31 is, for example, a capacitor C5.
The oscillating frequency can be made different by connecting and disconnecting, and one end thereof is given to the level converter 32 and the rectifying / smoothing circuit 33. The level converter 32 converts the DC level of the high frequency signal obtained from the LC resonance circuit 31, and its output is given to the PLL circuit 34. The PLL circuit 34 demodulates the frequency-shift keyed (FSK-modulated) signal supplied from the level converter 32 to the original serial digital signal (bi-phase encoded signal).
Is to be converted to. The output of the PLL circuit 34 is given to the amplifier 36 via the low-pass filter 35. The output of the amplifier 36 is given to the decoding circuit 37. Decoding circuit 37 is an amplifier
It has a clock extraction unit 37a for extracting a clock from the output of 36 and a decoding unit 37b composed of an exclusive OR circuit, and converts a biphase-encoded digital signal into an original NRZ digital signal. . Then, this NRZ digital serial signal is given to the memory control unit 38. The memory control unit 38 is connected to a memory 39, which is a programmable read-only memory (hereinafter referred to as EEPROM), which is a non-volatile memory that can be electrically written and erased, and a frequency divider 40. The frequency divider 40 provides a clock signal to the memory control unit 38 by dividing the high frequency signal obtained from the LC resonance circuit 31 via the level converter 32.
The memory control unit 38 converts the serial digital signal obtained from the decoding circuit 37 into a parallel signal, determines the command included in the data, writes the data to the memory 39,
It controls the reading of data from the. The data and clock signal read from the memory control unit 38 are given to the encoding circuit 41. The encoding circuit 41 is for bi-phase encoding the NRZ serial digital signal, and is an EOR that takes the exclusive OR of the clock signal and the NRZ signal.
It is composed of a circuit and is given as a control signal for changing the resonance frequency of the LC resonance circuit 31. Here, the LC resonance circuit 31, the PLL circuit 34, the low-pass filter 35, the amplifier 36, the decoding circuit 37 and the encoding circuit 41 are data transmission means for demodulating a high frequency signal given from the head section 5 of the write / read control unit 3. 42 make up. The power supply output of the rectifying / smoothing circuit 33 is also given to the level discriminating circuit 43. The level discriminating circuit 43 is a status code transmitting means for discriminating whether or not the power supply voltage of the rectifying / smoothing circuit 33 has reached a predetermined level to enable data transmission with the write / read control unit 3 and for transmitting a status code. Consists of a Zener diode and a Schmitt trigger circuit,
When the power supply voltage is equal to or higher than a predetermined value, data transmission becomes possible, so the detection signal is given to the memory control unit 38.

FIG. 5 is a circuit diagram showing a detailed configuration of the LC resonance circuit 31, the level converter 32, and the rectifying / smoothing circuit 33 in the ID unit 2. As shown in this figure, the LC resonance circuit 31 is connected to a parallel circuit of a coil L3 and a capacitor C4, and a capacitor C5 is connected in parallel via a switching transistor Tr4 and a Zener diode D1. A rectifying / smoothing circuit 33 having a resistor R1, a diode D2 and a capacitor C6 is connected to the LC resonance circuit 31, and its output is supplied to each unit of the ID unit as a power source. A level converter 32 composed of a resistor R2, a diode D3 and a zener diode D4 is connected to the resistor R1, and the DC level of the output signal of the LC resonance circuit 31 is converted to the PLL circuit 34.
Given to. The above-mentioned encoding circuit 41 drives the switching transistor Tr4, and changes the resonance frequency discontinuously by intermittently connecting the transistor Tr4 in which the capacitor C5 is connected in parallel at high frequency.

(Structure of Memory Control Unit) FIG. 6 is a block diagram showing the detailed structure of the memory control unit 38. In the figure, the memory control unit 38 is a decoding circuit 37.
S / which converts the serial digital signal obtained from this into a parallel signal
It has a P converter 51 and a command decoder 52 which decodes a command of a parallel signal which is an output thereof. A serial input control unit 53 is connected to the S / P converter 51. The serial input control unit 53 sends the clock signal to the S / P at a predetermined timing.
The serial signal given at a required time is converted into parallel data by giving it to the converter 51. A command register 52 for temporarily holding a command given from the write / read control unit 3 is provided in the command decoder 52.
a, an address register 52b for temporarily holding an address, a data register 52c for temporarily holding data, and a byte number counter 52d for holding the number of bytes of read data are provided. The command decoder 52 is connected to a status control unit 54 and a memory control circuit 55 for controlling command execution, and further connected to an address generation circuit 57 via an address bus 56. The status control unit 54 controls each block to execute the given coil based on the clock signal given from the frequency divider 40, and also the level discrimination circuit.
Based on the output from 43, each part is controlled so as to send a transmission start status signal s as described later. The memory control circuit 55 controls the writing / reading of the data of the memory 39 based on the writing / reading signal of the status controller 54. The output of the data register 52c of the command decoder 52 is given to the memory 39 via the data bus 58. A data buffer 59 for temporarily holding the data read from the memory 39 is connected to the data bus 58. The address generation circuit 57 is for sequentially generating addresses based on the step signal given by the status control unit 54 based on the address value from the address register 52b of the command decoder 52, and the address signal is the memory 39.
Is given to the status register 60. The status register 60 is a register for holding a command of transmission / reception, execution completion and error information, and is arranged in a part of the same address space as the memory 39. The parallel output of the data buffer 59 is connected to the P / S converter 61.
The status control unit 54 is a sequential circuit that advances the control of each unit when a predetermined condition is satisfied, and gives an output start signal to the serial output control unit 62 when outputting data.
The serial output control unit 62 gives the P / S converter 61 a clock signal corresponding to the transmission timing,
A stop bit is added. The P / S converter 61 converts the data held in the data buffer at the time of reading the data into a serial signal, adds a parity bit and a start bit and a stop bit, and gives the serial signal to the above-mentioned encoding circuit 41.

(Operation of Embodiment) Next, the operation of this embodiment will be described with reference to the flowchart of FIG. 7 and the time chart of FIG. First, when the ID unit 2 attached to the article 1 to be detected approaches the head portion 5 of the writing / reading control unit 3,
From coil L1 of LC oscillator 18 of write / read control unit 3
A high frequency signal is transmitted to the LC resonance circuit 31 of the ID unit 2. LC
Since the oscillator 18 continues to oscillate without interruption,
The high frequency signal obtained by the LC resonance circuit 31 is rectified and smoothed by the rectification / smoothing circuit 33.
Is converted into a DC voltage by the power supply, and power is supplied to the input terminal of the level discrimination circuit 43 and each block of the ID unit 2.
The level discrimination circuit 43 outputs a detection signal to the status control unit 54 of the memory control unit 38 when this level becomes equal to or higher than a predetermined level. Then, the status code stored in the memory 39 in advance is given to the status register 60, and in step 71, the preamble is added as shown in FIG. 8 (a) to obtain the status code a including the data transmission start status s. Sent out. The ID unit 2 thereafter enters a standby state waiting for a command from the write / read control unit 3. The writing / reading control unit 3 is the ID unit 3
When it is necessary to read more data, as shown in FIG. 8, a read command b consisting of a read code, a leading address from which the data of the ID unit 2 is to be read, and the number of read bytes is sent after the preamble. This command b
FS by changing the oscillation frequency of the LC oscillator 18 via the serial interface 14 and the encoding circuit 17.
K modulated and transmitted to the ID unit 2 side. Then, in the ID unit 2, the same signal is obtained from the LC resonance circuit 31, and this signal is transmitted to the PLL circuit 34 via the level converter 32 and demodulated. Then, the signal is decoded through the decoding circuit 37 and this signal is transmitted to the memory control unit 38. The memory control unit 38 converts the serial signal into a parallel signal and outputs the first command of the given command.
Connect the byte to command register 52a (step 7
3) If there is no reception error, decode the command and determine either the read code, the write code, or the communication test code. If it is a lead code, step 75
In step 76, the second byte is held in the address register 52b, and if there is no reception error, the third byte is held in the byte number counter 52d to check whether there is a reception error. If there is no reception error, the status information of the status register 60 including the code executed and the error information at that time is given to the data buffer 59 and converted into a serial signal to change the resonance frequency of the resonance circuit 31 to write / write. It is sent to the read control unit 3 side (step 81).
Then, the process proceeds to steps 82a to 82c to set the memory control circuit 55 in the read mode, generate the address given by the address generation circuit 57, and transfer the data obtained from the memory 39 at that time to the data buffer 59. And step
Proceeding to 83, the contents of the data buffer 59 are similarly transmitted. Then, in step 84, the byte number counter 52d is decremented and the address of the address generating circuit 57 is incremented to check whether the byte number counter 52d becomes 0 (steps 84, 85). If this is not 0, return to step 82 and repeat the same processing.
The necessary data 1 to 4 are sequentially transmitted as shown in the response c from the ID unit 2 in FIG. When the byte counter reaches 0, the process returns from step 85 to 71 and the same process is repeated.

Here, it is assumed that the response c in FIG. 8 is composed of 1-byte data 1 to 4 by adding a start bit, a parity bit and a stop bit, respectively, and shows an example in which these data are transmitted, for example, 4 bytes.

Then, as shown in FIG. 8, the write / read control unit 3
If the write command d is sent from the ID unit 2, the ID unit 2 similarly holds the first byte in the command register 52a in step 71, and if there is no reception error, decodes the command in step 75. If it is a write code, the process proceeds to step 86, the second byte is held in the address register 52b, and if there is no reception error, the third byte is set in the data register 52c (step 8).
7,88). And if there is no reception error, steps 90a, 90b,
In 90c, the memory control circuit 55 is set to the write mode, and the address generation circuit 57 generates an address. Then, the data held in the data register 52c is transferred to the memory 39. Then, the process proceeds to step 91, where the presence or absence of the error information executed at that time is set in the status register 60, and the process proceeds to step 92 where the contents of the status register are sent out via the data buffer. Meanwhile steps 74, 77, 79
Alternatively, if there is a reception error at 87 or 89, each processing is stopped and the process proceeds to step 93 to set error information in the status register 60. Then, in step 92, the data in the register is sent out via the data buffer 59, and the process ends. By doing so, the execution contents of the command can be transmitted to the write / read control unit 3 side.

As described above, according to the present embodiment, the data transmission can be performed immediately when the ID units 2 come close to each other and the data transmission becomes possible. Further, even when a large-capacity memory is used as the memory of the ID unit, any address of the memory can be freely accessed, and the efficiency of data transmission can be greatly improved.

Here, communication is possible when the distance between the coil L3 of the ID unit 2 and the coil L1 of the write / read control unit 3 is within a certain range. Here, it is assumed that one frame consisting of one byte of data is composed of 11 bits including a start bit, a parity bit, and a stop bit, and the preamble and status shown in FIG. 8 are one frame each, the command code and the number of bytes. If one frame is included in total, it takes 11 frames for mutual data transmission of a to c in FIG. And the data transmission rate is 1200 bps
If so, communication time of 100 msec including status transmission indicating that data can be transmitted is required. Therefore, when the moving speed of the ID unit 2 is 0.2 m / sec or less, as shown in FIG.
Bytes can be read.

In this embodiment, in order to transmit data from the write / read control unit 3 to the ID unit 2, the NRZ signal is once converted into a biphase code, and the signal is transmitted from the ID unit 2 to the write / read control unit 3. In the same way, the NRZ signal is converted into the bi-phase code and read out in the same manner, but other transmission codes may be used, or FSK modulation can be performed directly using the NRZ signal without performing such code conversion. You may go. Alternatively, the data may be transmitted by the base band method without performing FSK modulation.

Further, in this embodiment, an electrically erasable EEPROM is used as a memory.
Various memories that use OM but are electrically writable and erasable, eg CMOS backed up by a battery
It is also possible to use type memory.

[Brief description of drawings]

FIG. 1 is a block diagram showing the overall construction of an article identification system according to an embodiment of the present invention, FIG. 2 is a block diagram showing the construction of a write / read control unit of this embodiment, and FIG. Circuit diagram showing the configuration of the LC oscillator 18 of the read control device,
FIG. 6 is a block diagram showing the configuration of the ID unit, FIG. 5 is a circuit diagram showing the configuration of the LC resonance circuit and level converter in the ID unit, and FIG. 6 is a block diagram showing the detailed configuration of the memory control unit. FIG. 7 is a flowchart showing the operation of the ID unit according to this embodiment, and FIG. 8 is a write / read control unit and ID.
It is a time chart which shows the state of half-duplex data transmission between units. 1 ... Article, 2 ... ID unit, 3 ... Write / read control unit, 4 ... Write / read control device main body, 5 ... Head part, 11 ... MPU, 14 ... Serial interface, 1
7,41 ... Encoding circuit, 18 ... LC oscillator, 20,34 ... PLL circuit, 21,35 ... LPF, 23,37 ... Decoding circuit, 24 ... Data processing means, 25,42 ... … Data demodulator, 31 …… LC resonance circuit, 33 …… Rectification / smoothing circuit, 38 …… Memory controller, 39
...... Memory, 43 ...... Level discrimination circuit (status code sending means)

Continuation of the front page (56) Reference JP-A-60-171475 (JP, A) JP-A-59-27278 (JP, A) JP-A-59-63582 (JP, A) JP-A-58-212680 (JP , A) JP-A-55-126874 (JP, A)

Claims (1)

(57) [Claims] 1. An article identification system, comprising: an ID unit attached to an article to be identified; and a write / read control unit for writing data to and reading data from the ID unit. Includes a coil that shares the functions of power transmission and data transmission,
Data transmission means for performing two-way data transmission in a non-contact manner with the writing / reading control unit, a memory for storing identification data of an article to which the ID unit is attached, and writing provided by the writing / reading control unit / Memory control means for decoding the read control command to control writing of data to the memory and reading of data, and DC for each part of the ID unit by rectifying and smoothing the output obtained in the coil of the data transmitting means. A rectifying / smoothing circuit for supplying power, and a status code for giving a read signal of a predetermined status code to the memory control means when the output of the rectifying / smoothing circuit is given and the data can be transmitted and received. Sending means, wherein the write / read control unit shares the functions of power transmission and data transmission. Including
Data transmission means for performing two-way data transmission in a non-contact manner with the ID unit, and providing the data transmission means with serial data to be transmitted when the predetermined status code is received from the ID unit, and the data transmission And a data processing means for converting the data given by the means into a parallel signal, the article identification system.