JPH0454751A - Commodity identification system - Google Patents

Abstract

PURPOSE:To attain high speed data transmission by generating a clock signal synchronously with a Manchester signal in a data carrier and decoding an original transmission data signal thereby. CONSTITUTION:A data to be sent is inputted from a CPU 21 to an S/P converter 23 at data transmission and an NRZ signal is inputted to a coding circuit 25. The coding circuit 25 converts the signal into a Manchester signal and gives the signal to a transmission section 26. A signal ASK-modulated is obtained at a reception section 41, which outputs a Manchester signal MANI. A decoding signal 43 receives the signal MANI and a clock signal CLK from a Manchester signal synchronizing circuit 44 simultaneously and a SYNC signal is outputted from a coincidence circuit 62 when a signal string is coincident with a predetermined specified value. A D flip-flop 65 latches an input signal by using a clock signal CLIF to obtain an NRZ signal.

Description

DETAILED DESCRIPTION OF THE INVENTION C. Industrial Application Field The present invention relates to an article identification system used in parts and product management in factories, logistics systems, and the like.

[Conventional technology]

In order to mechanize the tool management of conventional machine tools and the identification of parts and products on assembly lines in factories, tools 9 are required.
A system is required to identify and manage various items such as parts and products. Therefore, JP-A No. 63-229593,
As disclosed in Japanese Unexamined Patent Publication No. 1-151832, an ID unit (data carrier) having a memory is provided in the object to be identified, and the ID
The necessary information is written in such memory by data transmission from the read/write head of the controller.
An article identification system has been proposed in which the information is read out as needed.

[Problem to be solved by the invention]

However, in such conventional article identification systems, the data transmission rate between the data carrier and the ID controller is determined by the frequency of the carrier. If an attempt is made to increase the data transmission rate by changing the ratio between the carrier frequency and the transmission rate, the S/N ratio during signal transmission will decrease. Therefore, in order to increase the data transmission speed, it is necessary to increase the carrier clock frequency, but due to the magnetic permeability of the core, it is not possible to increase the carrier frequency to more than a few MHz, and it is not possible to perform high-speed data transmission. The drawback was that it was difficult.

The present invention has been made in view of the problems of the conventional article identification system, and its technical object is to enable high-speed data transmission.

[Means to solve the problem]

The present invention relates to a memory that holds data, a memory control means that controls writing and reading of data to the memory, and
It has a data transmission means that demodulates commands and data given from the outside and transmits the read data to the memory control means, and transmits the data to the data carrier attached to the article to be identified and sends out the data. a write/read control unit having a data transmission means for receiving the data transmitted, the data transmission means of the write/read control unit transmits the data signal to be transmitted at a predetermined frequency. It has an encoding circuit that converts the Manchester signal into a Manchester signal, and a transmitter that outputs an ASK modulation signal that intermittents a clock signal of a predetermined frequency in correspondence with the logic level of the Manchester signal obtained by the encoding circuit, and the data carrier. The data transmission means includes a receiving section that receives the transmitted ASK modulated signal, a demodulation circuit that identifies the Manchester signal from the ASK modulated signal among the received signals, and a synchronization system that detects the change point of the signal obtained from the demodulation circuit. A Manchester signal synchronization circuit that obtains a clock signal synchronized with the Manchester signal by multiplying the number by the Manchester signal; a decoding circuit that decodes the original signal from the Manchester signal and the clock signal output from the Manchester signal synchronization circuit; The apparatus is characterized in that it includes a reverberation control circuit that controls reverberation by reading out data to be transmitted based on a clock signal obtained by the signal synchronization circuit.

[Effect]

According to the present invention having such characteristics, the write/read control unit converts the data signal into a Manchester signal during data transmission, and transmits the data signal to the data carrier side by ASK modulation. In the data carrier, AS is determined by the receiving section.
By receiving the K modulated signal and demodulating the Manchester signal, and synchronizing at the time of change, a clock signal synchronized with the Manchester signal is generated inside the data carrier, and the original transmitted data signal is thereby decoded. ing.

〔Example〕

FIG. 2 is a block diagram showing the structure of an article identification system according to an embodiment of the present invention. In this figure, the article identification system includes a data carrier 3 that is directly attached to a pallet 12 on which parts to be identified are transported on a transport line 11, and a lead that is a data transmission means for writing and reading data on the data carrier 13. A write head 14 and an ID controller 15 connected to the read/write head 14 and controlling their operations are provided. The read/write head 14 and the ID controller 15 constitute a write/read control unit 6.

Now, read/write head 14 and ID controller 15
As shown in the block diagram in FIG. 3, each is provided with a microprocessor (CPU) 21 that controls writing and reading of data to and from the data carrier 13, and a memory 22 that holds its system program and data. It has an S/P converter 23 that converts the signal into a serial signal.

The S/P converter 23 supplies the parallel signal output from the CPU 21 to the read/write head 14 as a serial NRZ signal, and also provides the NRZ signal obtained from the read/write head 14.
It converts the Z signal into a parallel signal and provides it to the CPU 21. Also, the data transmission clock is read/write head 1.
Given by 4. A clock oscillator 24 is provided within the ID controller 15 to generate the clock.

Now, the read/write head 14 has an encoding circuit 25 that converts the NRZ signal into a Manchester signal, and the output thereof is given to the transmitter 26.

The transmitter 26 transmits a high-frequency signal to the data carrier 13 by ASK modulating the carrier at a predetermined frequency obtained from the clock generator 27 . Further, the receiving section 29 receives damped vibrations having the same carrier frequency as the carrier obtained from the data carrier 13, and the received signal is given to the demodulation circuit 30. The demodulation circuit 30 demodulates the signal transmitted from the data carrier 13 depending on the presence or absence of attenuation to obtain a Manchester signal, and its output is given to the decoding circuit 31. The decoding circuit 31 demodulates this signal into an NRZ signal using the clock set by the clock generator 27 and supplies it to the S/P converter 23 of the ID controller 15.

Next, the configuration of the data carrier 13 will be explained with reference to FIG. 4. In FIG. 4, the data carrier 13 has a receiving section 41 consisting of a resonant circuit that receives an ASK-modulated signal transmitted from the read/write head 14, and its output is given to a demodulating circuit 42. Demodulation circuit 4
2 demodulates the original Manchester signal from the obtained high frequency signal and supplies it to the decoding circuit 43 and the Manchester signal synchronization circuit 44. The Manchester signal synchronization circuit 44 generates a clock signal for synchronization from the Manchester signal, and its output is given to the decoding circuit 43. The decoding circuit 43 decodes the NRZ signal and extracts the data clock from the obtained Manchester signal and clock signal, and the NRZ signal and the clock signal are given to the memory control section 45. Memory control unit 45
controls the writing and reading of data into the memory 46, and the read signal is given to the encoding circuit 47 as an NRZ output signal. The encoding circuit 47 is NRZ
signal into a Manchester signal, the output of which is given to the reverberation control circuit 48. Reverberation control circuit 4
Reference numeral 8 controls the reverberation of the ASK signal obtained from the receiver 41 by logically multiplying the Manchester signal to be transmitted and the clock signal, thereby transmitting the signal to the read/write head 14 at the same carrier frequency.

Next, the demodulation circuit 42 of the data carrier 13. Decoding circuit 4
3 and the Manchester signal synchronization circuit 44 will be explained in detail with reference to FIG. As shown in FIG. 1, the demodulating circuit 42 includes a rectifying circuit 51 that rectifies the signal obtained from the receiving section 41, an integrating circuit 52 that integrates the output thereof, and a comparator 53 that discriminates the integrated output using a predetermined threshold value and obtains an envelope signal. The ASK modulated high frequency signal is demodulated to obtain the Manchester signal VAN.

This signal is applied to the falling edge detector 54 of the Manchester signal synchronization circuit 44. The fall detector 54 detects the fall of the input signal and supplies it to the counter 55 as a reset signal. Further, the Manchester signal synchronization circuit 44 has a reset signal generation circuit 56 connected to the rectification circuit 51, and the output thereof is used as an enable signal to the oscillator 5.
7 is given. The reset signal generation circuit 56 consists of, for example, a Zener diode and a voltage detection element, and the rectification circuit 51
It outputs a reset signal when the output reaches a certain level. Alternatively, a monostable multivibrator may be operated based on the output of the comparator 53 to output a reset signal.

Further, the oscillator 57 oscillates a high frequency signal of, for example, 2 MHz, and its output is given to the counter 55. The counter 55 is cleared in response to the falling edge detector 54 and provides the decoding circuit 43 with a clock signal CLK synchronized with the Manchester signal by dividing the input signal.

Now, the decoding circuit 43 has a shift register 61 that shifts this Manchester signal every clock, and its output is given to a matching circuit 62.

The matching circuit 62 determines whether the synchronization signal 5YNC matches the fixed value, and when there is a match, the RS flip-flop 6
A set input is given to 3. Also, the basic clock signal CL
K is applied to a % frequency divider circuit 64 consisting of a D flip-flop, and its Q output is applied to a D flip-flop 65. The frequency dividing circuit 64 is a frequency dividing circuit that starts operating after receiving the clear signal from the D flip-flop 63 and changes its state every time the basic clock signal rises. Signal CLI
F and is further provided to the memory control unit 45 as a clock signal. The D flip-flop 65 is a holding circuit that receives the Manchester signal demodulated by the demodulation circuit 42 at its D input terminal, starts operating after receiving the preset signal from the flip-flop 63, and converts the Manchester signal into an NRZ signal. be. This NRZ signal and data clock signal CLIF are given to the memory control section 45.

Next, the operation of this embodiment will be explained. When transmitting data, the data to be transmitted is sent from the CPU 21 to the S/P converter 23.
The NRZ signal is applied to the encoding circuit 25 as shown in FIG. 5(a)K.

The encoding circuit 25 converts this signal into a Manchester signal as shown in FIG. 5(b) and supplies it to the transmitter 26. It is assumed that the half pit of this Manchester signal uses the same frequency as the output of the counter 55. Therefore, the receiving section 41 of the data carrier 13 receives an ASK modulated signal as shown in FIG. 5(C). Then, it is received by the receiving section 41 of the data carrier 13 and demodulated by the demodulation circuit 42. In the demodulation circuit 42, as shown in FIG. 1, the signal is rectified by a rectifier circuit 51, then integrated by an integrating circuit 52, and a Manchester signal MAN1 as shown in FIG. 5(d) is obtained by a comparator 53.

Every time this signal falls, the Manchester signal synchronization circuit 44
The counter 55 is reset by the fall detector 54 of . Now, when the RAD 14 approaches the read/write area, an enable signal is applied from the reset signal generation circuit 56 to the oscillator 57, and oscillation is started. and counter 55
A reset signal is periodically applied from the fall detector 54 to . Therefore, as will be explained in detail later, the counter 55 outputs a lock signal CLK as shown in FIG. Since this signal is approximately synchronized with the Manchester signal MAN 1, the original signal can be demodulated based on these signals. That is, the decoding circuit 43 is the shift register 61
When the Manchester signal MAN 1 and the clock signal CLK generated by the Manchester signal synchronization circuit 44 are applied simultaneously to the synchronization circuit 44, and the signal train matches a predetermined value, the coincidence circuit 6 is applied as shown in FIG. 5 (80).
A 5YNC signal is output from 2. This signal sets the flip-flop 63 and outputs a signal as shown in FIG. 5(C). Further, the frequency of the basic clock is divided by the frequency dividing circuit 64 at each rising edge of the basic clock to obtain the data clock signal CLIF as shown in FIG. 5(i). By holding the input signal in the D flip-flop 65 using this signal, the same NRZ signal as shown in FIG. 5(a) can be obtained as shown in FIG. 5(U).

FIG. 6 is a diagram showing in detail the oscillation output of the oscillator 57, the Manchester signal, the counter clear pulse, and its frequency division state. As shown in FIGS. 6(b), (d), (e), and (f), the clock signal CLK is obtained from the counter 55 by dividing the reference clock of the oscillator 57. A reset signal having a constant time constant is applied to the counter 55 each time, and the counter 55 is reset at the rising edge of the next reference clock. In this way, the counter is shown in Figure 5(d).
As shown in (e), since the cycle is reset at least once every 4 half bits, it is possible to suppress the cycle deviation due to the slight difference in the oscillation frequency of both oscillators, and the transmitted Manchester signal and the generated Synchronization with lock CLK can be ensured.

The signal transmitted to the data carrier 13 in this way is decoded into a command by the memory control unit 45, and the transmitted data is held in the memory 46 or
Necessary data is read from. The read signal is converted into a Manchester signal via a decoding circuit 47, and the reverberation is controlled by a reverberation control circuit 48.

Figure 7 shows data carrier 13 to ID controller 5.
5 is a time chart showing an operation when transmitting data to the other side. In this figure, when transmitting data from the data carrier 13, the read/write head 14
), a signal with a duty ratio of 50% is generated at twice the frequency of the Manchester signal used during transmission and is applied to the data carrier 13 side. The receiving section 41 of the data carrier 13 receives this signal, and the demodulating circuit 42 causes the seventh
Extract a constant clock signal as shown in (turn).

Then, as shown in FIG. 7(C), the falling edge detector 54
A falling signal is applied to the counter 55, and the counter 55 outputs the clock signal CLK shown in FIG. 7(d). Therefore, the data clock signal CLIF is output from the decoding circuit 43 to the memory controller 4 as shown in FIG. 7(e).
5 continues to be given. Note that the CLIF signal is output until the data carrier 13 finishes sending the response signal. When the response transmission is completed, the memory control unit 45 outputs a TA times signal, the RS flip-flop 63 is reset, and the CLI
The F output is stopped, and the decoding circuit 43 enters the 5YNC input waiting state again. In synchronization with this, data to be transmitted by NRZ is successively transmitted as shown in Fig. 7).

This signal is converted into a Manchester signal M by an encoding circuit 47.
The signal is converted to ANO and output as shown in FIG. 7(6). The reverberation control circuit 48 uses the AND of the inverted output of the clock signal CLK and the Manchester signal to obtain the result shown in FIG.
A shunt pulse is output as shown in the figure, and the shunt pulse is sent to the receiver 4.
It is given to 1. Then, as shown in FIG. 7(a), when the shunt pulse is at the H level, the resonant circuit is short-circuited, so no reverberation occurs, whereas when the shunt pulse is at the L level, reverberation occurs. Therefore, read/write head 1
On the 4th side, data can be received by receiving this signal and demodulating the signal depending on the presence or absence of reverberation using a demodulation circuit.

In this embodiment, the Manchester signal synchronization circuit is constructed using an oscillator and a counter that divides the frequency of its oscillation output. A synchronized clock signal may be obtained by periodically resetting the monostable multi-by break to the stable multi-by break at the time of change of the Manchester signal.

〔Effect of the invention〕

According to the present invention having such characteristics, the data transmission speed can be determined regardless of the frequency of the carrier, so that data transmission can be performed at high speed. Therefore, a large amount of data can be transmitted without reducing the moving speed of the data carrier. Therefore, it is also possible to increase the memory capacity of the data carrier.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing details of a data carrier demodulation circuit, Manchester signal synchronization circuit, and decoding circuit according to an embodiment of the present invention, and FIG. 2 shows the overall configuration of an article identification system according to the present invention. Block diagram, Figure 3 is a block diagram showing the configuration of the ID controller and read/write head, Figure 4 is a block diagram showing the configuration of the data carrier, and Figure 5 is a time chart showing the operation of the data carrier according to this embodiment. , FIG. 6 is a time chart showing the state in which a clock signal synchronized with the Manchester signal is generated within the data carrier, and FIG.
It is a time chart showing the operation when transmitting a signal to the D controller side. 13--Data carrier 14--Read/write head 15---ID controller 21--CPU 25,47. -・-Encoding circuit 30.42--・-・-Demodulation circuit 31
．． 43---Decoding circuit 44------
Manchester signal synchronization circuit 45--Memory control section
46------ Memory 54-- Fall detector 55-- Counter 56-- Reset signal generation circuit 57-- Oscillator patent applicant Omron Co., Ltd. agent Patent attorney Yoshiki Okamoto (1 person)

Claims (1)

[Claims] (1) A memory that holds data, a memory control means that controls writing and reading of data to the memory, demodulating commands and data given from the outside, and transmitting the read data to the memory control means. a data carrier that is attached to an article to be identified, and a write/read control unit that has a data transmission means that transmits data to the data carrier and receives the transmitted data. An article identification system, wherein the data transmission means of the write/read control unit includes an encoding circuit that converts a data signal to be sent into a Manchester signal at a predetermined frequency, and a logic of the Manchester signal obtained by the encoding circuit. a transmitting section that outputs an ASK modulated signal that intermittents a clock signal of a predetermined frequency in accordance with the level, and the data transmission means of the data carrier includes: a receiving section that receives the transmitted ASK modulated signal; , a demodulation circuit that identifies the Manchester signal from the ASK modulated signal among the received signals; and Manchester signal synchronization for obtaining a clock signal synchronized with the Manchester signal by detecting a change point of the signal obtained from the demodulation circuit and applying synchronization. a decoding circuit that decodes the original signal from the clock signal and Manchester signal output from the Manchester signal synchronization circuit, and a clock signal to be transmitted based on the clock signal obtained by the Manchester signal synchronization circuit. An article identification system comprising: a reverberation control circuit that reads data and controls reverberation.