WO2006117866A1 - Ic tag - Google Patents

Abstract

A nonvolatile memory array (NVM_ARY) includes a storage area (NML_ARA) which can be utilized by a general user, and an extended storage area (EXTD_ARA) which can be utilized by a specific user. The extended storage area (EXTD_ARA) is provided with an area (TRIM_ARA) for storing the trimming data of a regulator circuit, and an area (SECU_SW) for storing security-specific data. The trimming data and the security-specific data are read from the NVM_ARY through the memory control circuit (NVM_CTL), when triggered by an AND output of the rising detection signal, as generated by a VREG_DET, of the regulator circuit and the detection signal, as generated by a PRE_DET, of a preamble start. The trimming data thus read is set in the regulator circuit, and the security-specific data is used to set the release/unrelease of the EXTD_ARA from the user.

Description

 Specification

 IC tag

 Technical field

 TECHNICAL FIELD [0001] The present invention relates to an IC tag, and more particularly to a technique effective when applied to a passive IC tag.

 Background art

 According to a study by the present inventor, the following technologies can be considered for the technology of the IC tag.

 [0003] An IC tag refers to a small device having a storage medium, a wireless communication function, an antenna, and the like. The IC tag is sometimes referred to as a “wireless tag”, “electronic tag”, or “RFID (Radio Frequency Identification) tag”. For example, there are various shapes such as a coin type with a diameter of about 2 cm, a stick type with a length of about 5 cm, a label type and a card type with a cash card.

 [0004] Such an IC tag includes information in its storage medium. The information can be read out wirelessly using a device called a reader / writer. In recent years, for example, attempts have been made to perform process management using an IC tag in a product assembly process, or to perform product management using an IC tag instead of a barcode.

 [0005] By the way, IC tags are roughly classified into active types and passive types because of the difference in power supply method. Active type IC tags obtain the power required for operation by mounting batteries. On the other hand, a noisy IC tag does not have a battery or the like, and obtains power necessary for operation through wireless communication with a reader / writer. In other words, radio waves that are also sent by the reader / writer force are converted into electric power and used as radio wave energy that can be used only as a signal.

[0006] Note that the frequency band of radio waves used for communication between an IC tag and a reader / writer is determined by standards. One example is the 13.56MHz band using the electromagnetic induction system and the 2.45GHz band using the microwave system. Among them, the 2.45 GHz band standard is defined in ISO 18000-4, which is an international standard. 2.45 GHz band power Waves have a communication distance of, for example, about lm, which is longer than the 13.56 MHz band. Recently, the 900 MHz band has attracted attention as a frequency band that can further extend the communication distance.

 Disclosure of the invention

 Problems to be solved by the invention

 [0007] By the way, as a result of the study by the inventor of the IC tag technology as described above, the following became clear.

 [0008] For example, in the standard ISO18000-4 as described above, a signal transmission / reception procedure between an IC tag and a reader / writer is defined. Within this standard, there are certain specifications such as the signal format for synchronizing the input signal to the IC tag and the start bit.

 [0009] With regard to the reader / writer power, the transmission / reception of data to / from the IC tag is performed by specifying the IC tag and address by the reader / writer. For example, in the case of a READ command, the IC tag reads a unique ID value from the storage medium, and stores the data at the address specified by the reader / writer when the ID value matches the ID value specified by the reader / writer. Read the media force and send it back to the reader / writer.

 [0010] Under such circumstances, for example, the following problems can be considered for such an IC tag.

[0011] First, there is a problem related to the reliability of the operation of the IC tag. For example, a passive IC tag as described above rectifies a carrier wave transmitted from a reader / writer to generate a power supply voltage. The input voltage level of this carrier wave depends on the distance between the reader / writer and the IC tag at the time of communication. For this reason, if this power supply voltage is directly used as an operating power source for a storage medium or the like in an IC tag, for example, fluctuations of about 1.5V to 4V may occur, which may cause the storage medium or the like to be out of the guaranteed operating range. Therefore, it is conceivable to provide a regulator circuit in order to stabilize the operating power supply of the storage medium. However, even when a regulator circuit is mounted in an IC tag, the output voltage varies due to process variations of the regulator circuit, and there is a concern that the reliability may be lowered.

[0012] Secondly, there is a problem related to data security of IC tags. For IC tags As described above, if the ID values match, the information on the storage medium can be read. Therefore, as long as the ID value is sufficient, information in the storage medium can be easily stolen by remote control using a general-purpose reader / writer. Of course, only information that has no problem even if read can be stored in the IC tag. There are times when you want to use different data separately.

 Accordingly, an object of the present invention is to improve the reliability of an IC tag. Another object of the present invention is to improve IC tag data security. Furthermore, it is to realize a low cost IC tag.

[0014] The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

 Means for solving the problem

[0015] Among the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

 An IC tag according to the present invention is a passive IC tag including a nonvolatile memory and a regulator circuit, and trimming for adjusting the value of the internal power supply voltage generated by the regulator circuit in the nonvolatile memory. It has data, is read out, and is reflected in the regulator circuit. By providing trimming data in the nonvolatile memory in this way, variations in internal power supply voltage due to process variations and the like can be suppressed at a low cost or in a small area, and the reliability of the IC tag can be improved.

[0017] Here, when reading trimming data from the nonvolatile memory, the regulator circuit is activated upon receiving power supply from the reader / writer, and accordingly, an operable voltage level is supplied to the nonvolatile memory. It needs to be done later. In addition, it is desirable that this is performed before the synchronization of the internal clock in the IC tag is completed in response to the synchronization signal from the reader / writer. In other words, after synchronization of the internal clock, the internal power supply voltage changes as the trimming data is reflected, and there is a concern that synchronization will be lost. Therefore, by reflecting before the synchronization is completed, a stable internal clock can be generated and the reliability of the IC tag is improved. [0018] In addition, the reader / writer normally transmits a synchronization signal of, for example, about 10 cycles after the signal for power supply. Trimming is performed using the start of the synchronization signal (that is, the first signal edge) as a trigger. Data may be read out. Normally, the regulator circuit has already started up before the trigger time, and an internal clock signal having almost the same clock cycle as the synchronization signal starts to be generated by the trigger time clock recovery circuit or the like. Therefore, since the nonvolatile memory can be operated using this internal clock signal, the trimming data can be read easily. Even when this trigger is used, trimming data can be sufficiently read and reflected within the time when the synchronization signal is transmitted from the reader / writer (that is, before the synchronization is completely confirmed). .

 [0019] The IC tag according to the present invention is a passive IC tag including a nonvolatile memory and a regulator circuit, and includes a first storage area and a second storage area in the nonvolatile memory, and the first storage area The first mode is accessible only to the first mode, and the second mode is accessible to both the first storage area and the second storage area. The second storage area stores first data for setting the first mode or the second mode.

 [0020] In such a configuration, after the regulator circuit is activated upon receiving the power supplied by the reader / writer, and after the voltage level operable to the nonvolatile memory is supplied, the nonvolatile circuit is first The first data is read from the memory. Then, the first data is compared with a specific value provided in advance in the IC tag, and the mode is switched between the first mode and the second mode. As a result, two types of IC tags with different apparent storage areas from the reader / writer can be easily realized using one IC tag.

 [0021] Therefore, for example, if the first storage area is an open area to general users and the second storage area is a security area that can be used only by a specific user, the first data can be An IC tag that does not have a security area for users and an IC tag that has a security area for specific users can be realized.

[0022] Further, in the second storage area, it is preferable to store second data for authenticating whether the second storage area is accessible in addition to the first data. This second data is compared with the security code when the security code is sent from the reader / writer, and the IC tag permits access to the second storage area only when it matches. [0023] Therefore, even an IC tag whose second storage area is open (that is, an IC tag in the second mode) cannot access the second storage area unless the security code is successfully authenticated. Data security is improved. The second data should be rewritten only by a specific user who knows the second data. Then, the security code (ie second data) can be changed as necessary. In addition to the first and second data, if an original command for accessing the second storage area is provided in the IC tag, data security can be further improved.

 In addition, the IC tag according to the present invention includes trimming data in addition to the first data and the second data described above in the second storage area described above. In this case, after the operable voltage level is supplied to the nonvolatile memory, the trimming data is read first, and then the first data is read. Then, along with the reflection of the trimming data as described above, security-related processing is performed using the first data. The reader / writer also reads the second data when a security code is issued along with its own command. When the security code matches the security code, the second storage area can be accessed. This makes it possible to improve the reliability of IC tags and improve data security at a low cost or in a small area.

 [0025] It should be noted that the trimming data and the first data are preferably written only in the manufacturing stage and thereafter can only be read and cannot be rewritten. The trimming data and the first data may be stored at consecutive memory addresses in the second storage area. Thus, for example, by using an address counter or the like, it is possible to efficiently read these data and perform a desired process.

 The invention's effect

 [0026] If the effects obtained by the representative ones of the inventions disclosed in the present application are simply described, the reliability of the IC tag can be improved. In addition, IC tag data security can be improved. Furthermore, the low cost of IC tags can be realized.

 Brief Description of Drawings

[0027] [FIG. 1] A system configuration including an IC tag according to an embodiment of the present invention. It is the schematic which shows an example.

 FIG. 2 is a block diagram showing an example of the overall configuration of an IC tag according to an embodiment of the present invention.

 FIG. 3 is an explanatory diagram showing an example of a signal format when a reader / writer force reading request is made in the IC tag of FIG. 2, and (a) is an example of a signal format in which the reader / writer force is also directed to the IC tag. (B) shows an example of the signal format from the IC tag to the reader / writer.

 4 is a block diagram showing a configuration example of a part of the logic control circuit, the VREG detection circuit, and the nonvolatile memory in the IC tag of FIG.

 FIG. 5 is a circuit diagram showing a detailed configuration example of a circuit related to setting of trimming data in the IC tag of FIGS. 2 and 4.

 6 is an explanatory diagram showing an example of a memory map of the nonvolatile memory in the IC tag of FIG.

 FIG. 7 is a flowchart showing an example of processing of the security transaction or normal operation transaction in the IC tag of FIGS. 2 and 6.

 [FIG. 8] An explanatory diagram showing an example of a signal format from the reader / writer to the IC tag in the case of a security transaction in the flow of FIG. 7, (a) is the signal format of the first half, (b ) Is a signal format of the latter half part following (a).

 BEST MODE FOR CARRYING OUT THE INVENTION

 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted. The circuit elements constituting each functional block of the embodiment are not particularly limited, but are formed on a semiconductor substrate such as single crystal silicon by a known integrated circuit technology such as a CMOS (complementary MOS transistor). Is done.

In the drawing, the PMOS transistor is distinguished from the N MOS transistor by adding a circle symbol to the gate of the PMOS transistor. In the drawing, the connection of the substrate potential of the MOS transistor should be clearly stated, but the connection method is not particularly limited as long as the MOS transistor can operate normally. In the following description, the standard ISO18000 Based on —4. 2. The passive IC tag operating in the 45GHz band will be described as an example, but it is equally applicable to IC tags with other frequency bands that are not limited to this. It is.

 FIG. 1 is a schematic diagram showing an example of a system configuration including an IC tag according to an embodiment of the present invention. The system shown in FIG. 1 includes, for example, a reader / writer RW and a plurality of IC tags TG. For example, the reader / writer RW supplies electric power to a plurality of IC tags TG by radio waves, and communicates by radio waves with a desired TG. The TG performs processing according to the command from the radio wave from the RW and returns the processing result to the RW.

 [0031] The IC tag TG in FIG. 1 has an IC chip in which a storage medium, a communication circuit, and the like are integrated on a film and an antenna connected to the IC chip. It is about centimeters. In FIG. 1, for example, an IC tag TG called an inlet or the like is shown, and when this is packaged, various shapes such as a stick type, a coin type and a card type are formed.

 FIG. 2 is a block diagram showing an example of the overall configuration of an IC tag according to an embodiment of the present invention. The IC tag shown in FIG. 2 includes, for example, a power supply system circuit block, a signal processing system circuit block, and a nonvolatile memory NVM. The power system circuit block includes, for example, a rectifier circuit RECT connected to the antenna ATN, a voltage limiter circuit LMT and a regulator circuit VREG connected to its output, and a VREG detection circuit VREG— Including DET!

 [0033] The circuit block of the signal processing system includes, for example, a modulation circuit MO DU and a demodulation circuit DMODU connected to the antenna ATN, and a logic control circuit LOG-CTL provided between these circuits and the nonvolatile memory NVM Etc. In addition, the signal processing circuit block includes the oscillation circuit OSC, the clock recovery circuit CLK-GEN, and the power-on reset circuit POR.

[0034] The antenna ATN receives the radio wave from the reader / writer RW and sends a reply to the reader / writer RW. The rectifier circuit RECT includes, for example, a diode bridge and a smoothing capacitor, and arranges AC signal radio waves (specifically, 2.45 GHz carrier waves) received by the ATN. It is converted into a DC power supply voltage by flowing and smoothing. This DC power supply voltage is high, for example, about 7-8V. The voltage limiter circuit LMT limits the DC power supply voltage converted by the RECT within a certain range for the purpose of ensuring the withstand voltage of the transistor. That is, for example, the voltage of about 7-8V is limited to the DC power supply voltage RFvdd, such as 5V or less.

 The regulator circuit VREG generates an internal power supply voltage Vdd to be supplied to a signal processing circuit block, a nonvolatile memory NVM, and the like based on the DC power supply voltage RFvdd limited by the LMT. VREG detection circuit VREG—DET operates with RFvdd and detects the VREG power supply rise by determining the output voltage of VREG. Details of VREG and VR EG-DET will be described later with reference to FIG.

 The modulation circuit MODU modulates the carrier wave transmitted from the reader / writer RW based on the baseband data output from the logic control circuit LOG-CTL when sending a reply to the reader / writer RW. Specifically, for example, encoding called FM0 is performed on 40 kHz baseband data, and the impedance of the antenna ATN is changed based on the data. Then, the 2.45 GHz carrier wave transmitted from RW is reflected by ATN, and RW receives a different reflected wave corresponding to the change in its impedance. By detecting this, the response from the IC tag is returned. Can receive.

 [0037] The demodulation circuit DMODU demodulates the radio wave received from the reader / writer RW via the ATN, and generates a baseband signal. Specifically, for example, the radio wave power that has been subjected to amplitude modulation, etc. for a 2.45 GHz carrier wave. The signal part is detected, and decoding is performed based on a format called Manchester one, and 40 kHz Generate baseband signals. This generated signal is output to the logic control circuit LOG-CTL and the clock recovery circuit CLK-GEN.

[0038] The logic control circuit LOG—CTL performs various baseband processing. For example, processing to decode commands from signals input via DMOD U, processing to read or write stored data to NVM based on commands, processing to output stored data read from NVM to MODU, etc. Is mentioned. The oscillation circuit OSC is, for example, a so-called ring oscillator that is supplied with the internal power supply voltage Vdd and includes a plurality of inverter circuits. The 1MHz clock signal is output. The clock recovery circuit CLK—GEN includes, for example, a counter that is supplied with the internal power supply voltage Vdd and operates with a 1 MHz clock signal from the OSC.

 [0039] Such CLK-GEN generates an internal clock signal in a cycle based on a counter value, for example. This counter value is calculated by measuring the time between the rising and falling edges of the 40kHz preamble signal (synchronization signal) from DMODU and averaging them. It is determined by making it. This makes it possible to generate an internal clock signal (40 kHz) with a uniform duty ratio in synchronization with the ATN-received radio wave. This internal clock signal is used as a reference clock signal for internal circuits such as LOG-CTL.

 [0040] The power-on reset circuit POR detects the rise of the power supply of the regulator circuit VREG or the reset of each internal circuit after waiting for the generation of an internal clock signal in response to this, or the fall of the power supply of the VREG. To reset each internal circuit. The non-volatile memory NVM is supplied with Vdd and can be read and written, for example, an EEPROM (Electronically Erasable and Programmable Read Only Memory), a FLASH memory, or the like. NVM here has a capacity of 256 bytes.

 [0041] In such a configuration, the main feature of the present invention is that the trimming data of the regulator circuit VREG and the security-related data are stored in the nonvolatile memory NVM in addition to the ID data normally provided. Be prepared. And, to use these data while complying with the standard specified in ISO18000-4, for example. Hereinafter, these details will be described.

 FIG. 3 is an explanatory diagram showing an example of the signal format when the reader / writer force is also requested to read in the IC tag of FIG. 2, and (a) is a signal format in which the reader / writer force is also directed to the IC tag. An example of the format, (b) shows an example of the signal format for the IC tag power toward the reader / writer.

[0043] Upon a read request, the reader / writer RW outputs radio waves in the signal format shown in Fig. 3 (a) toward the IC tag. The signal format shown in Fig. 3 (a) is a preamble. It comprises detection 300, preamplifier 301, S delimiter 302, = f command 303, ID 304, dress 305, and CRC 306. The preamble detection 300 is intended to power up the IC tag, and is a level signal that is continuous for a certain period of time.

 [0044] It should be noted that, although shown in the figure, a '1, level signal on an actual radio wave is a waveform obtained by modulating a 2.45GHz carrier wave with a' 1 'level signal. It becomes a carrier wave with amplitude A. On the other hand, the “0” level signal on the actual radio signal becomes a carrier wave having an amplitude B smaller than the amplitude A of the “1” level signal, for example, when amplitude modulation is used.

 [0045] Preamble 301 is intended for IC tag synchronization, and is composed of a synchronization signal in which a '0' level signal and a '1' level signal are repeated nine times. The S delimiter 302 is intended to notify the start of the command 303 and is, for example, a “1100111010” signal. The command 303 is an 8-bit signal. In the case of a READ command, for example, it is a “00001100” signal. ID304 is an 8-byte (64-bit) signal that identifies the destination IC tag. The address 305 designates a memory address in the destination IC tag, and is an 8-bit signal, for example. A CRC (Cyclic Redundancy Check) 306 is used to check whether or not the data communication is normally performed, and is a 16-bit signal, for example.

 On the other hand, the IC tag receives a signal as shown in FIG. 3 (a), performs an operation corresponding thereto (in this case, a memory read operation), and sends it to the reader / writer RW as shown in FIG. 3 (b). The signal format is returned as shown in. The signal format shown in FIG. 3B is composed of a quiet 307, a preamplifier reply 308, read data 309, and a CRC 310.

 The quiet 307 is a period of, for example, 16 bits provided to regenerate the power supply of the IC tag that may be lowered, as in the preamble detection 300 described above. The bumble reply 308 is a synchronization signal sent back to the reader / writer RW, and is, for example, 16 bits. Read data 309 is a signal corresponding to data read from NVM in response to a read request from RW, and is 8 bytes (64 bits), for example. CR C310 is the same signal as described above.

[0048] In such a signal format, the IC tag performs, for example, the operation shown in the lower part of Fig. 3 (a) in response to a request to read the reader / writer RW force. Do. First, the first point in this operation is that the trimming data (TRIM-DAT) is also read out by the NVM force by the end of the preamble, and the setting has been completed. In the preamble 301, the reader / writer RW and the IC tag are synchronized using the clock recovery circuit CLK—GEN as described in FIG. Assuming that trimming data setting is completed after the end of preamble 301, the internal power supply voltage Vdd of CLK-GEN changes after synchronization, and the oscillation circuit cycle and power-tuner cycle associated with this change. There is a risk that synchronization will be lost due to fluctuations in

 Therefore, by completing the setting of the trimming data before the preamble 301 is completed, it is possible to prevent such a synchronization problem. Furthermore, after setting trimming data (and after synchronization), the IC tag can be operated with the internal power supply voltage Vdd based on this trimming data. Therefore, variations in internal power supply voltage Vdd due to process variations are reduced, preventing malfunction of IC tags due to inappropriate power supply voltage values and destruction of IC tags due to excessive power supply voltage values. In addition, the yield of IC tags in the manufacturing process will be improved. Such power also makes it possible to improve the reliability of IC tags. In addition, the manufacturing cost of IC tags can be reduced.

 [0050] The second point in the IC tag operation in Fig. 3 (a) is that after trimming data (TRIM —DAT) is read from NVM and before ID data (ID — DAT) is read The switch (SECU-SW) is being read. Here, for example, TRIM-DAT and SECU-SW may be stored in consecutive memory addresses, and TRIM-DAT and SECU-SW may be read continuously. This makes it possible to shorten the readout time and reduce the readout power.

 [0051] A detailed usage example of the SECU-SW will be described later with reference to Figs. Reading of ID—DAT after reading of SEC U—SW is performed based on the standard. That is, the ID tag is read from the NVM memory address specified by the standard, and the ID tag is identified by comparing the ID-DAT with the ID sent from the reader / writer RW. Is called.

Such trimming data TRIM-DAT and security switch SECU-SW are read using a configuration as shown in FIG. 4, for example. Figure 4 shows the IC tag in Figure 2. FIG. 2 is a block diagram showing a configuration example of a part of the logic control circuit, the VREG detection circuit, and the nonvolatile memory. Here, for ease of explanation, each circuit is classified into circuit blocks for explanation, but the correspondence between each circuit and circuit block is of course not limited thereto.

 In FIG. 4, in the logic control circuit LOG—CTL, the S delimiter analysis circuit S—CTL, the command analysis circuit CMD—CTL, the read / write address register ADD—REG, and the preamplifier falling detection circuit PRE — Includes DET. In addition, an AND circuit AND of the PRE-DET and the VREG detection circuit VREG-DET described above is also included. The output signals of these circuits are input to the nonvolatile memory NVM.

 The non-volatile memory NVM is classified into, for example, a non-volatile memory array NVM-ARY and a memory control circuit NVM-CTL that controls the memory array. The NVM-CTL includes a count control circuit CUNT-CTL, a load value control circuit LD-CTL, an address counter ADD-CUNT, and a memory address register MADD-REG! /.

 [0055] S-CTL and CMD-CTL output signals and the above-described AND circuit AND output signal trg are input to CUNT-CTL. LD—CTU receives the output signal trg and S—CTL and ADD—REG output signals. The output signals of CUNT-CTL and LD-CTL are input to the address counter ADD-CUNT, and the output signal of ADD-CUNT is set in the memory address register MADD-REG. In the non-volatile memory array NVM-ARY, a read operation or a write operation using the address value of the MADD-REG is performed. For example, the bit width of MADD-REG is 8 bits.

Here, the storage area of the nonvolatile memory NVM includes an extended storage area EXTD-ARA in addition to the normal storage area NML-ARA defined by the standard. NVM is, for example, 256 knots, 128 bytes are allocated to NML—ARA, and 128 bytes are allocated to EXTD—ARA. In accordance with the standard, NML—ARA includes an ID storage area ID—ARA in which the ID of the IC tag is stored, and a user area USR_ARA that can be used by the user, from the lower part of the address. EXTD_ARA is, for example, the area TRIM—ARA where trimming data is stored and the area where security related data is stored (security switch H SECU—SW and security code SECU—CD) and private memory area SPE—A RA.

 Next, the operation of FIG. 4 will be described. First, the VREG detection circuit VREG-DET detects that the regulator circuit VREG has risen and its output voltage has reached a desired value. The preamble falling detection circuit PRE-DET detects the first falling signal in the preamble 301 in FIG. That is, in Fig. 3 (a), a change from '1, level signal to' 0, level signal when transitioning from the preamble detection 300 to the preamble 301 is detected. Then, an output signal trg obtained by performing an AND operation on these detection signals is input to the load value control circuit LD-CTL and the count control circuit CUNT-CTL.

 [0058] LD_CTL receives this output signal trg and outputs an initial value provided in advance (that is, a leading address in which trimming data is stored) to address counter ADD-CUNT. Then, the output of ADD-CUNT is set in the memory address register MADD-REG, and then reading of trimming data from the nonvolatile memory array NVM-ARY is started. On the other hand, the CUNT-CTL receives the output signal trg and controls the count in the ADD-CUNT. Therefore, the trimming data can be completely read out by sequentially counting up the addresses by a preset amount. Furthermore, when trimming data and security-related data are stored continuously (ie, when TRIM-ARA and SECU-SW are consecutive), both data can be controlled by controlling the count. Can be read continuously.

[0059] Here, in addition to the rise of the regulator circuit VREG, the power of reading trimming data in response to the first fall of the preamble, and in some cases, reading of trimming data only at the rise of VREG It is also possible to perform. In the operation of Figure 4, the first falling edge of the preamble that occurs after the rising edge of VREG is added as a condition to facilitate the timing of the NVM read operation. In other words, here, it is assumed that the NVM operates based on the 40 kHz internal clock signal output from the clock recovery circuit CLK-GEN in FIG. 2. This 40 kHz internal clock signal is the first rising edge of the preamble. It will be output from the bottom. But Therefore, if the NVM is configured to operate using a different clock signal from the rise of VREG, trimming data can be read only by the rise of VREG.

 [0060] The S-delimiter analysis circuit S-CTL is a circuit that detects, for example, the first falling signal when the S-delimiter 302 shown in FIG. S-CTL is used when TRIM-ARA and SECU-SW are not continuous or when trimming data and SECU-SW are read separately. That is, starting from the S-CTL detection signal, the LD-CTL loads the start address of the SECU-SW, and the CUNT-CTL controls the ADD-CUNT as in the above-described trimming data reading. Read SECU— SW completely from ARY.

 [0061] In the read / write address register ADD—REG, the value input at the address 305 in FIG. 3A is set. For example, the command analysis circuit CMD-CTL analyzes whether the command 303 force 1 byte read command force 8 byte read command in FIG. In the case of a 1-byte read command, by setting the value of ADD—REG to MADD—REG via LD—CTL and ADD—CUNT, 1 byte of the address is read. On the other hand, in the case of an 8-byte read command, 8 bytes are read by controlling ADD-CUNT by CUNT-CTL in response to the 1-byte read operation.

 FIG. 5 is a circuit diagram showing a detailed configuration example of a circuit related to setting of trimming data in the IC tag of FIGS. 2 and 4. In FIG. 5, the regulator circuit VREG in FIG. 2 and the VREG detection circuit VREG—DET, preamble falling detection circuit PRE—DET, AND circuit AND in FIG. 4, nonvolatile memory array NVM—ARY and memory control circuit NVM— CTL is shown! /

[0063] The regulator circuit VREG includes, for example, a so-called series regulator having a two-stage configuration. One series regulator (first series regulator) has a PMOS transistor MP 1 and a variable resistor RV connected in series between the power supply voltage RFvdd and the ground voltage GND, and an amplifier circuit AMP 1 at the gate of MP 1 The output is connected to each other. The variable resistor RV has a plurality of resistors connected in series and outputs one of the connection nodes between the resistors. It can be connected to the ND1. That is, the voltage of ND1 can be changed by changing the resistance ratio. The selection of the connection node is performed by selecting the switch SW, for example, and the selection of the SW is performed based on the value of the trimming setting register TRIM-REG. In this case, 16 SWs are used and TRIM-REG is configured in 16 bits (2 bytes).

In the amplifier circuit AMP1, the reference voltage BIAS is input to one input, and the feedback signal from the specific connection node ND11 in the variable resistor RV is input to the other input. An NMOS transistor MN 1 is connected between the other input and the output node ND 1. The gate of MN1 is controlled by VREG detection circuit VREG—DET

[0065] The other series regulator (second series regulator) has a PMOS transistor MP2 and a plurality of resistors RL connected in series between the power supply voltage RFvdd and the ground voltage GND, and an amplifier circuit at the gate of MP 2 The output of AMP2 is connected. In the amplifier circuit A MP2, the output node ND1 described above is connected to one input, and a feedback signal from a connection node ND21 in the plurality of resistors RL is input to the other input. The other connection node ND22 in the plurality of resistors RL is connected to the VREG detection circuit VREG-DET. The internal power supply voltage Vdd is output from the drain of MP2.

 [0066] The VREG detection circuit VREG-DET includes, for example, a comparator circuit CMP and an inverter circuit INV connected to the output thereof. The output of CMP is also connected to the gate of the NMOS transistor MN1 described above. One input of the comparator circuit CMP is connected to the aforementioned output node ND1, and the other input is connected to the aforementioned connection node ND22.

[0067] The AND circuit AND is composed of, for example, two-stage flip-flops DFF1 and DFF2. The flip-flop DFF1 in the first stage outputs the power supply voltage RFvdd to DFF2 at the rise of the inverter circuit INV described above, and DFF2 generates the output signal trg by the detection signal of the preamble fall detection circuit PRE—DET described above. To do. In other words, the VREG—DET output and the PRE—DET output are ANDed. The AND output signal trg is output to the memory control circuit NVM-CTL. Next, an outline of the operation of the configuration in FIG. 5 will be described. First, at the stage when VREG rises, the output power of CMP becomes 1 'level signal. Therefore, MN1 is on and the output signal trg is a '0' level signal. At this time, the output of TRIM-REG and the SW state are indefinite. However, the connection to AMP2 is secured by turning on MN1. That is, MN1 equivalently defines the SW connection point in the initial state.

 [0069] After that, the output of MP1 is input to AMP2 via variable resistor RV and MN1, and MP2 is turned on by driving AMP2. When the voltage of ND22 exceeds the desired judgment value (that is, when VREG rises and exceeds the voltage level at which NVM etc. can operate normally), the CMP output is '1, level signal to' 0, level signal Invert to. As a result, MN1 is turned off. Here, there is concern about the indefiniteness of the voltage of ND1, but any SW (eg, Y6) is turned on in advance by resetting TRIM-REG at the timing before MN1 is turned off.

 [0070] On the other hand, DFF1 outputs a '1' level signal in response to the transition of the CMP output to a '0' level signal, and DFF2 outputs in response to the first falling edge of the subsequent preamble signal. The signal trg changes from '0' level signal to '1, level signal. As a result, the operation as described in FIG. 4 is performed, and the trimming data is transferred from the non-volatile memory array NVM-ARY to the TRIM-REG. If the NVM data width is 8 bits, TRIM-REG is set in two data transfers. When TRIM-REG is set, the SW is set accordingly and the desired internal power supply voltage Vdd can be generated. Note that the value of Vdd is set to 1.7 V, for example, by trimming in consideration of the transistor operating range and power consumption.

In addition, the value of the trimming data is determined for each IC tag by inspecting each IC tag in the IC tag manufacturing process (test process). In the manufacturing process, the optimum value is written to each NVM. Here, as a means for setting the trimming data, it is possible to use a widely known fuse other than NVM. In this case, since the internal power supply voltage reflecting the trimming data has already been generated when the regulator circuit is started up, there is no difficulty in conforming to the standard. [0072] However, if a fuse is used, the manufacturing cost associated with the fuse cutting increases, and the circuit area may also increase. In the case of IC tags, such a problem that the demand for cost reduction and area reduction is very high is not preferable. Therefore, using NVM and setting the trimming data with the configuration and method described above, it is possible to improve the reliability of the IC tag at a low cost and in a small area without affecting the standard. In addition to reading trimming data from NVM, it is possible to improve IC tag reliability and data security efficiently by continuously reading security-related data as described later. It becomes.

 Next, an example of using security related data stored in NVM will be described.

 FIG. 6 is an explanatory diagram showing an example of a memory map of the nonvolatile memory in the IC tag of FIG. In Figure 6, for example, a 256 byte memory map in NVM is shown. Of these, the lower 128 bytes of the address is the storage area NML—AR A defined by the standard. For example, the 8-byte area ID—ARA, in which the ID of the IC tag is stored—can be freely used by general users. USR—Includes ARA. In addition, an area for storing the serial number may be provided in the USR-ARA.

 On the other hand, the upper 128 bytes of the address is an expanded storage area EXTD-ARA. Inside, for example, a 2-byte trimming data storage area TRIM-ARA, a 1-byte security switching data storage area SECU-SW, an 8-byte security code storage area SECU-CD, and a private memory area SPE—Equipped with ARA. This EXTD-ARA is used as an area that can be used only by specific users, for example.

[0076] SPE-ARA stores secret information of a specific user. The SECU—SW stores data for switching whether to enable the security function. If the specific code stored in the SECU-SW is stored, the EXTD-ARA is released. Otherwise, the EXTD-ARA is not released. That is, two modes are switched by SECU-SW. In one mode, only NML-ARA can be used, and in the other mode, both NML-ARA and EXTD-ARA can be used. . The SECU-CD stores, for example, a security code for authenticating access permission to the SPE-ARA. In such a configuration, when a signal format similar to that shown in FIG. 3 (a) is received from the reader / writer RW, the logic control circuit LOG-CTL of the IC tag in FIG. 2 is shown in FIG. The operation is performed. FIG. 7 is a flowchart showing an example of processing of the security transaction or normal operation transaction in the IC tag of FIG. 2 and FIG. Fig. 8 is an explanatory diagram showing an example of the signal format from the reader / writer to the IC tag in the case of the security transaction in the flow of Fig. 7, (a) is the signal format of the first half, (b) Is the signal format of the second half following (a).

 First, the outline of the processing flow of FIG. 7 will be described. The IC tag of this embodiment can support two compatible signal formats. One is a normal signal format as shown in Fig. 3 (a), and the other is a unique signal including a unique command 303a that does not conflict with the standard command as shown in Figs. 8 (a) and (b). Is the signal format. In the case of the signal format in Fig. 3 (a), processing is performed as a normal operation transaction, and in the case of the signal format in Figs. 8 (a) and (b), processing is performed as a security transaction. Which transaction is to be performed is determined by the SECU-SW data and whether or not a unique command is received. These details will be described below.

 [0079] First, in response to the first fall of the preamble detection 300, 300a and the preamble 301, 3 Ola in 03 (a) and FIG. 8 (a), the trimming data and the security-related data are Read continuously. That is, TRIM-ARA and SECU-S W in Fig. 6 are read out. Trimming data is transmitted from NVM to VREG, while SE CU-SW data is transmitted from NVM to logic control circuit LOG-CTL and held in LOG-C TL. Here, in order to proceed with the internal processing of the IC tag promptly in response to the input signal from the reader / writer, the transmission of the commands 303 and 303a in Fig. 3 (a) and Fig. 8 (a) is not completed at the latest. It is desirable that the SECU-SW data is retained in the LOG-CTL. It should be noted that this condition can be fully met if the 1-byte SECU-SW is read immediately after trimming data.

Thereafter, as shown in FIG. 7, the LOG-CTL looks at the value of the SECU-SW and determines whether or not it is a specific code (S701). And if it is a specific code, EXTD ARA Release (S702), otherwise release is not performed (S707). In other words, if a specific code is not stored in the SECU-SW, the IC tag is apparently equipped with only 128-byte NML-ARA. Therefore, in this case, it is not recognized when an independent command is received in the subsequent commands 303 and 303a (S708), and operates only when a normal command is received. In other words, it does not work with the signal format in Fig. 8 (a), but only with the signal format in Fig. 3 (a).

 When a normal command is received (S709), normal operation including ID 304 and ID-DAT match determination (S709a) is performed according to the signal format of FIG. 3A (S710). A series of processes when the normal command is received and the force normal operation is performed will be referred to as a normal operation transaction here.

 On the other hand, when the specific code is stored in the SECU-SW and the EXTD-ARA is released (S702), it is determined whether or not the subsequent commands 303 and 303a are unique commands (S703). If it is not an original command, the normal command is judged (S709), and the normal operation transaction conforms to the signal format shown in Fig. 3 (a). If it is an original command, ID304a and ID-DAT match determination is performed according to the signal format in Fig. 8 (a) (S703a) o If there is a mismatch, for example, nothing is returned to the reader / writer Reply rejection processing such as “No” is performed (S706).

 [0083] If ID304a is a match, LOG-CTL reads and holds the SECU-CD data from NVM. At this time, in order to proceed with the internal processing of the IC tag promptly in response to the input signal with the reader / writer power, at the latest by the end of the transmission of the security code 31 la in FIG. CD data should be kept in LOG—CTL.

Then, the LOG-CTL compares the read SECU-CD data with the security code 31 la transmitted by the reader / writer according to the signal format of FIG. 8 (a) (S704). If the results match, access to SPE-ARA is permitted (S705), and if not, the reply is rejected (S706). A series of processing from receiving this unique command to authenticating the availability of access to SPE-ARA is called an authentication transaction here. And this authentication transaction and the unique operation transaction described later These are called security transactions.

 [0085] When access to the SPE-ARA is permitted by the authentication transaction, a unique operation transaction is subsequently performed. In the specific operation transaction, specific instructions (read or write, etc.) are issued to the reader / writer SPE-ARA based on the signal format shown in Fig. 8 (b). Here, the signal format shown in Fig. 8 (b) has the same configuration as the signal format shown in Fig. 3 (a), and the SPE-ARA address can be specified as address 305a to perform the desired operation. It is possible.

 [0086] Further, the signal format shown in FIG. 8 (b) is issued immediately after the signal format shown in FIG. 8 (a). From the initial stage of the signal format shown in FIG. V dd is still maintained. In other words, in Fig. 8 (b), since the internal power supply voltage Vdd is maintained, trimming data and security-related data with NVM power are not read. Therefore, authentication is performed by the authentication transaction, and the unique operation transaction is performed while maintaining the authentication state.

 [0087] As described above, security-related data is provided in NVM, and the data processing of the IC tag is easily improved by processing the data so that it conforms to the standard signal format. It becomes possible to make it. In addition, by switching SECU-SW data to a common chip, normal IC tags and IC tags with security functions can be realized, so the costs associated with chip sharing can be reduced. It becomes.

 [0088] While the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention. There's nothing wrong!

[0089] For example, the description has been given by taking the 2.45 GHz band passive IC tag based on the standard as an example, but almost the same signal format is applied to other frequency band IC tags. Therefore, it is possible to set the security if trimming is set using the same method as described above. In addition, storing trimming data and security-related data in NVM is also beneficial for active IC tags. In other words, it is not very desirable to keep these data constantly with the built-in battery in terms of power saving. Use a similar method to load NVM force data.

Industrial applicability

 The IC tag of the present invention is particularly useful when applied to an IC tag that is passive and requires data security, and is not limited to this, and can be widely applied to all IC tags.

Claims

The scope of the claims

 [1] A circuit that generates a power supply voltage using power transmitted wirelessly from a reader / writer, etc., and generates an internal power supply voltage by converting the power supply voltage, and further, based on trimming data, the value of the internal power supply voltage An adjustable regulator circuit;

 A voltage detection circuit that generates a detection signal when the internal power supply voltage reaches or exceeds a desired voltage level with the start of the operation of the regulator circuit;

 A clock recovery circuit for synchronizing an internal clock signal based on the transmitted synchronization signal;

 An IC tag having a nonvolatile memory to which the internal power supply voltage is supplied, wherein the trimming data is stored in the nonvolatile memory,

 After the voltage detection circuit generates the detection signal and before the synchronization of the internal clock signal by the clock recovery circuit is determined, the trimming data is read from the nonvolatile memory and reflected in the regulator circuit. IC tag characterized by placing.

[2] In the IC tag according to claim 1,

 The reader / writer force has a signal detection circuit that outputs a detection signal when the first edge in the transmitted synchronization signal is detected,

 After the voltage detection circuit generates a detection signal and the signal detection circuit generates the detection signal, the trimming data is read from the nonvolatile memory before the synchronization of the internal clock signal by the clock recovery circuit is determined. An IC tag characterized by being read and reflected in the regulator circuit.

[3] In the IC tag according to claim 1 or 2,

 The regulator circuit is:

 A first series regulator that outputs a voltage to a first node using a first voltage as a reference voltage, and a second series regulator that outputs the internal power supply voltage to a second node using the voltage of the first node as a reference voltage When,

 A trimming setting register for holding trimming data read from the nonvolatile memory;

The first and second series regulators are respectively an amplifier circuit and an output transistor. And multiple resistors connected in series,

 The first node is

 After holding the trimming data in the trimming setting register, based on the held trimming data, the trimming setting register is connected to a connection point of V or shift in a plurality of resistors included in the first series regulator,

 Before holding the trimming data, the trimming data is connected to any of the above-mentioned connection points determined in advance as an initial state,

 The IC tag, wherein the voltage detection circuit includes a comparator circuit that compares the voltage of the first node before holding the trimming data with the voltage of the second node.

[4] A circuit that generates a power supply voltage using power transmitted wirelessly from a reader / writer, etc., a regulator circuit that converts the power supply voltage to generate an internal power supply voltage, and an operation start of the regulator circuit, A voltage detection circuit that generates a detection signal when the internal power supply voltage reaches or exceeds a desired voltage level;

 A nonvolatile memory provided with the internal power supply voltage and having a first storage area and a second storage area;

 An IC tag having a control circuit including an access control function for the nonvolatile memory,

 The IC tag is

 A first mode accessible only to the first storage area;

 The first storage area and a second mode accessible to the second storage area, wherein the first data for setting the first mode or the second mode is stored in the second storage area Stored,

 The control circuit reads the first data from the nonvolatile memory after the voltage detection circuit generates a detection signal, and determines whether or not the first data is the same as a specific value set in advance. If it is the same as the specific value, the IC tag shifts to the second mode, and if not, the IC tag shifts to the first mode.

[5] The IC tag according to claim 4,

The second storage area is further used for authenticating whether or not access to the second storage area is possible. Second data is stored,

 The control circuit reads the first data and the second data from the nonvolatile memory after the voltage detection circuit generates a detection signal, and when the mode is shifted to the second mode, the reader / writer force is also transmitted. An IC tag, wherein access to the second storage area is permitted when the security code matches the second data.

[6] In the IC tag according to claim 4,

 Reading the first data from the non-volatile memory is completed before the command transmission from the reader / writer is completed.

[7] In the IC tag according to claim 5,

 The IC tag is characterized in that reading of the second data from the nonvolatile memory is completed before the transmission of the security code from the reader / writer is completed.

[8] In the IC tag according to claim 5,

 The IC tag further has a unique command specially provided for accessing the second storage area,

 When the ID is transmitted after the unique command is transmitted from the reader / writer, and then the security code is transmitted,

 The reading of the first data is completed before the transmission of the unique command is completed, the reading of the second data is completed before the transmission of the security code is completed, and the control circuit When the mode is switched to the first mode or the second mode by reading, the mode is switched to the second mode and the unique command is transmitted from the reader / writer, and the transmitted ID and the IC tag The IC tag is characterized in that access to the second storage area is permitted when the ID of the second data matches and the read second data matches the transmitted security code.

[9] A circuit for generating a power supply voltage using power transmitted wirelessly from a reader / writer, etc., an internal power supply voltage is generated by converting the power supply voltage, and the value of the internal power supply voltage is based on trimming data An adjustable regulator circuit;

A voltage detection circuit that generates a detection signal when the internal power supply voltage reaches or exceeds a desired voltage level with the start of the operation of the regulator circuit; A clock recovery circuit for synchronizing an internal clock signal based on the transmitted synchronization signal;

 A nonvolatile memory provided with the internal power supply voltage and having a first storage area and a second storage area;

 An IC tag having a control circuit including an access control function for the nonvolatile memory,

 The IC tag is

 A first mode accessible only to the first storage area;

 A second mode accessible to the first storage area and the second storage area;

 The trimming data;

 Storing the first data for setting the first mode or the second mode, and the control circuit,

 After the voltage detection circuit generates the detection signal and before the synchronization of the internal clock signal by the clock recovery circuit is determined, the trimming data is read and reflected in the regulator circuit,

 The first data is read after the trimming data is read, and if the read first data is the same as the preset specific value, the process proceeds to the second mode, otherwise In the case of the IC tag, the mode is shifted to the first mode.

[10] The IC tag according to claim 9, further comprising:

 The reader / writer force has a signal detection circuit that outputs a detection signal when the first edge in the transmitted synchronization signal is detected,

 After the voltage detection circuit generates a detection signal and the signal detection circuit generates the detection signal, the trimming data is read from the nonvolatile memory before the synchronization of the internal clock signal by the clock recovery circuit is determined. An IC tag characterized by being read and reflected in the regulator circuit.

[11] In the IC tag according to claim 9 or 10, An address counter,

 The trimming data and the first data are stored in adjacent memory addresses in the nonvolatile memory,

 Reading the trimming data and the first data from the nonvolatile memory is performed continuously using the address counter.