JPH04330838A - Demodulating circuit in ask modulation system - Google Patents

Abstract

PURPOSE:To provide a demodulating circuit in an ASK modulation system by which an exact logical judgement can be always attained regardless of the fluctuation of a carrier frequency. CONSTITUTION:As for the demodulating circuit of a modulated wave in the ASK system, which turns ON/OFF the output signal of an oscillator according to digital information, and switches an oscillation period included in a constant cycle T to two kinds, the output of a counter 23 which counts the number of the carriers of the modulated wave included in the above mentioned cycle T is connected with a comparison judging circuit 24. The pertinent comparison judging circuit 24 prepares a reference count value being a judging reference for judging whether the present count value obtained by the counter 23 indicates which binary state of logical information, and also increases and decreases the pertinent reference count value according to the past count value, judges whether the present count value indicates which binary state based on the relation of a size between the present count value and the reference count value, and outputs the result.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention is an ASK (Amplifier) that turns on/off the output signal of an oscillator according to digital information.
This invention relates to an improvement of a demodulation circuit in a shift keying (shift keying) modulation method.

0002

[Prior Art] In recent years, in the field of FA, processes have been made more flexible and intelligent by introducing ID (identification) systems to identify the types of semi-finished products and finished products being moved within the factory, for example. Attempts are being made to respond to market needs (see ``Data Carrier Technology and Applications'' (published by Nikkan Kogyo Shimbun)). For example, as shown in FIG. 9, there are multiple workstations (8) (81) (82).
) and a conveyor line (80) that connects the workstations, each of the semi-finished products (9), (91), and (92) on the conveyor line (80) is equipped with a data memory (53). Data carrier (1
) while attaching each workstation (8) (8
1) (82) includes an R/W head (2) that writes and reads identification data to and from the data carrier (1).
), each R/W head (2) is connected to a programmable controller (6) via an ID controller (3), and the programmable controller (6) controls the operation of the assembly robots (83), (84), and (85). is controlled.

[0003] Data carrier (1) and R/W head (2)
) is performed based on electromagnetic coupling between coils (5) and (4) provided in the data carrier (1) and the R/W head (2), respectively, as shown in FIG. 10, for example. The coil (5) of the data carrier (1) has a modulation/demodulation circuit (5
1) and the memory (
53) is connected. On the other hand, a modulation/demodulation circuit (41) is connected to the coil (4) of the R/W head (2), and an oscillator (42) is connected to the modulation/demodulation circuit (41).

For example, the memory (
53), when reading the data written in
A read command output from the controller (3) is modulated by a modulation/demodulation circuit (41) and applied to the coil (4). As the modulation method, for example, an ASK method is adopted in which the output signal of the oscillator (42) is turned ON/OFF according to a digital signal from the ID controller (3). Figure 1
1(a) represents a modulation waveform in the ASK system. In the modulation signal SO that repeats ON/OFF at a constant period T, the period in which a carrier appears within each period T can be made to correspond to "1" when it is t1, and to be "0" when it is t2.

As shown in FIG. 10, due to electromagnetic coupling between the coil (5) of the data carrier (1) and the coil (4) of the R/W head (2), the coil (5) of the data carrier (1)
An induced electromotive force is generated in the coil (5), and the signal induced in the coil (5) is demodulated into the original digital signal in the modulation/demodulation circuit (51) and sent to the conversion/control circuit (52). Information is read out by the conversion/control circuit (52) from the memory address specified by the code in the sent signal. The read parallel signal is converted into a serial signal by a conversion/control circuit (52) and further modulated. The modulated signal is sent to the modulation/demodulation circuit (41) via the coils (5) and (4).
The signal is then demodulated into a digital signal and sent to the ID controller (3). The demodulation method is shown in Figure 1.
An envelope waveform shown in FIG. 11(b) is created based on the modulated waveform shown in 1(a), and the number of carriers of the modulated waveform within each high period of the waveform is counted. When it corresponds, it is judged as logic “1” and the period t
If it corresponds to 2, it is determined to be logical "0".

In the example shown in FIG. 9, a storage address for process confirmation information and a storage address for product type information are set in the memory (53) of the data carrier (1). At each workstation (8) (81) (82), a data carrier (
1) Product type information stored in the memory (53)
A” is read out, and based on that information the assembly robot (
83), (84), and (85) are performed. Thereafter, data indicating that the assembly at each workstation has been completed is sent to the data carrier (1) and the memory (53
), a completion flag "1" is set in a predetermined bit of the specified address.

[0007]

[Problem to be Solved by the Invention] However, in the ID system shown in FIG. 9, envelope detection is performed,
When measuring the periods t1, t2, etc. within each cycle T of the modulation signal SO and determining logic "1" or "0", a clock generation source is required in the data carrier (1), resulting in large power consumption. There is a problem with becoming. Therefore, in order to reduce the power consumption of the data carrier (1), the data carrier (1) does not include a clock generation source, and the demodulation circuit uses the modulated signal SO shown in FIG. 11(a) as described above. There is a method of determining logic "1" and "0" based on the number of carriers in each period T, but in this case, if the carrier frequency changes over time for any reason, there is a risk of incorrect logic determination. was there. Furthermore, since the modulation signal shown in FIG. 11 causes residual damped oscillation on the data carrier (1) side, errors in logic judgment occur due to this being counted.

[0008] An object of the present invention is to provide a demodulation circuit for ASK modulated waves that can always make accurate logic judgments regardless of carrier frequency fluctuations.

[0009]

[Means for Solving the Problem] As shown in FIG. 1, the demodulation circuit in the ASK modulation system according to the present invention
A means (A) for counting the number of carriers included in the /OFF period T, and which binary state (“0” or “1”) of the logical information is represented by the current count value obtained from the counting means. means (B) for outputting a reference count value that serves as a judgment criterion; means (C) for increasing or decreasing the reference count value according to the past count value by the counting means; It is provided with logic determining means (D) for determining which binary state the current count value represents based on the relationship and outputting the result as logical information.

0010

[Operation] For example, if the current count value by the counting means is CT
If the basic operation is to determine that when the value is 1 as logic "0" and when CT2 is determined as logical "1", a value of (CT1+CT2)/2 can be set as the initial value of the reference count value. In this case, the logic determining means determines that when the current count value is smaller than the reference count value, it is set to logic "0".
It is possible to determine that the current count value is greater than the reference count value as logic "1". By the way, when the carrier frequency of the modulated wave increases or decreases, or when residual damped oscillation occurs, the tendency is that the ON/Off of the modulated wave
Normally, it is continued for a period longer than the F period T. Therefore, if the current count value increases or decreases by 1 from the previous count value, for example, if the reference count value is also increased or decreased by 1 using the reference count value increase/decrease means in logical judgment regarding the current count value, the carrier frequency will be increased or decreased by 1. It is possible to reflect the fluctuations in logical judgments, thereby preventing errors in logical judgments.

[0011]

According to the demodulation circuit in the ASK modulation system according to the present invention, accurate logic judgment is always possible regardless of carrier frequency fluctuations or residual damped oscillations.

0012

[Example] Hereinafter, a demodulation circuit in the ASK modulation method according to the present invention will be described.
An example applied to 51) will be explained. It should be noted that the examples are for illustrating the present invention, and should not be construed as limiting the invention described in the claims or reducing its scope.

In this embodiment, the period T of the modulation signal shown in FIG. 11 is 100 μs, and the standard period t1 corresponding to logic “1” is
is 75 μs, and the standard time t2 corresponding to logic “0” is 50 μs.
The frequency is set to μs, and the carrier frequency is 500 KHz. Then, as the initial value of the reference count value, 3
3 is set.

In addition, in the circuit described below, if the count value immediately before the current count value for which a logical judgment is to be made is 15 or less, it is determined that the circuit operation is abnormal, and the reference count value is not changed with respect to the current count value. do not have. If the previous count value is 16 or more and 24 or less, the reference count value is fixed at 32, and when the current count value is less than 32, it is determined to be logic "0",
When the current count value is 32 or more, it is determined to be logical "1". Further, when the immediately preceding count value is 25, the reference count value is set to 33, and thereafter, the reference count value is also increased by one every time the immediately preceding count value increases by one. That is, when the previous count value is 26, the reference count value is set to 34,
When the previous count value is 27, the reference count value is set to 35. Thereafter, the reference count value is similarly increased in accordance with the increase in the immediately preceding count value, and when the immediately preceding count value is 31, the reference count value is set to 39.

[0015] If the previous count value is 32 or more,
The reference count value is fixed at 39. In addition, the range of the immediately preceding count value for which the reference count value should be changed is set from 25 to 31.
The reason why this is set is that in actual circuit operation, it is thought that within this range, the influence on logical judgment due to carrier frequency fluctuations and the generation of residual attenuation signals becomes significant. In the circuit of the embodiment, the reference count value for determining 1 in the next logical determination is set based on the count value when 0 is determined in the previous logical determination. Of course, the reverse is also possible.

FIG. 2 shows the overall configuration of the demodulation circuit section of the modulation/demodulation circuit (51), and the input signal shown in FIG.
An original signal obtained by clipping the modulation signal SO at a level of 0 or higher as shown in FIG. 11B, and the envelope signal shown in FIG. 11B are supplied. A counter (23) is used to count the number of carriers included in the ON/OFF period T of the modulated wave.
), and outputs a reference count value that serves as a criterion for determining which binary state (“0” or “1”) of the logical information the current count value obtained from the counter (23) represents. a means for increasing or decreasing the reference count value according to a past count value by a counter (23); and means for determining which binary state the current count value represents based on the magnitude relationship between the current count value and the reference count value. The logic judgment means for judging whether the data is true and outputting the result as logic information is constituted by a comparison judgment circuit (24) consisting of a logic circuit to be described later.

The original signal is supplied as a clock signal to a counter (23), the number of carriers within the period T is counted, and the count output, 6-bit data Q0 to Q5, is sent to a comparison judgment circuit (24). is being supplied to. In order to clear the counter (23) and the comparison/judgment circuit (24) every period T, first and second flip-flops (21) and (22) are provided, and the envelope signal is sent to the first flip-flop (21). supplied as a clock signal,
Its Q output is connected to a second flip-flop (22). Then, the inverted output of the second flip-flop (22) serves as a clear signal to the first flip-flop (21),
It is connected to a counter (23) and a comparison/judgment circuit (24).

FIG. 6 shows the first and second flip-flops (
21) (22) and the counter (23), the Q output of the first flip-flop (21) goes high in synchronization with the rise of the envelope signal shown in FIG. 6(a),
The second flip-flop (22) takes in the high output of the first flip-flop (21) as data in synchronization with the first falling edge of the original signal. As a result, the inverted output of the second flip-flop (22) becomes low, and the first flip-flop (21) is cleared. At the same time, Figure 6
The counter (23) is also cleared as shown in (c). As a result, the Q output of the first flip-flop (21) becomes low, and the second flip-flop (22) takes in the Q output of the first flip-flop (21) at the next falling edge of the original signal. Therefore, the inverted output of the second flip-flop (22) becomes high, and the counter clear signal becomes low as shown in FIG. 6(c). Further, the counter (23) executes a counting operation as shown in FIG. 6(d) by supplying the original signal.

FIGS. 3 to 5 show the comparison/judgment circuit (24)
It shows a specific configuration example of the pulse generation circuit (
The reference count value mentioned above is set by 70a), and a comparison is made with the output count value of the counter (23), and when the output count value matches the reference count value, one pulse of output PO is issued. It is. The pulse output PO is output by an output holding circuit (70c) shown in FIG.
and is outputted as the logic judgment output OUT for each period T. Further, the latch signal generation circuit (70b) shown in FIG. 4 is connected to the pulse generation circuit (70a), and the latch signal RT generated from the circuit controls the acquisition of the counter output when the previous count value is 16 or more. It is done.

The specific configuration of each circuit in FIGS. 3 to 5 will be explained below, and the operation of these circuits will be explained in detail in FIGS. 7 and 8.
The explanation will be given according to the time chart shown in . The outputs Q0 to Q5 of the counter (23) are connected as input signals to the pulse generation circuit (70a) in FIG. 3, and the latch signal R from the latch signal generation circuit (70b) in FIG.
T is supplied as a clock. Among the counter outputs, the lower three bits Q0 to Q2 correspond to the first to third A bits, respectively.
Through the ND circuits (25a) (25b) (25c) and the first to third OR circuits (26a) (26b) (26c),
First to third flip-flops (27a) (27b) (
27c). First to third flip-flops (27a) (27b) (27c)
are respectively connected to the latch signals, and their inverted outputs "R0, R1, R2" are connected to the first to third EX-ORs, respectively.
5th AND via circuits (28a) (28b) (28c)
It is connected to the circuit (29).

Further, the fourth and fifth bits Q3 and Q4 of the counter output are passed through the fourth AND circuit (25d) to the first
to the third AND circuits (25a), (25b), and (25c), and their inverted signals are connected to the fifth AND circuit (29). Furthermore, the sixth bit Q5 of the counter output is connected to the first to third OR circuits (26a).
(26b) and (26c), and the fifth AND
It is connected to the circuit (29).

In the latch signal generation circuit (70b) of FIG. 4, the inverted signal of the fifth bit Q4 of the counter output and the output of the sixth bit Q5 are output to the EX-OR circuit (7) and the A
It is connected to the data input terminal of a flip-flop (72) via an ND circuit (71). The flip-flop (72) also receives an inverted signal (C) of the envelope signal shown in FIG.
LK) is connected as a clock signal, and the inverted output (inverted C
LR) is connected as a clear signal. Further, the Q output of the flip-flop (72) and the inverted signal (CLK) of the envelope signal are connected to an AND circuit (73).

In the output holding circuit (70c) of FIG. 5, the pulse output PO shown in FIG. 3 is connected to the data input terminal of the flip-flop (75) via the OR circuit (74), and The inverted signal (CLK1) of the original signal shown in FIG. 2 is connected as a clock signal, and the inverted CLR signal is connected as a clear signal. The Q output of the flip-flop (75) is OR
The data is fed back to the circuit (74) to hold the data during the period T, thereby obtaining the logic judgment output OUT.

The operation of setting the reference count value according to the immediately preceding count value is performed by the pulse generating circuit (70a) shown in FIG.
Inside, mainly the first to third flip-flops (27a) (2
7b) and (27c), and the operation of detecting the point in time when the count value matches the reference count value in the process of counting up the current count value is performed by the first to third EX-
This is performed by OR circuits (28a) (28b) (28c) and a fifth AND circuit (29). In addition, in this embodiment, in the operating range in which the reference count value is increased or decreased according to the increase or decrease of the immediately preceding count value, the count-up is performed by utilizing the fact that the lower 3 bits of the immediately preceding count value match the lower 3 bits of the reference count value. In the process, the immediately preceding count value is used instead of the reference count value to be compared, and bit comparison is limited to the lower three bits to simplify the circuit. That is, the first to third flip-flops (27a) (27b) (27c) output the data of the lower three bits Q0 to Q2 of the counter output to the latch signal RT.
The signal is stored at the rising edge of , and the inverted signal is output from the inverted output terminal. In addition, the first to third EX-OR circuits (28a) (2
8b) (28c) are the first to third flip-flops (
27a), (27b), and (27c) (the inverted data of the data representing the reference count value) and the data of the lower 3 bits Q0 to Q2 of the counter output (the current count value) are determined, and in the case of a mismatch, the Yes and Q3, Q4
When Q5 is L and Q5 is H, it is recognized that the count value has passed the reference count value. In this case, the first to third EX-OR circuits (28a) (28b) (28c)
All outputs are 1.

The operation of not changing the reference count value and maintaining the previous reference count value when the previous count value is 15 or less is performed when both count outputs Q4 and Q5 are output in the latch signal generation circuit (70b) of FIG. 0, therefore the data to the flip-flop (72) becomes 0, and further A
This is done when the output of the ND circuit (73), that is, the latch signal RT becomes 0. As a result, the first
to third flip-flops (27a) (27b) (27
Since the clock signal to c) is stopped, these flip-flops maintain their previous values and no change in the reference count value takes place.

The operation of fixing the reference count value to 32 when the previous count value is 16 or more and 24 or less is performed in this range when the count output Q3 is 0 and Q4 is 1 in the pulse generation circuit (70a) of FIG. As a result, the first to third flip-flops (27a) (27b) (27c
) is always 0, and the data “R0, R
This is done by setting "1, R2" to "1, 1, 1", that is, the inverted value of the lower three bits ("0, 0, 0") when the count value is 32.

Furthermore, the operation of fixing the reference count value to 39 when the previous count value is 31 or more is performed when the count output Q4 is 0.
, Q5 becomes 1, and as a result, the first to third OR circuits (
The outputs of 26a) (26b) (26c) are always 1, and the first to third flip-flops (27a) (27b)
Data “R0,” output from the inverted output terminal of (27c)
R1, R2” are “0, 0, 0”, that is, the count value is 39
This is done by inverting the lower three bits (“1, 1, 1”) in the case of .

By the above operation, the counter (23)
When the count value during counting up matches the reference count value, all the inputs of the fifth AND circuit (29) in FIG. is the output holding circuit (70c) in Figure 5.
sent to. In this circuit, the output is connected to an OR circuit (
74) to the flip-flop (75), and is output from the Q output terminal in synchronization with the fall of the clock signal CLK1 (an inverted signal of the original signal). The output is held constant by the feedback loop passing through the OR circuit (74) until the counter clear signal (inverted CLR) shown in FIG. 6(c) is input, that is, the period T. .

For example, when the count value (current count value) of the original signal changes as shown in FIG. 7(a), when the current count value is 16 and the previous count value is 15, the first
to third flip-flops (27a) (27b) (27
The inverted outputs R0, R1, and R2 of (c) each become undefined values, and then, when the current count value becomes 16, the inverted outputs R0, R1, and R2 of FIG.
) The latch signal becomes 1 in response to the fall of the envelope signal shown in FIG. 7(d) (e
) As shown in (f), data setting of the inverted outputs R0, R1 and R2 of the first to third flip-flops and logic judgment based thereon are performed.

In the logical judgment when the current count value is 31 and the previous count value is 16, the inverted outputs R0, R1 and R2 are all 1 as described above, so the reference count value is set to 32. As a result, logical judgment output OUT
becomes 0 as shown in FIG. 7(d). Next, the current count value is 25
In this case, the inverted outputs R0, R1, and R2 are all 0, so the reference count value is set to 39, and as a result,
The logic judgment output OUT becomes 0. Furthermore, the current count value is 3
If it becomes 2, the inverted output R0 becomes 0 and R1 and R2 become 1, so the reference count value is set to 33, and as a result, the logic judgment output OUT becomes 0.

FIG. 8 shows the circuit operation when the current count value passes through 23 and then reaches 32. In this case, since the immediately preceding count value is 23, the inverted outputs R0, R1 and R
2 are all 1, and the reference count value is set to 32. Therefore, the counter is reset as shown in FIG. 8(d) by the counter reset signal shown in FIG. 8(c), and thereafter, the count-up is executed in synchronization with the rising edge of the original signal shown in FIG. 8(b). Ru. When the count value matches the reference count value of 32, the logic judgment output OUT becomes 1 due to the fall of the original signal, and the value of 1 is held until the next time the counter reset signal becomes high. . Then, when the current count value becomes 31 next time as shown in FIG. 7, the AND circuit (7
1) is set to the previous value of 1, the latch signal RT is not generated, and the inverted outputs R0, R1, and R2 in FIG. 3 maintain their previous values. Therefore, the reference count value remains 32, and the logic judgment output OUT for the current count value 31 becomes 0.

As described above, according to the demodulation circuit in the ASK modulation system according to the present invention, accurate logic judgment is always possible regardless of changes in carrier frequency, etc. 1) In an ID system that does not include a clock generation source within the data carrier (
It is extremely effective as a demodulation circuit (1). The above description of the embodiments is for illustrating the present invention, and should not be construed to limit or reduce the scope of the invention described in the claims. Further, it goes without saying that the configuration of each part of the present invention is not limited to the above-mentioned embodiments, and various modifications can be made within the technical scope of the claims.

For example, the demodulation circuit in the ASK modulation system according to the present invention can be applied not only to ID systems but also to various other data communication systems. It is also possible to implement the logic circuits shown in FIGS. 3 to 5 using microcomputer software.

[0034]

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a demodulation circuit in an ASK modulation method according to the present invention.

FIG. 2 is a block diagram showing an example in which the present invention is applied to an ID system.

FIG. 3 is a block diagram of a pulse generation circuit forming the circuit of FIG. 3;

FIG. 4 is a block diagram of a latch signal generation circuit forming the circuit of FIG. 3;

FIG. 5 is a block diagram of an output holding circuit that constitutes the circuit of FIG. 3;

6 is a time chart showing counter clear and count up operations of the circuit in FIG. 2; FIG.

FIG. 7 is a time chart showing the circuit operation of FIGS. 3 to 5;

FIG. 8 is a time chart showing an enlarged part of FIG. 7;

FIG. 9 is a diagram showing the overall configuration of the ID system.

FIG. 10 is a block diagram showing an electromagnetic coupling state between a data carrier and a head.

FIG. 11 is a waveform diagram of a modulation signal, an envelope signal, and an original signal.

[Explanation of sign]

(51) Modulation/demodulation circuit (23) Counter (24) Comparison judgment circuit (70a) Pulse generation circuit (70b) Latch signal generation circuit (70c) Output holding means

Claims (1)

[Claims] Claim 1: A modulated wave representing binary logical information is converted to the original by turning the output signal of an oscillator ON/OFF according to digital information and switching the oscillation period included within a constant period T between two types. In the circuit that demodulates digital information,
A means for counting the number of carriers of the modulated wave included in the period T, and outputting a reference count value serving as a criterion for determining which binary state of logical information the current count value obtained from the counting means represents. means for increasing or decreasing the reference count value according to a past count value of the counting means; and means for determining which binary state the current count value represents based on the magnitude relationship between the current count value and the reference count value. 1. A demodulation circuit in an ASK modulation system, characterized in that the demodulation circuit comprises logic determination means for determining whether or not a signal is present, and outputting the result as logical information.