JPS63227144A - Synchronization detecting system - Google Patents

Abstract

PURPOSE:To suppress a bit shift in a central arithmetic unit to the minimum by providing a circuit comparing a received data with a data value '0' between a serial/parallel converting circuit and a central processor. CONSTITUTION:A data received from a transmission line 1 is converted to a bit train by a demodulating circuit 2, and also, converted to the data of 8 bits by a serial/parallel converting circuit 3. A comparator 7 compares the received data of 8 bits with the value of an 8-bit register 8 storing '0' in all of each bit, and when they coincide, it becomes a fact that 8 pieces of bits '0' are received continuously, and a synchronization detecting counter 6 is added with 8. A central arithmetic unit 4 processes the received data in accordance with the comparing output.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a telemeter/telecontrol system that transmits signals via a communication line using a cyclic digital information transmission method, and particularly relates to a synchronous detection method for cyclic digital information. Regarding.

[Conventional technology]

The conventional technique will be explained using FIG. The transmission format data (hereinafter referred to as the cyclic digital transmission format of the Institute of Electrical Engineers of Japan method) based on the cyclic digital information transmission equipment specification standards published by the Institute of Electrical Engineers of Japan Communication Expert Committee obtained from the transmission line 1 through the demodulation circuit 2 is as follows: The serial-parallel conversion circuit 3 passes the data to the central processing unit 4 in units of a certain number of bits (usually 8 bits - 1 byte). The central processing unit 4 temporarily saves the data passed to the shift register 5 constituted by a random access memory in order to edit the received data and detect a synchronization word.

The synchronization word has the configuration shown in FIG. 4, and is detected by counting successive bits of 0. Conventionally, the flow shown in FIG.゜302) If it is “O”, increase the synchronization detection counter 6 by 1 Steps 303, 304)
If it is 1, compare the value of the synchronization detection counter 6 with the number of consecutive 0 bits of the synchronization word, that is, the number of bits per word - 2.Slap 305) When they match, detect synchronization Step 306) , the synchronization detection counter 6 was cleared (step 307).

[Problem that the invention seeks to solve]

In the above-mentioned conventional technology, the received data must always be checked bit by bit to check for synchronization words, which are not transmitted very often, which places a heavy load on the central processing unit.

Particularly when the central processing unit has low capability or the transmission speed is high, most of the load on the central processing unit is due to this synchronization detection.

[Means for solving problems]

The present invention has a function of minimizing bit shifts in the central processing unit by newly inserting a comparison circuit that compares received data with a data value of 0 between the serial-parallel conversion circuit and the central processing unit.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment in which the method of the present invention is applied to a device that receives data in the 44-bit/1-word cyclic digital transmission format of the Institute of Electrical Engineers of Japan method and converts it from serial to parallel in 8-bit units. be. 4
In the case of 4 bits/word, the synchronization word consists of 42 consecutive zero bits as shown in FIG.

Data received through the transmission path 1 is converted into a bit string by a demodulation circuit 2, and further converted into 8-bit data by a serial-parallel conversion circuit 3.

Comparison circuit 7 compares the serial-parallel converted 8-bit received data with the value of 8-bit register 8 in which 0°' is stored in all bits, and if they match, 8 consecutive data are Since bit 0 has been received, the synchronization detection counter 6 is set to +8. The central processing unit 4 receives the output of the comparison circuit 7 and processes the received data according to the flow shown in FIG. In step 201, it is determined whether OO is detected by the comparison circuit 7 of FIG. 1, and if it is determined that OO is not detected, 1. In step 202, it is determined whether the 8-bit data received includes the last bit 1 of the synchronization word based on the current value of the synchronization detection counter 6 in FIG. In other words, since the received data may contain up to 7 bits of bit 0, if the value of the synchronization detection counter 6 is "35" or more, this data may be used to detect the end of the synchronization word. it is conceivable that. In step 205, the shift register 5 is used to count bit 0 of the data just received by bit shifting from the upper order until bit 1 appears, and in step 206, the result is added to the synchronization detection counter 6. Further, in step 207, the updated value of the synchronization detection counter 6 is compared with the value "42", and if they are equal, it means that a synchronization word has been detected. (Step 208). Further, if the value of the synchronization detection counter 6 is 43" or more, it is assumed that invalid data has been received, and error processing in step 209 is performed. In step 202, the synchronization detection counter 6 is
If it is determined that the value of the synchronization detection counter 6 is less than "35", or if the value of the synchronization detection counter 6 is less than "42" in step 207, the data is other than the synchronization word or the first bit 1 of the synchronization word is It is considered to be data containing,
If synchronization is detected (step 208), in order to detect the next synchronization word, the shift register 5 sets bit 0 from the lower bit of the received data as a clock (step 203), and sets the count value in the synchronization detection counter 6. The process is repeated (step 204), and the processing of the 8-bit data is completed.

〔Effect of the invention〕

In the flow explained above, when receiving information words that make up most of the transmitted data, bit 0 is counted starting from the lower bit, but since the possibility of bit 0 continuing is relatively low, bit 0 by bit shift
count decreases considerably. Further, in the case of synchronous word reception, since OO that lasts 4 to 5 bytes is counted by the comparator circuit, bit shifting becomes unnecessary during that time. These advantages have the effect of significantly reducing the load on the central processing unit.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a specific device that receives data in accordance with the 44-bit/1-word cyclic digital transmission format of the Institute of Electrical Engineers of Japan system using the method of the present invention, and FIG. 2 is a block diagram showing an embodiment of the present invention. A flowchart showing an example of the flow of synchronization detection processing according to the method, FIG. 3 is an explanatory diagram of the synchronization detection method according to the conventional method, FIG. 4 is a configuration diagram of a synchronization word in the cyclic digital transmission method of the Institute of Electrical Engineers of Japan method, The figure is a flowchart showing an example of a synchronization detection processing flow according to a conventional method. DESCRIPTION OF SYMBOLS 1... Transmission line, 2... Demodulation circuit, 3... Serial-parallel conversion circuit, 4... Central processing unit, 5...
Shift Figure 3 Figure 4

Claims (1)

[Claims] In the synchronization detection method of the cyclic digital transmission method of the Institute of Electrical Engineers of Japan method, after converting the received serial data to predetermined parallel data, by checking whether all the converted parallel bits are 0 or not. A synchronization detection method characterized by counting a string of consecutive bits 0 accompanying a synchronization word.