JPS63227053A - Semiconductor photodetector - Google Patents
Semiconductor photodetectorInfo
- Publication number
- JPS63227053A JPS63227053A JP62061542A JP6154287A JPS63227053A JP S63227053 A JPS63227053 A JP S63227053A JP 62061542 A JP62061542 A JP 62061542A JP 6154287 A JP6154287 A JP 6154287A JP S63227053 A JPS63227053 A JP S63227053A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- light
- section
- stepped
- inp layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 8
- 239000000758 substrate Substances 0.000 claims description 6
- 230000031700 light absorption Effects 0.000 claims description 5
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 claims description 3
- 238000000926 separation method Methods 0.000 claims description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 2
- 238000005530 etching Methods 0.000 abstract description 7
- 238000002955 isolation Methods 0.000 abstract description 3
- 230000002093 peripheral effect Effects 0.000 abstract description 2
- 239000011347 resin Substances 0.000 abstract description 2
- 229920005989 resin Polymers 0.000 abstract description 2
- 230000002950 deficient Effects 0.000 abstract 2
- 238000007493 shaping process Methods 0.000 abstract 1
- 210000003128 head Anatomy 0.000 description 11
- 238000000034 method Methods 0.000 description 7
- 230000007547 defect Effects 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- 230000003287 optical effect Effects 0.000 description 3
- 150000001875 compounds Chemical class 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- VEXZGXHMUGYJMC-UHFFFAOYSA-M Chloride anion Chemical compound [Cl-] VEXZGXHMUGYJMC-UHFFFAOYSA-M 0.000 description 1
- 101000690484 Leptodactylus fallax Aggression-stimulating peptide Proteins 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 239000011324 bead Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 210000004709 eyebrow Anatomy 0.000 description 1
- 150000004820 halides Chemical class 0.000 description 1
- 125000005842 heteroatom Chemical group 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 230000005693 optoelectronics Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/1443—Devices controlled by radiation with at least one potential jump or surface barrier
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Electromagnetism (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Solid State Image Pick-Up Elements (AREA)
- Light Receiving Elements (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は半導体受光素子に関し、化合物半導体から成る
受光素子を含んだ集積回路、特に光集積回路に適したも
のである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor light-receiving element, and is suitable for integrated circuits, particularly optical integrated circuits, including a light-receiving element made of a compound semiconductor.
従来の技術
従来のＩｎＧａＡｓＰ／ＩｎＰ系半導体受光素子は、第
２図に示すように、半絶縁性ｎＰ基板上にＬｐｘ成長で
成長した、ｎ −−ＩｎＧａＡｇ層２、ｎ″″−ＩｎＧ
ａＡｓＰ層３、ｎ−Ｐ層Ｐ層４、Ｐ −ＩｎＧａＡｓＰ
層６、ｎ Ｐ層ＩｎＰ層６の多層エピタキシャル基板に
、ｎ−Ｐ−ｎ接合型のへテロバイポーラトランジスタ（
ＨＢＴ）部７と、Ｐｉｎ受光部８を形成したものである
。ＨＢＴ部７は，ベースとなるＩｎＧａＡｓＰ層６にグ
ラフトベース１３を、拡散によシＰ型領域として形成し
、電極９をｎ−ＩｎＰ層６エミツタ、ｎ−１ｎＰ層４コ
レクタ同様に形成している。受光部８では、ＬＰｇ成長
によりＩｎＧａＡｇ 層上ＩｎＰ層を成長する際に、Ｉ
ｎＧａＡｓがＩｎＰ成長用溶液に溶融しないように形成
するアンチメルトバック層のＩｎＧａムｓＰ層３までエ
ツチングを施し、受光部のみにＰ型頭域１ｏを形成し、
Ｐｉｎ−７オトダイオード（Ｐｉｎ −ＦＤ ）とする
ものである。このように半絶縁性ＩｎＰ基板１上に集積
化したＰｉｎ −ＰＩ）とＨＢＴは絶縁物で埋込まれた
分離溝１１により分離されているが、配線電極１２はこ
の段差上に形成しなくてはならない。この段差上への配
線は、配線パターン形成上また配線自体の段切れ等のた
め不良を起し易く、歩留り低下の大きな問題であった。2. Description of the Related Art A conventional InGaAsP/InP-based semiconductor light-receiving device is made of an n--InGaAg layer 2, an n''''-InG layer 2 grown by Lpx growth on a semi-insulating nP substrate, as shown in FIG.
aAsP layer 3, n-P layer P layer 4, P-InGaAsP
Layer 6, nP layer InP layer 6 multilayer epitaxial substrate has an n-P-n junction type hetero bipolar transistor (
HBT) section 7 and a pin light receiving section 8 are formed. In the HBT section 7, a graft base 13 is formed as a P-type region by diffusion on an InGaAsP layer 6 serving as a base, and an electrode 9 is similarly formed as an emitter of an n-InP layer 6 and a collector of an n-1nP layer 4. . In the light receiving section 8, when growing the InP layer on the InGaAg layer by LPg growth, the I
Etching is performed up to the InGamsP layer 3, which is an anti-meltback layer formed to prevent nGaAs from melting in the InP growth solution, and a P-type head region 1o is formed only in the light receiving area.
This is a Pin-7 autodiode (Pin-FD). Although the Pin-PI (Pin-PI) and HBT integrated on the semi-insulating InP substrate 1 are separated by the isolation trench 11 filled with an insulator, the wiring electrode 12 must not be formed on this step. Must not be. Wiring over this step is likely to cause defects due to the formation of the wiring pattern or breakage of the wiring itself, which has been a major problem in reducing yield.
発明が解決しようとする問題点
従来の例によれば、受光素子とＨＢＴ等電気素子の集積
化において、前記素子構造上のため２素子間のエピタキ
シャル層の構造による段差が大きく、そのために配線電
極等のパターン形状を光学的工程で形成する事の難しさ
等により、段切れを生じ易く、歩留りを著しく低下させ
るものであった。そのため、前記の素子においては、受
光素子とＨＢＴ等電気素子間のエピタキシャル層の構造
による段差を低減させなければならない。Problems to be Solved by the Invention According to the conventional example, when integrating a light receiving element and an electric element such as an HBT, there is a large step difference due to the structure of the epitaxial layer between the two elements due to the element structure, and therefore the wiring electrode Due to the difficulty of forming such a pattern shape by an optical process, step breakage is likely to occur, which significantly reduces the yield. Therefore, in the above device, it is necessary to reduce the level difference due to the structure of the epitaxial layer between the light receiving element and the electric element such as the HBT.
問題点を解決するための手段
本発明は前述の問題点を解決するために、集積化する受
光素子と電気素子において、受光部のみをエツチングに
より露出させ、Ｐ型頭域をエツチング段差側面及び受光
部とその周囲に渡り形成し、受光素子のＰ型電極をエツ
チング部分周囲のＰ型頭域に形成し、電気素子との配線
を容易にするものである。Means for Solving the Problems In order to solve the above-mentioned problems, the present invention aims to expose only the light-receiving part by etching in the light-receiving element and electric element to be integrated, and etching the P-shaped head area and removing the step side surface and the light-receiving part. The P-type electrode of the light-receiving element is formed in the P-type head area around the etched part to facilitate wiring with electric elements.
作用
本発明によれば、集積化する受光素子と電気素子間の段
差、特に配線電極間の段差を低減する事が可能であり、
段差上の配線電極の断線による不良を低減するものであ
る。また受光素子部分は、必要なエピタキシャル層まで
露出させる事が可能であシ、Ｐ型頭域を例えば表面から
深く拡散する必要がなく、Ｐ型頭域の膜厚を薄くし最適
化する事が可能であり、Ｐ型頭域中の光入力によるキャ
リアの移動の拡散速度に起因する部分が低減でき、高速
化を可能とするものである。また、ｐ −ｎ接合は光吸
収のためのバンドギャップが狭い領域でなく、受光部周
辺の光吸収領域よりバンドギャップの大きい層上に形成
する事が可能となり、受光素子の暗電流を低減する事が
可能である２、実施例
本発明の一実施例を第１図を用いて説明する。According to the present invention, it is possible to reduce the level difference between the integrated light receiving element and the electric element, especially the level difference between the wiring electrodes,
This reduces defects caused by disconnection of wiring electrodes on steps. In addition, the light-receiving element part can be exposed to the required epitaxial layer, and there is no need to diffuse the P-type head region deeply from the surface, making it possible to thin and optimize the film thickness of the P-type head region. It is possible to reduce the portion of carrier movement caused by the diffusion speed due to optical input in the P-type head region, making it possible to increase the speed. In addition, the p-n junction can be formed not on a region with a narrow bandgap for light absorption, but on a layer with a larger bandgap than the light absorption region around the light-receiving part, which reduces the dark current of the light-receiving element. 2. Embodiment An embodiment of the present invention will be described with reference to FIG.
第１図は、ＩｎＧａＡｓ／ＩｎＰ 系の半導体受光素
子の断面図である。半絶縁性ＩｎＰ 基板１上に、Ｌ
ＰＫ成長によって形成されたｎ−−ＩｎＧａＡｇ 層
２ 、 ｎ−−ＩｎＧａＡｓＰ 層３．ｎ−ＩｎＰ層
４．Ｐ−ＩｎＧａＡＳＰ層（ＩｎｘＧａ、−ｘＡ＋ｓｙ
Ｐ、−ｙ：Ｏ≦Ｘ≦１．０≦ｙ≦１）５．ｎ−ＩｎＰ層
６の多層構造において、電気素子であるＨＢＴ７と受光
素子であるＰｉｎ−ＰＤ１４からなる受光素子と電気素
子を集積化したものである。電気素子であるＨＢＴ７は
、エミッタであるｎ−ＩｎＰ層６、ベースであるＰ −
ＩｎＧａＡＳ Ｐ層５、コレクタであるｎ−ＩｎＰ層４
からなり、ベースの電極はＺｎ拡散によりグラフトベー
ス１３を形成した後、形成する。受光素子部は、ｎ−Ｉ
ｎＰ層４の表面までエツチングしたのち、Ｐｉｎ −Ｐ
Ｄの受光部１６のみｎ−ＩｎＰ層４をエツチングしてｎ
−ＩｎＧａＡｓＰ層３を露出させ受光部１６及び周辺部
のｎ −ＩｎＰｎ感層にＰ型頭域１６をＺｎ拡散等で形
成し、電極９をｎ−ＩｎＰｎ感層のＰ型頭域に形成する
。FIG. 1 is a sectional view of an InGaAs/InP semiconductor light receiving element. On the semi-insulating InP substrate 1, L
n--InGaAg layer 2, n--InGaAsP layer 3 formed by PK growth. n-InP layer 4. P-InGaASP layer (InxGa, -xA+sy
P, -y: O≦X≦1.0≦y≦1)5. In the multilayer structure of the n-InP layer 6, a light-receiving element consisting of an HBT 7 as an electric element and a Pin-PD 14 as a light-receiving element and an electric element are integrated. The HBT 7, which is an electric element, has an n-InP layer 6 as an emitter and a P-InP layer 6 as a base.
InGaAS P layer 5, collector n-InP layer 4
The base electrode is formed after the graft base 13 is formed by Zn diffusion. The light receiving element part is n-I
After etching to the surface of the nP layer 4, Pin-P
The n-InP layer 4 is etched only in the light-receiving part 16 of D.
The -InGaAsP layer 3 is exposed and a P-type head region 16 is formed in the light receiving part 16 and the n-InPn sensitive layer in the peripheral area by Zn diffusion, etc., and an electrode 9 is formed in the P-type head region of the n-InPn sensitive layer.
電気的なｐｉｎ−ＰＤ１４とＨＢＴｙの分離は、溝を形
成し絶縁物例えばＳｉＯ□、 Ｓｉ３Ｎ４．絶縁性樹脂
で埋込んだ、分離溝１１を形成する。Electrical isolation between pin-PD14 and HBTy is achieved by forming a trench and using an insulator such as SiO□, Si3N4. A separation trench 11 filled with insulating resin is formed.
Ｐｉｎ−ＰＤ１３とＨＢＴ７の配線電極１３は、ベース
及びエミッタの段差すなわちｎ−ＩｎＰ層５ 、 ｐ
−ＩｎＧ！ＬＡＳＰ層５の膜厚の段差であり、ベース、
エミッタ、コレクタ間の配線電極と同じ段差となり、段
差による段切れ等の不良は低減する。The wiring electrode 13 of the Pin-PD 13 and the HBT 7 has a step between the base and the emitter, that is, the n-InP layer 5, p
-InG! This is a step in the film thickness of the LASP layer 5, and the base,
The difference in level is the same as that of the wiring electrode between the emitter and the collector, and defects such as breakage due to the difference in level are reduced.
受光素子のＰＩｎ−ＰＤ１３の露出するＰ−ｎ接合は、
ｎ−ＩｎＰｎ感層に形成されＩｎＧａＡｓ やＩｎＧ
ａＡｓＰよりバンドギャップの大きいところでのＰ −
ｎ接合である事から、暗電流が低減するものである。ま
た受光部１６のＰ型頭域１６の厚さは、ｎ−ＩｎＧＩＬ
ＡｊｉＰ層３の膜厚が最低必要であるが、ｎ−ＩｎＧａ
Ａｓ＋Ｐ層３Ｌ／ｉ、０．１〜０．３μｍ程度でありＰ
ｉｎ−ＰＤ１４の量子効率、高速動作を考慮した設計が
容易に行なえ、最適化が可能である。The exposed P-n junction of PIn-PD13 of the light receiving element is
Formed on the n-InPn sensitive layer, InGaAs and InG
P − where the bandgap is larger than that of aAsP
Since it is an n-junction, dark current is reduced. The thickness of the P-type head region 16 of the light receiving section 16 is n-InGIL.
Although the minimum thickness of the AjiP layer 3 is required, n-InGa
As+P layer 3L/i, about 0.1 to 0.3 μm and P
Design that takes quantum efficiency and high-speed operation of the in-PD 14 into consideration can be easily performed and optimization possible.
これらの素子構造を本実施例ではＬＰｇ法によるもので
あるが、これは他の成長方法によるもの例えば、ｖｐｇ
法（ハライドライド系、クロライド系）やＭＯＶＰＩＣ
法、ＭＢＫ法でも同様であり、これらの成長方法による
化合物半導体例えばＧａＡｄＡｓ／ＧａＡＳ系等にも容
易に適用が可能なものである。In this example, these device structures were formed using the LPg method, but they could also be formed using other growth methods, such as vpg.
method (halide-based, chloride-based) and MOVPIC
The same applies to the MBK method and the MBK method, and it can be easily applied to compound semiconductors such as GaAdAs/GaAS based using these growth methods.
発明の効果
本発明によれば、受光素子としてのＰｉｎ−ＰＤと電気
素子としてのＨＢＴ等を集積化する際の、エピタキシャ
ル多層構造と素子構造からなる素子間の段差を小さくで
き、段差による配線電極の断線による不良を低減できる
ものである。また受光素子であるＰｉｎ−ＰＤの露出す
るＰ −ｎ接合を、受光のだめの光吸収層よりバンドギ
ャップの大きい層で形成することができ、暗電流の低減
が可能である。それに伴う受光部のＰ型頭域も光吸収層
上のエピタキシャル層が０〜０．３μｍであるので、量
子効率や高速動作を考慮したＰ型頭域の厚さが選択でき
、素子特性の最適化が容易に可能となるものである。こ
のように、本発明は高性能、高歩留りの０ＫＩＣ（光電
子集積回路）の生産には欠くことのできないものである
。Effects of the Invention According to the present invention, when integrating a Pin-PD as a light-receiving element and an HBT as an electric element, it is possible to reduce the difference in level between elements consisting of an epitaxial multilayer structure and an element structure, and the wiring electrode due to the difference in level can be reduced. It is possible to reduce defects due to wire breakage. Furthermore, the exposed P-n junction of the Pin-PD, which is a light receiving element, can be formed of a layer having a larger band gap than the light absorption layer of the light receiving element, and dark current can be reduced. Since the epitaxial layer on the light absorption layer is 0 to 0.3 μm in the P-type head area of the light-receiving part, the thickness of the P-type head area can be selected in consideration of quantum efficiency and high-speed operation, and the device characteristics can be optimized. It is possible to easily change the As described above, the present invention is indispensable for the production of high-performance, high-yield OKICs (optoelectronic integrated circuits).
第１図は本発明の一実施例における半導体受光素子を含
んだ集積回路装置の断面図、第２図は従来の集積回路装
置の断面図である。
１・・・・・・半絶縁性ＩｎＰ基板、２・・・・・・ｎ
”’−ＩｎＧａＡｇ層、３ 、、、 、、、 ｎ−−
ＩｎＧｉＬＡＪ Ｐ層、４−−−−−−ｎ−ＩｎＰ層、
ｓ −−−−−−Ｐ −Ｉ ｎＧａＡｓ Ｐ層、６−−
−−−− ｎ −ＩｎＰ層、７・・・・・・ＨＢＴ、９
・・・・・・電極、１１・・・・・・分離溝、１２・・
・・・・配線電極、１４・・・・・・Ｐｉｎ−ＰＤ、１
５・・・・・・受光部。
代理人の氏名 弁理士 中 尾 敏 男 ほか１名ｌ
−牛ｉｔ Ｍ ＆ Ｉ ｎ Ｐ基板２− ｎ−−Ｉｎ
ＧａＡｓ層
３ ”’−ｎ−−ＩｎＧａＡｓＰ層
４．６ ｎ−１ｎＰＪ１
５ Ｐ −１ｎＧｃＡｓ Ｐ眉
７＝ＨＢ丁
９−ｔ ｍ
！！−分曖遣
１２−配線を撮
１３−クラフトベース
７４−− Ｐｉｎ−ＰＤ
１６− 受光部
／−１縁性ｉｎＰ嘉扶
２ °−ｎ−Ｉｎ（ｚａＡｓ層
３−ｎ”−ＩｎＧａＡｓＰ層
４ ｎ−ＩｎＰ層
５ Ｐ−ｆｎＧｃＡｓＰ層
−Ｈ８Ｔ
８Ｐｉｎ−ＰＤ
？〜 ｔ 極
１ｏ −Ｐ ’Ｉ ｎｌ ｍ。
１１−−一 分 βツ１＝ ２１票；。
１２−配珠電極FIG. 1 is a sectional view of an integrated circuit device including a semiconductor light receiving element according to an embodiment of the present invention, and FIG. 2 is a sectional view of a conventional integrated circuit device. 1...Semi-insulating InP substrate, 2...n
”'-InGaAg layer, 3, , , , n--
InGiLAJ P layer, 4-------n-InP layer,
s -------P -I nGaAs P layer, 6--
----- n-InP layer, 7...HBT, 9
... Electrode, 11 ... Separation groove, 12 ...
...Wiring electrode, 14...Pin-PD, 1
5... Light receiving section. Name of agent: Patent attorney Toshio Nakao and 1 other person
-Cow it M&InP board 2-n--In
GaAs layer 3 ''-n--InGaAsP layer 4.6 n-1nPJ1 5 P -1nGcAs P eyebrow 7=HBcho9-t m !!-Bunfu 12-Picture the wiring 13-Craft base 74--Pin -PD 16- Light receiving part/-1 related inP Kafu 2 °-n-In(zaAs layer 3-n''-InGaAsP layer 4 n-InP layer 5 P-fnGcAsP layer-H8T 8Pin-PD ? ~ t pole 1o -P'I nl m. 11--One minute βtsu1=21 votes;. 12-Bead array electrode
Claims (1)
ＧａＡｓ層，コレクタ用の第１の導電型ＩｎＰ層，ベー
ス用の第２の導電型ＩｎＧａＡｓＰ層，エミッタ用の第
１の導電型ＩｎＰ層を有し、前記表面からの３層により
ヘテロ接合バイポーラトランジスタが形成され、分離領
域を介して前記第１の導電型ＩｎＧａＡｓ層までの露出
がなされ、その段差周囲にＰ−ｎ接合と電極を形成して
いる受光部を有してなる半導体受光素子。A first conductivity type In for light absorption is formed on a semi-insulating InP substrate.
It has a GaAs layer, a first conductivity type InP layer for the collector, a second conductivity type InGaAsP layer for the base, and a first conductivity type InP layer for the emitter, and the three layers from the surface form a heterojunction bipolar transistor. A semiconductor light-receiving element comprising a light-receiving section in which a P-n junction and an electrode are formed around the step, in which the first conductivity type InGaAs layer is exposed through a separation region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62061542A JPS63227053A (en) | 1987-03-17 | 1987-03-17 | Semiconductor photodetector |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62061542A JPS63227053A (en) | 1987-03-17 | 1987-03-17 | Semiconductor photodetector |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63227053A true JPS63227053A (en) | 1988-09-21 |
Family
ID=13174105
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62061542A Pending JPS63227053A (en) | 1987-03-17 | 1987-03-17 | Semiconductor photodetector |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63227053A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02231775A (en) * | 1989-03-03 | 1990-09-13 | Fujitsu Ltd | Compound semiconductor photodetector |
| EP0392480A2 (en) * | 1989-04-12 | 1990-10-17 | Sumitomo Electric Industries, Ltd. | Method of manufacturing a semiconductor integrated circuit device |
| JPH03185771A (en) * | 1989-12-14 | 1991-08-13 | Hikari Keisoku Gijutsu Kaihatsu Kk | Photodetective element |
| JPH0492479A (en) * | 1990-08-07 | 1992-03-25 | Hikari Keisoku Gijutsu Kaihatsu Kk | Photodetector |
| KR100430860B1 (en) * | 2000-06-07 | 2004-05-10 | 샤프 가부시키가이샤 | Circuitcontaining photodetector, method of manufacturing the same, and optical device using circuitcontaining photodetector |
| WO2010041756A1 (en) * | 2008-10-10 | 2010-04-15 | 独立行政法人産業技術総合研究所 | Light-sensing element |
-
1987
- 1987-03-17 JP JP62061542A patent/JPS63227053A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02231775A (en) * | 1989-03-03 | 1990-09-13 | Fujitsu Ltd | Compound semiconductor photodetector |
| EP0392480A2 (en) * | 1989-04-12 | 1990-10-17 | Sumitomo Electric Industries, Ltd. | Method of manufacturing a semiconductor integrated circuit device |
| JPH03185771A (en) * | 1989-12-14 | 1991-08-13 | Hikari Keisoku Gijutsu Kaihatsu Kk | Photodetective element |
| JPH0492479A (en) * | 1990-08-07 | 1992-03-25 | Hikari Keisoku Gijutsu Kaihatsu Kk | Photodetector |
| KR100430860B1 (en) * | 2000-06-07 | 2004-05-10 | 샤프 가부시키가이샤 | Circuitcontaining photodetector, method of manufacturing the same, and optical device using circuitcontaining photodetector |
| WO2010041756A1 (en) * | 2008-10-10 | 2010-04-15 | 独立行政法人産業技術総合研究所 | Light-sensing element |
| US8530933B2 (en) | 2008-10-10 | 2013-09-10 | National Institute Of Advanced Industrial Science And Technology | Photo transistor |
| JP5386764B2 (en) * | 2008-10-10 | 2014-01-15 | 独立行政法人産業技術総合研究所 | Photodetector |
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