JPS63224512A - Digital signal processor - Google Patents

Abstract

PURPOSE:To attain the quick change of a parameter without intermitting the signal processing by applying a signal outputted from a signal processing means in a cross-fade mode to a signal inputted to the said means to change the parameter of the said means. CONSTITUTION:A coefficient A of a multiplier 15 is set to '1' and a coefficient B of a multiplier 17 is set to '0' at the normal operation, and in being subject to a prescribed signal processing at a digital processing circuit DSP, a digital signal from an input terminal 1 is extracted at an output terminal 18 via a multiplier 15 and an adder 16. From the state as above, operation starts to apply an output signal S1 of the DSP in a cross-fade (period T1) to a signal S2 inputted to a multiplier 17 from the terminal 1. When a 1st operation is finished, only the signal S2 is outputted to the terminal 18. Each parameter of the DSP is changed during this time. When the change of each parameter of the DSP is finished, a 2nd operation applying cross-fade of the signal S2 to the signal S1 is brought. After the 2nd operation is finished, the signal S2 is made zero and the state enters the normal operation where the signal S2 is made zero, and only the signal S1 is outputted to the terminal 18.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital signal processing device suitable for use when changing many parameters of signal processing equipment.

[Summary of the invention]

The present invention provides cross-fade means for cross-fading a digital signal input to the signal processing means and a digital signal output from the signal processing means, and converts the digital signal output from the signal processing means into the digital signal input to the signal processing means. By changing the parameters of the signal processing means after cross-fading, the parameters can be changed without interrupting signal processing and with noise suppressed.

[Conventional technology]

In signal processing equipment that handles digital signals, its parameters may be changed.

Conventionally, when changing many parameters, it was done as follows. That is, the first method is to enter minting once, change parameters, and then turn off muting.

The second method is to directly change the parameters.

[Problem that the invention seeks to solve]

However, the first method described above has the drawback that signal processing is interrupted during muting.

Furthermore, the second method has the disadvantage that noise may occur when the parameters change significantly.

The present invention has been made in view of these points, and an object thereof is to provide a digital signal processing device that can suppress noise to a low level without interrupting signal processing.

[Means for solving problems]

The digital signal processing device according to the present invention includes a signal processing means DSP to which a digital signal is input, and a cross-fade means for cross-fading the digital signal input to the signal processing means DSP and the digital signal output from the signal processing means DSP. (15 to 17), and is configured to change the parameters of the signal processing means DSP after crossfading the digital signal output from the signal processing means DSP to the digital signal input to the signal processing means DSP. .

[Effect]

The digital signal input to the signal processing means (L) SP by the cross-fade means (15 to 17) and the signal processing means (D)
Crossfade the digital signal output from SP. That is, in the first operation mode, the signal processing means DSP
gradually narrowing down the digital signal output from the signal processing means DSP and increasing the digital signal input to the signal processing means DSP,
In the second operation mode, the digital signal input to the signal processing means DSP is gradually reduced, and the signal output from the signal processing means DSP is increased. After the first operation mode, that is, after crossfading the digital signal output from the signal processing means DSP to the digital signal input to the signal processing means, the multiplication coefficient, the number of delay samples, the type of ROM, etc. of the signal processing means DSP are changed. The parameters are changed and then the second operation begins. This ensures that signal processing is not interrupted and that noise is kept low.

〔Example〕

Hereinafter, one embodiment of the present invention will be described in detail based on FIGS. 1 to 3.

FIG. 1 shows the circuit configuration of this embodiment. In the figure, (1) is an input terminal to which an input digital signal is applied, and (2) is a multiplier as an attenuator. (2) controls the input level. (3)
is a multiplier as a balancer, and when this circuit is used for receiving stereo signals, this multiplier (3) controls the balance of left and right channel signals. (4)
is a de-emphasis circuit, (5).

(6) is a multiplier for de-emphasis on/off, (7
) is an adder that adds the respective outputs of the multipliers (51, (61).

For example, when the coefficient of the multiplier (5) is 1.0 and the coefficient of the multiplier (6) is 0.0, the output of the de-emphasis circuit (4) is sent to the adder (7) via the multiplier (5). A multiplier (5) is supplied to one input side and a multiplier (5) to the other output side of the adder (7).
As a result, a de-emphasized signal is obtained at the output side of the adder (7).

On the other hand, when the coefficient of multiplier (5) is 0.0 and the coefficient of multiplier (6) is 1.0, the zero output of multiplier (5) is
) and the other output of the adder (7) is fed the output of the multiplier (3) via the multiplier 3 (6), resulting in the output of the adder (7). Nothing on the side
The signal without emphasis is output as is. In other words, the multipliers (51, (6) work to turn on/off de-emphasis.

The digital signal from the adder (16) is sent to the latch circuit (8).
) are latched in parallel. The output signal of the latch circuit (8) is supplied as an address signal to a memory such as a ROM (91, (10)) and is also supplied to a multiplier (11). a
It has effect characteristics as shown by the dashed lines and outputs new data according to the characteristics using the input data as an address.

The data output from the ROM (91, (10)) is selected by the switch (12) and supplied to the multiplier (13), where it is multiplied by a predetermined coefficient and sent to one input side of the adder (14). Furthermore, the output signal of the latch circuit (8) is multiplied by a predetermined coefficient in a multiplier (11) and then supplied to the other input side of the adder (14).
4) adds both the supplied signals and supplies it to the multiplier (15). Note that (2) to (14) constitute a digital signal processing circuit DSP. The multiplier (15) multiplies the supplied signal by a predetermined coefficient A and supplies the result to one input side of the adder (16). Further, the digital signal from the input terminal (11) is supplied to the other input side of the adder (16).The adder (16) adds the two supplied signals and outputs the result to the output terminal (18). .

Now, each parameter of the digital signal processing circuit DSP is changed as follows. First, during normal operation, the coefficient A of the multiplier (15) is set to 1, and the coefficient B of the multiplier (17) is set to 0. Therefore, during normal operation, the digital signal from the input terminal (1) is After undergoing predetermined signal processing in the signal processing circuit DSP, it passes through the multiplier (15) as it is, is supplied to the adder (16), and is output to the output terminal (1
8). Of course, since the digital signal supplied to the multiplier (17) is multiplied by the coefficient O here, it is not output to the output terminal (18).

In this state, the operation of cross-fading the output signal S of the digital signal processing circuit DSP from the input terminal (L) to the signal S2 input to the multiplier (17), that is, the signal An operation (first operation) is started in which the signal S1 is gradually reduced and, conversely, the signal S2 is gradually increased as shown in FIG. 3B. At this time, the microcomputer (not shown) gradually reduces the coefficient A of the multiplier (15) from 1 toward O, and conversely, the coefficient B of the multiplier (17) gradually decreases from O toward 1. Increased. This cross-fade period (first operation) corresponds to period T1 in FIG. 3C.

When this first operation is completed, only the signal s2 is output from the output terminal (
1 day), and the signal S□ is output with a coefficient of 0 in the multiplier (15).
Since the multiplication becomes zero, nothing is output to the output terminal (18). This period is period T2 in FIG. 3C.

In this way, during the period T2, the digital signal processing circuit DS
Since the output signal s1 of P has no effect on the signal finally obtained at the output terminal (18), each parameter of the digital signal processing circuit DSP is changed during this period. That is, for example, multipliers (2), (31, (5), ゛(
6), (11), and (13), or the number of delay samples of the de-emphasis circuit (4), or by controlling the switch (12).
Select the desired one from 10).

After changing each parameter of the digital signal processing circuit DSP in this manner, the signal S2 input from the input terminal (1) to the multiplier (17) is cross-fade to the output signal S of the digital signal processing circuit DSP. An operation (second operation) in which the signal S2 is gradually reduced and, conversely, the signal S1 is gradually increased is entered. At this time, the coefficient B of the multiplier (17) is set to 1 by the microcomputer.
The coefficient A of the multiplier (15) is gradually increased from O toward 1. This cross-fade period (second operation) corresponds to period T3 in FIG. 3C.

After the second operation is completed, the normal operation described above, that is, the signal S2 is set to zero, and only the signal S1 is outputted to the output terminal (18) is started.

In addition, in the above-mentioned embodiment, ROM (9) and (1
0) is not limited to these two, and more may be provided.

Furthermore, the circuit configuration of the digital signal processing circuit DSP is not limited to the above-described circuit configuration, and may be other configurations such as a graphic equalizer.

〔Effect of the invention〕

As described above, according to the present invention, the parameters of the signal processing means are changed after crossfading the digital signal output from the signal processing means to the digital signal input to the signal processing means, so that signal processing is interrupted. Parameters can be quickly changed without having to do so, and with minimal noise.

[Brief explanation of drawings]

FIG. 1 is a circuit configuration diagram showing one embodiment of the present invention, and FIGS. 2 and 3 are diagrams for explaining the operation of FIG. 1. (15) and (17) are multipliers, (16) is an adder, and DSP is a digital signal processing circuit.

Claims (1)

[Claims] A signal processing means to which a digital signal is input, and a cross-fade means to cross-fade the digital signal input to the signal processing means and the digital signal output from the signal processing means, 1. A digital signal processing device, wherein a parameter of said signal processing means is changed after cross-fading a digital signal inputted to said signal processing means with said digital signal inputted to said signal processing means.