JPH04345311A - Digital fadar - Google Patents

Abstract

PURPOSE:To obtain a desired fade waveform with simple constitution. CONSTITUTION:A general output Ya of a DSP 20 is expressed in Ya=(C2)<n>Yo, where Yo is an output of a multiplier 22 and C2 is a coefficient of a multiplier 26, and when the coefficient C2 is smaller than the unity, the calculation decreasing logarithmically with respect to the input Yo is implemented. When a fixed value '1'('0') is alternately inputted from a fixed value output section 10(12) to the DSP 20, a waveform of fade-in, fade-out is outputted from the DSP 20. Thus, the fade waveform is fed to a multiplier 30, in which fade processing corresponding to the inputted sound signal from a terminal TA is implemented.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in a digital fader device for performing fade-in and fade-out processing on digital audio signals and the like.

0002

2. Description of the Related Art A table reference method is known as a digital fader method for automatically performing fade-in and fade-out processing on digital audio signals. According to this method, coefficients in a table created in advance and stored in a ROM etc. are read out one after another,
Based on these, a desired fade waveform can be obtained.

0003

[Problems to be Solved by the Invention] However, such conventional techniques require a huge table of coefficients in order to obtain fade waveforms of various types, which requires a considerable amount of storage capacity and reduces productivity. There is also the disadvantage that it is also bad. To avoid this, a method of incrementing or decrementing a fixed value may be considered. However, this method has the disadvantage that not only is it difficult to obtain a desired fade waveform, but also that the fade waveform becomes linear, making it impossible to obtain a logarithmic fade characteristic that suits the sense of hearing. The present invention has focused on this point, and an object of the present invention is to provide a digital fader device that can satisfactorily obtain a desired fade waveform with a simple configuration.

0004

One aspect of the present invention is a digital fader device that performs at least one of fade-in and fade-out processing on an input signal.
gain data output means for changing the value of output gain data in response to desired fade processing; first multiplication means for multiplying the gain data by a first coefficient; and input for multiplication by a second coefficient. a second multiplier for data; an adder for adding the outputs of the first and second multipliers; and an adder for delaying the added output data corresponding to the sampling period of the digital signal; and delay means for supplying the signal to the multiplication means.

Another invention is a digital fader device that performs at least one of fade-in and fade-out processing on an input signal, the device including a plurality of cascade-connected arithmetic units, each arithmetic unit having a predetermined gain data output means for outputting gain data; first multiplication means for multiplying the gain data by a first coefficient that changes in accordance with desired fade processing; a second multiplication means for multiplying input data by a second coefficient; an addition means for adding the outputs of the first and second multiplication means; and delay means for supplying the signal to the second multiplication means.

Still another invention is a digital fader device that performs at least one of fade-in and fade-out processing on an input signal, and this device includes a plurality of arithmetic units provided in parallel and a plurality of arithmetic units of these arithmetic units. and a selection means for selecting one of the outputs, and each arithmetic unit includes a gain data output means for outputting predetermined gain data, and a selection means for selecting one of the outputs. a first multiplier that multiplies the gain data; a second multiplier that multiplies the input data by a second coefficient that changes in accordance with desired fade processing; and outputs of these first and second multipliers. , and delay means for delaying the added output data corresponding to the sampling period of the digital signal and supplying it to the second multiplication means.

[0007]

According to the present invention, a fade waveform is obtained by arithmetic operations using multiplication, addition, and delay processing by an arithmetic unit. At this time, the gain data of the arithmetic unit or the multiplication coefficient changes in accordance with the desired fade waveform. Further, a desired fade waveform can also be obtained by cascading arithmetic units or by selecting the outputs of arithmetic units arranged in parallel.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of a digital fader device according to the present invention will be described with reference to the accompanying drawings. <Example 1> First, Example 1 of the present invention will be described with reference to FIGS. 1 to 4. FIG. 1 shows Example 1
The configuration of the fader device is shown. In the same figure,
The output sides of the fixed value output sections 10 and 12 are respectively connected to the switching input side of the switch 14. The output side of this switch 14 is connected to the output side of the digital volume 16 as well as the switching input side of another switch 18. The output side of this switch 18 is connected to the input side of a digital signal processor (hereinafter referred to as "DSP") 20.

The DSP 20 functions as an equivalent circuit as shown in the figure, and the input signal is first multiplied by a coefficient C1 by a multiplier 22. The signal multiplied by C1 is added to the output of another multiplier 26 in an adder 24. The output of the adder 24 serves as the output of the DSP 20 on one side, and is input to the delay circuit 28 on the other side. This delay circuit 28 is for delaying the input signal by one sampling time and outputting the delayed signal, and the delayed output is input to the multiplier 26. The multiplier 26 multiplies the input signal by a coefficient C2. Note that a sampling pulse Fs that defines the operation timing of each section is input to the DSP 20.

Next, the output side of the DSP 20 is connected to the multiplication coefficient input side of a multiplier 30 for amplifying and outputting a digital audio signal. Among the above parts,
The fixed value output units 10 and 12 are for outputting fixed values "1" and "0", respectively. The digital volume 16 is configured to output gain data DV that changes in steps in accordance with the position of the knob KN.

The DSP 20 is a well-known device that can perform the operations of the illustrated equivalent circuit using software. The signal supplied from switch 18 is multiplied by a coefficient C1 in multiplier 22. If the output of this multiplier 22 is, for example, Y0, it is first output from the adder 24. At the next sampling timing, Y0 is delayed by the delay circuit 28 and input to the multiplier 26, where it is multiplied by C2 and supplied to the adder 24. As a result, the output Y1 of the adder 24 becomes Y1=C2Y0. Note that the coefficients C1 and C2 are set to satisfy the condition of C1+C2=1.

[0012] Furthermore, for example, when inputting gain data DV, C
Initial settings are performed so that 1DV+C2DV=(C1+C2)DV=DV, that is, the input and output values are equal (from time t0 to t in FIG. 3, which will be described later).
1, t4-t5).

At the next timing after the output of the adder 24 becomes Y1=C2Y0, Y2=C2Y1=C2(C2Y0)=(C2)2Y0. When the above operations are repeated in order, the DSP20
The general output Yn is: Yn=(C2)nY0......
…………………………………(1). Therefore, when the coefficient C2 of the multiplier 26 is smaller than 1, an output Yn obtained by performing a logarithmic reduction operation on the input Y0 is obtained. For example, when the input Y0 is "1", an output waveform of (C2)n is obtained.

Next, the output fixed value RV of the switch 14 is "
When switched from "0" to "1", the output Yn of the multiplier 22 is as follows: Y1=C1 Y2=C1C2 …… Yn=C1+C1C2+C1C22+…… ……+C
1C2n=C1 [(1-C2n)/(1-C2)]. Here, if we set n→∞ and substitute the condition of C1+C2=1, then Yn=C1(1/(1-C2))=1
……………………(2), and as time passes, the final gain approaches 1. In this case, the fade waveform rises like an attack rather than rising logarithmically, which is audibly preferable.

Next, the operation of the first embodiment as described above will be explained with reference to the graphs of FIGS. 2 and 3. First, fade in with digital volume 16,
The operation of fade out will be explained. switch 18
It is assumed that the switch has been switched to the digital volume 16 side. The digital volume 16 outputs step-like gain data DV, for example, as shown by the graph GA in FIG. 2, corresponding to the position of the knob KN. Note that the degree of step STP is based on digital volume 1.
It is determined by a resolution of 6. Such gain data DV
is input to the DSP 20.

In the DSP 20, the above-described arithmetic processing is performed on the gain data DV. As a result, DS
The output of P20 becomes as shown in graph GB in FIG. 2 by connecting the calculated values for each sampling. For example, if the gain data DV of the digital volume 16 is smoothed by passing it through a low-pass filter, the result will be as shown in the graph GC in the figure. In this way, if an attempt is made to smooth the portion where the step interval is large, the smoothing time constant of the filter becomes long, and the ability to follow up and down movements in the portion where the step interval is small becomes poor. Therefore, the feeling of operating the knob KN becomes worse.

However, in this embodiment, the fade waveform can be set as shown in graph GB in accordance with the step interval, and as is clear from comparing graphs GB and GC, the followability to graph GA, in other words, is This will greatly improve the ability of the output of the DSP 20 to follow the movement of the knob KN of the digital volume 16, and the operating feel of the knob KN will be extremely good. Furthermore, the stepped waveform is a logarithmic waveform that suits the sense of hearing. The result of such calculation by the DSP 20 is supplied to the multiplier 30, and based on this, multiplication processing is performed on the audio signal input to the terminal TA, and the signal after this fade processing is outputted from the terminal TB.

Next, the fade-in and fade-out operations by the fixed value output sections 10 and 12 will be explained with reference to FIG. It is assumed that the switch 18 is switched to the switch 14 side. Next, the switch 14 is initially on the fixed value output section 10 side, as shown in FIG. 3(A).
It is switched to the fixed value output section 12 side at time t1, further switched to the fixed value output section 10 side at time t3, and further switched to the fixed value output section 12 side at time t5. Therefore, the gain data RV of the switch 14 becomes as shown by the graph GD in the figure.

[0019] Such gain data RV is
, the calculations shown in equations (1) and (2) are performed. As a result, the signal after the calculation becomes as shown by graph GE in the figure, and this is output to the multiplier 30. Here, if the signal shown in the figure (B) is input to the terminal TA of the multiplier 30, as a result of the calculation by the multiplier 30, the fade signal shown in the figure (C) is input to the terminal TB. A processed signal will be obtained. Even in this case, the fade waveform has a good logarithmic hearing sensation.

The automatic fader device configured as described above is utilized as shown in FIG. 4, for example. In the figure, the audio signal is input to an automatic fader device 32 on the recording side, where the above-described fade processing is performed as necessary. The processed signal is then input to the signal recording/reproducing device 34, and thereby recorded on an appropriate recording medium 36. Further, the signal reproduced from the recording medium 36 by the signal recording and reproducing device 34 is subjected to the above-described fade processing by the automatic fader device 38, if necessary.

<Embodiment 2> Next, Embodiment 2 of the present invention will be described with reference to FIGS. 5 and 6. Note that the same reference numerals are used for the same or corresponding components as in the first embodiment described above (the same applies to the third embodiment). In this second embodiment, DSPs are connected in cascade to enable various types of fade characteristics to be obtained.

In FIG. 5, the output side of the fixed value output section 10 is connected to the input side of the first DSP 40, and the output side of this first DSP 40 is connected to the input side of the second DSP 50. ing. The output side of this second DSP 50 is connected to the coefficient input side of the multiplier 30. D
The multipliers 22 and 26 of the SPs 40 and 50 each have a coefficient CP.
11, CP12, CP21, and CP22 are input, respectively.

Next, the operation of the second embodiment as described above will be explained. a. When operating in a non-cascade state, first, the DSP
A case will be described in which fade processing is performed using only one of the signals 40 and 50, for example, the DSP 40. In this case, CP11=1-k, CP12=k...
The coefficients are set as shown in (3). Here, k is a positive number smaller than 1, and is 0 before the fade starts and becomes 1 when the fade ends. In addition, DSP
The coefficients CP21 and CP22 of 50 are as follows: CP21=1, CP22=0
………………………………(4) is set. Therefore, in the DSP 50, the output of the multiplier 26 is "0".
The input of the multiplier 22, that is, the DSP
The output of 40 is directly output to the multiplier 30.

First, before the start of the fade, k=0, so CP11=1, CP12=0
…………………………………(5). This results in
The multiplier 26 of the DSP 40 has an output of "0" and does not function, and the input of the multiplier 22 is directly output to the multiplier 30. Next, during the fade, calculation according to equation (1) is performed based on the coefficient shown in equation (3), and the calculation result is output.

Furthermore, at the end of the fade, k=1, that is, CP11=0, CP12=1
Coefficient CP so that ……………………………(6)
11, Rewrite CP12. The multiplier 30 performs fade processing on the input signal based on the thus obtained fade waveform.

b. Case of operating in cascade state Next, the operation when both the DSPs 40 and 50 are used in a cascade state will be described. In this case, the operation in the non-cascade case described above is performed in both the DSPs 40 and 50. As a result, the multiplier 22 of the DSP 40
The relationship between the output Y0 and the output Y40n is
Y40n=(CP12)nY0 ………………
………………(7), and the relationship between this and the output Y50n of the DSP50 is Y50n=(CP22)n・CP21Y40n
=(CP22)n・(CP12)n・CP21Y0
...(8) becomes. Note that, similarly to equation (3), CP21=1−k,
CP22=k.

When the calculated values at each sampling point in the above-described operation are connected, a waveform like the graph GG in FIG. 6 is obtained, for example. Note that the graph GF in the figure is a fade waveform in the case of non-cascade as described above.

Note that the sum CP1 of the coefficients of the multipliers 22 and 26
Theoretically, it is necessary that 1+CP12 and CP21+CP22 be "1". However, in cases where the output of the DSP 40 or 50 is rounded off, the output level should approach infinity over time, but errors accumulate and converge to a finite value as shown in Figure 6. It may not be infinitely small. Therefore, in practice, the sum of both coefficients is set to be slightly smaller than "1". That is, for δ satisfying 0<δ<k, CP11=1−k−δ, CP12=k
, CP21=1-k-δ, CP22=
k ………………………Correct as shown in (9). Thereby, the above-mentioned inconvenience can be eliminated.

<Embodiment 3> Next, Embodiment 3 of the present invention will be described with reference to FIGS. 7 and 8. In this third embodiment, a plurality of DSPs are connected in parallel, and by switching these, various types of fade waveforms can be obtained.

In FIG. 7, initial value output units 62, 72, and 82 are connected to the input sides of the DSPs 60, 70, and 80, respectively. ”
is now output. Also, DSP60,7
Each of the multipliers 22 and 24 of 0 and 80 has coefficients CP11 and C
P12, CP21, CP22, CP31, and CP32 are each input. Each output side of the DSP 60, 70, 80 is connected to one of the switches 92, 94, 96 of the changeover switch 90, respectively.
, 96 are commonly connected to the coefficient input side of the multiplier 30.

Next, the operation of the third embodiment as described above will be explained. First, the individual operations of each DSP 60, 70, and 80 are similar to those in the embodiment described above. For example, D.S.
It is assumed that the fade waveforms of P60, 70, and 80 are as shown in graphs GH, HI, and GJ of FIG. 8(A). Switch 92 of selector switch 90 at the start of fade
When one is turned on and the others are turned off, fade processing using the graph GH is initially performed.

If the switch 94 is turned on and the others are turned off during the process, a fade process using the graph GI is performed at that point. Further, when the switch 96 is turned on and the others are turned off, a fade process using the graph GJ is performed. Therefore, as a whole, processing is performed using the fade waveform shown by graph GX in the figure. Here, the changeover switch 90 can be realized by executing maximum value selection logic that selects the largest value among inputs.

Similarly, it is assumed that the fade waveforms of the DSPs 60, 70, and 80 are as shown in graphs GK, HL, and GM of FIG. When the switch 96 of the selector switch 90 is turned on and the others are turned off at the start of the fade, initially the fade processing is performed using the graph GM. If the switch 94 is turned on and the others are turned off during the process, a fade process using the graph GL is performed at that point. Further, when the switch 92 is turned on and the others are turned off, fade processing is performed using the graph GK. Therefore, as a whole, processing is performed using the fade waveform shown by graph GY in the figure. here,
The changeover switch 90 can be implemented by executing minimum value selection logic that selects the minimum value among the inputs.

To summarize, in the case of only one DSP, the graph GO in FIG. You will be able to get it.

<Other Embodiments> The present invention is not limited to the above-mentioned embodiments, and includes, for example, the following embodiments. (1) The coefficients of the multipliers constituting the DSP and the input values from the input section may be set as necessary, and are not limited to the above embodiments. (2) Furthermore, the number of DSPs connected in series or parallel may be arbitrary, and series and parallel connections may be combined.

[0036]

[Effects of the Invention] As explained above, according to the digital fader device according to the present invention, a fade waveform is obtained using a DSP, or a plurality of DSPs are combined, so that a desired fade waveform can be easily obtained. This has the effect that it can be obtained satisfactorily depending on the configuration.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram showing a first embodiment of a digital fader device according to the present invention.

FIG. 2 is a graph showing the effect of Example 1.

FIG. 3 is a graph showing the effect of Example 1.

FIG. 4 is an explanatory diagram showing how Example 1 is used.

FIG. 5 is a configuration diagram showing a second embodiment of the present invention.

FIG. 6 is a graph showing the effect of Example 2.

FIG. 7 is a configuration diagram showing a third embodiment of the present invention.

FIG. 8 is a graph showing the effect of Example 3.

[Explanation of symbols]

10, 12...Fixed value output section (gain data output means),
14, 18, 92, 94, 96...Switch, 16...Digital volume, 20, 40, 50, 60, 70, 8
0... DSP (arithmetic unit), 22, 26, 30... Multiplier (multiplying means), 24... Adder (adding means), 28... Delay circuit (delay means), 32, 38... Automatic fader device,
34...Signal recording/reproducing device, 36...Recording media, 62,
72, 82... initial value output section (gain data output means),
90...Selector switch, C1, C2, CP11, CP12
, CP21, CP22, CP31, CP32...coefficient, F
s...Sampling signal, GA to GP, G1, G2...graph, TA, TB...terminal.

Claims (3)

[Claims] 1. A digital fader device that performs at least one of fade-in and fade-out processing on an input signal, comprising: gain data output means for changing the value of output gain data in accordance with desired fade processing; a first multiplier that multiplies the gain data by a coefficient of 1; a second multiplier that multiplies the input data by a second coefficient; and adds the outputs of the first and second multipliers. A digital fader device comprising: an adding means; and a delay means for delaying the added output data corresponding to the sampling period of the digital signal and supplying the added output data to the second multiplication means. 2. A digital fader device that performs at least one of fade-in and fade-out processing on an input signal, the device including a plurality of cascade-connected arithmetic units, each arithmetic unit processing predetermined gain data. gain data output means for outputting; first multiplication means for multiplying the gain data by a first coefficient that changes in accordance with a desired fade process; and a second multiplier that changes in accordance with a desired fade process. a second multiplication means for multiplying input data by a coefficient; an addition means for adding the outputs of the first and second multiplication means; and delaying the added output data corresponding to the sampling period of the digital signal. and a delay means for supplying the signal to the second multiplication means. 3. A digital fader device that performs at least one of fade-in and fade-out processing on an input signal, which device comprises a plurality of arithmetic units provided in parallel and an output of one of these arithmetic units. each arithmetic unit includes gain data output means for outputting predetermined gain data, and a first selector that changes in accordance with desired fade processing.
a first multiplier that multiplies the gain data by a coefficient; a second multiplier that multiplies the input data by a second coefficient that changes in accordance with desired fade processing;
Adding means for adding the outputs of the first and second multipliers, and delaying the added output data corresponding to the sampling period of the digital signal;
and delay means for supplying signals to the multiplication means.