JPH0620272B2 - Digital signal processor - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a digital signal processing device configured by a digital circuit for performing crossfade processing.

(Prior Art and Its Problems) Conventionally, a digital signal processing device for performing cross-fade processing inputs a plurality of digital input signals 1n (n = 1, 2, ...) As shown in the block diagram of FIG. Then, the selection device 3 that outputs the selection output signal 2 by cross-fading from one input signal to the other input signal, and the selection control device 5 that outputs the selection signal 4 for controlling the selection. It consists of

However, in such a conventional device, there is no means for knowing whether or not the crossfade is being performed. Therefore, if the selection control device outputs the selection signal to the selection device during the crossfading of the selection device, the selection device cannot follow the selection signal and generates an abnormal sound, which interferes with the selection operation. There is a drawback that it ends up.

It is an object of the present invention to provide a digital signal processing device that eliminates such drawbacks and can smoothly perform crossfading.

(Means for Solving the Problem) In order to achieve the above-mentioned object, a plurality of digital input signals are used.
14 and a selection signal 18 for instructing a signal to be selected from among the digital input signals 14 as input signals, and outputs the selected digital input signal 14 and a status signal 21 indicating whether or not crossfading is being performed. A selection device 6 which is a signal, and a selection control device 7 which is an output signal and a selection signal 18 which is output only when the status signal 21 is an input signal and is not in crossfading.
It consists of

(Operation) As described above, even if the selection control device 7 is instructed to select during the crossfade, the selection control device 7 holds the output of the selection signal 18 until the crossfade is completed. Is not confused and therefore does not generate any abnormal noise.

(Embodiment) FIG. 1 is a block diagram of a digital signal processing device of the present invention,
FIG. 2 is a block diagram of the main part. In this circuit, there are two input signals. The circuits can be roughly classified into a selection device 6 and a selection control device 7. The selection control device 7 is composed of a microcomputer 8. The selection device 6 includes a counter 9, a clock generator 10, a coefficient unit 11,
It is composed of an adder 12 and n multipliers 13-1 and 13-2.

Next, the operation of the selection device 6 will be described.

The multiplier 13-1 inputs the input digital input signal 14-1 and the coefficient signal 15-1 output from the coefficient unit 11, multiplies both signals 14-1 and 15-1, and outputs the multiplication signal 16-1. Output.

Similarly, the multiplier 13-2 also has a digital input signal 14-2 and a coefficient signal 15
-2 is input, both signals 14-2 and 15-2 are multiplied, and the multiplication signal
Outputs 16-2.

These multiplication signals 16-1 and 16-2 are input to the adder 12 where they are added and output as a selection output signal 17.

On the other hand, the coefficient unit 11 inputs the selection signal 18 from the selection control device 7 (microcomputer 8) and the counter signal 19 from the counter 9, and the selection signal 18 crossfades from the digital input signals 14-1 to 14-2. In the case of the above format, the coefficient signal 15-1 is output by subtracting the count signal from the maximum count value of the counter signal 19, and the coefficient signal 15-2 is output by the count signal. Similarly, if the digital input signals 14-2 to 14-1 are crossfade, the coefficient signal 15-1 is a counter signal.
19 is output, and the count signal is calculated from the maximum count value of the counter signal to the coefficient signal 15-2.

The counter 9 inputs the selection signal 18 and the clock signal 20.
When the selection signal 18 is input, the value of the counter 9 is cleared and counting is performed by a clock signal 20 from a clock generator 10 described later until a carry is generated from 0. In this count, the value of the counter 9 is incremented by 1 and the value of the counter 9 is output as the counter signal 19, and the carry of the counter 9 is output as the state signal 21.

The clock generator 10 receives the status signal 21 and outputs a clock if no carrier is generated.

The selection control device 7 is composed of a microcomputer 8 and its operation is as follows. FIG. 3 is this flowchart. When you receive the instruction to start the operation,
The occurrence of carry is determined by the status signal 21.

If a carry is generated, the selection signal 18 is output, the counter 9 is cleared to start counting, and the coefficient unit 11 is operated to change the digital signal from 14-1 to 14-2 or from 14-2.
Perform a crossfade to 14-1.

If the carry is not generated, the judgment operation is repeated until the carry is generated.

That is, first, the selection signal 18 is output from the microcomputer 8 to the coefficient unit 11 and the counter 9, the counter 9 starts operating, and the carry of the state signal 21 is eliminated. Further, the counter signal 19 output from the counter 9 is converted into a desired crossfade format by the coefficient unit 11. Coefficient signal 15-1
And 15-2 and the digital input signals 14-1 and 14-2 are multipliers.
Crossfades are started by 13-1 and 13-2 and the adder 12.

Since the carry of the status signal 21 is not generated when the counter 9 is operating and crossfading, the microcomputer 8 does not output the next selection signal 18 and waits until the carry of the status signal 21 is generated.

The counter 9 generates a carry and outputs it to the status signal 21,
When the operation of the counter 9 is stopped, the microcomputer 8
The status signal 21 outputs the next selection signal 18 to start a new crossfade.

In this way, the digital input signal 14-1 and the coefficient signal 15-1
Is multiplied by the multiplier 13-1 by the multiplication signal 16-1, and the digital input signal 14-2 and the coefficient signal 15-2 are multiplied by the multiplier 13-2 by the addition signal 16-2. Is added to obtain the selected output signal 17, and the coefficient signals 15-1 and 15-2 are changed, so that crossfading can be performed from the digital input signals 14-1 to 14-2 or vice versa.

(Effects of the Invention) As described above, since the selection control device 7 knows the operating state of the selection device 6, it can be configured to be independent of the crossfade time of the selection device 6, and thus the device can be simplified. .

In addition, the selection control device 7 manages the crossfade time so that the loss of waiting time during the crossfade that may occur is minimized and the selection device 6 sends the selection signal 18 during the crossfade. It is possible to completely prevent the generation of noise.

[Brief description of drawings]

FIG. 1 is a block diagram of a digital signal processing device of the present invention,
FIG. 2 is a block diagram of the main part, FIG. 3 is a flowchart of the operation of the selection control device, and FIG. 4 is a block diagram of a conventional digital signal processing device. 6: Selection device, 7: Selection control device, 14: Digital input signal, 18: Selection signal, 21: Status signal.

Claims (1)

[Claims] 1. A digital signal processing device for selecting and outputting from a plurality of digital input signals, wherein a plurality of digital input signals and a selection signal for instructing a signal to be selected among the digital input signals are used as input signals. A digital input signal and a selection device having a status signal indicating whether or not crossfading is being performed as an output signal, and a selection signal that is output only when the status signal is not being crossfaded as an output signal and an output signal A digital signal processing device, comprising: