JPS63224414A - A/d converter - Google Patents
A/d converterInfo
- Publication number
- JPS63224414A JPS63224414A JP5815487A JP5815487A JPS63224414A JP S63224414 A JPS63224414 A JP S63224414A JP 5815487 A JP5815487 A JP 5815487A JP 5815487 A JP5815487 A JP 5815487A JP S63224414 A JPS63224414 A JP S63224414A
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- circuit
- conversion
- reference voltage
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000006243 chemical reaction Methods 0.000 claims abstract description 24
- 238000005259 measurement Methods 0.000 description 13
- 238000010586 diagram Methods 0.000 description 3
- 230000009466 transformation Effects 0.000 description 3
- 240000007594 Oryza sativa Species 0.000 description 1
- 235000007164 Oryza sativa Nutrition 0.000 description 1
- 241000270708 Testudinidae Species 0.000 description 1
- 235000013399 edible fruits Nutrition 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 235000009566 rice Nutrition 0.000 description 1
Landscapes
- Analogue/Digital Conversion (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発BAは被計測1号としてアナログ信号を取扱う計
測分野に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] This BA relates to the field of measurement that handles analog signals as the first measurement target.
第2図は、従来の遂次比較型A / D変換装置であり
9図において、 Saは被計測信号、(1)に被計測信
号とD/A変換回路(4)の信号を電圧比軟する電圧比
較量コンパレータ1t2)FiIK圧比較減コンパレー
タ(1)の信号を蓄積する遂次比較レジスタ、(3)は
基準電圧発生回路、(4)は上記基準電圧発生回路(3
)の電圧を入力し遂次比較レジスタ(2)のデータに対
応したアナログ電圧を発生させるD/A変挨変格回路5
)は上記動作のタイミングを制御するタイミング回路、
DaはA/D変換値である。Figure 2 shows a conventional sequential comparison type A/D converter. (3) is a reference voltage generation circuit, (4) is the reference voltage generation circuit (3)
) input voltage and generates an analog voltage corresponding to the data of the sequential comparison register (2).
) is a timing circuit that controls the timing of the above operation,
Da is an A/D conversion value.
上記構成によると、D/ム変供回路の発g:′tIt圧
によってのみ回路の分解能が決定されるなめ。According to the above configuration, the resolution of the circuit is determined only by the oscillation g:'tIt pressure of the D/mu conversion circuit.
D/A変換回路の発生電圧以上の電圧を計測する場合、
入力電圧を減圧してA/D変換しなければならず計測精
度を低下させて、計測するかより良い分解能を有したJ
) / A変換回路が必要となり。When measuring a voltage higher than the voltage generated by the D/A conversion circuit,
The input voltage must be reduced and A/D converted, reducing the measurement accuracy, and the measurement accuracy may be reduced.
)/A conversion circuit is required.
llff1格の増加を招く問題点があった。There was a problem that led to an increase in the number of llff1 cases.
この発明は、上記のような問題点t−屏消するためにな
されたもので、D/A変侠変格回発生電圧以上の電圧を
ぎ↑測する場合でも、計測精度を低下さセず計測できる
A / D変換装置ltk得ることを目的とする。This invention was made to eliminate the above-mentioned problems, and even when measuring a voltage higher than the D/A variable generation voltage, it is possible to measure without reducing measurement accuracy. The purpose is to obtain a capable A/D conversion device ltk.
この発明に保るA / D変換装置は、スイッチ回路で
MI真回路の出力を選択し、電圧比較型コンパレータに
て、加算回路を経由した基準電圧発生回路の出力電圧と
人力信号を比較1−ることにより。The A/D converter according to the present invention selects the output of the MI true circuit using the switch circuit, and compares the output voltage of the reference voltage generation circuit via the adder circuit with the human input signal using the voltage comparison type comparator.1- By doing so.
本装置に26けるA/D変侠変換上位ビットの判定が行
なわれる。七の結果をもとにラッチ回路が。The determination of the upper bit of the A/D conversion in 26 is performed in this device. A latch circuit is created based on the results of step 7.
上記スイッチ回路を制御し加算回路の国力を圧を供給す
るかl D/Af侠回路の国力電圧を供給するか決定す
る。このため2本装置は従来の計測精度を低ドさせず2
gE米の2倍の計測範囲を有することができるよ5にし
たものである。The switch circuit is controlled to determine whether to supply the voltage of the adding circuit or the voltage of the L D/Af circuit. For this reason, two devices can be used without reducing the conventional measurement accuracy.
It is set to 5 so that it can have twice the measurement range of gE rice.
この発明にsvfる蒐圧比奴型コノパV−夕は。 This invention is a svf pressure ratio type Konopa V-Yu.
人力信号と加算回路を経由した基準電圧発生回路の国力
電圧を比較1゛ることにより、入力信号が基準電圧発生
回路の出力電圧を超えるか否かの判定が最上位ビットの
電圧判定となり、その結果超えない場合は、スイッチ回
路はLl / A変換回路の出力を選択し従来のA /
D変換を実施する。また判定結果が基準電圧発生回路
の出力電圧を超えていると判定した場合、スイッチ回路
に変化しない。By comparing the human input signal with the national voltage of the reference voltage generation circuit via the adder circuit, it is determined whether the input signal exceeds the output voltage of the reference voltage generation circuit or not by determining the voltage of the most significant bit. If the result is not exceeded, the switch circuit selects the output of the Ll/A converter circuit and converts it to the conventional A/A converter.
Perform D conversion. Further, if it is determined that the determination result exceeds the output voltage of the reference voltage generation circuit, the circuit does not change to a switch circuit.
したがって電圧比較型コンパレータへfl D / A
変換回路の出力隠圧プラス基準亀圧発生回路の国力電圧
が供給されA/D変侠変換施3゛ゐ。このことにより重
装fは従来のA / D変換装置に刈し計測M度を低下
させることな(2倍の計測範囲を有することかでざる。Therefore, fl D/A to the voltage comparison type comparator
The output hidden pressure of the conversion circuit plus the national power voltage of the reference tortoise pressure generation circuit is supplied and A/D conversion is performed. As a result, the heavy equipment f does not reduce the measurement degree of the conventional A/D converter (it has twice the measurement range).
第1図は、この発明の一実施例を示1−栴成図である。 FIG. 1 is a diagram showing one embodiment of the present invention.
図において、(1)〜(5)は上記従来回路と全く同一
のものである。上記第1図において、タイミング回路(
5)はスイッチ回路(6)がIXJ算回路(7)を選択
するようにラッチ回路(8)を制f4するとともに、D
/A変換回路(4)の国力電圧が発生しないように逐次
比fL’ジスタ(2)を制御する。したがって、’m圧
比較型コンハレータ(1)に被計測信号Saと上記加算
回路(7)を経由し′fc基準基準発圧発生回路)の出
力′電圧とを比較することにより本装置における最上位
ビットの電圧判定が行なわれる。In the figure, (1) to (5) are completely the same as the conventional circuit described above. In Figure 1 above, the timing circuit (
5) controls the latch circuit (8) so that the switch circuit (6) selects the IXJ arithmetic circuit (7), and also controls the D
The successive ratio fL' resistor (2) is controlled so that the national power voltage of the /A conversion circuit (4) is not generated. Therefore, by comparing the measured signal Sa and the output voltage of the fc reference voltage generation circuit via the adder circuit (7) in the m-voltage comparison type conhalator (1), A bit voltage determination is performed.
上記電圧比較型コンパレータ(1)の比El果、被計測
信号Saが上記基準電圧発生回路(3)の出力電圧より
低いと判定した場会、上記ラッチ回路(81に上記判定
結果が蓄慣されA/D変良の鰍上位ピットDbを得ると
ともに上記スイッチ回路悌)を上記D / a変換回路
(4)に切り侠える。When the voltage comparison type comparator (1) determines that the measured signal Sa is lower than the output voltage of the reference voltage generation circuit (3), the determination result is stored in the latch circuit (81). In addition to obtaining the top pit Db of A/D conversion, the above switch circuit 2) can be switched to the above D/A conversion circuit (4).
さらに、従来回路によるA/D変侠変換始される。この
時、上記スイッチ回路(6)は上記D / A回路(4
)を選択しているため、上記加算回路(7)の出力電圧
は合成されず、上記D / A変換回路(4)の出力電
圧によってのみA / D変換が実施され、従来回路と
同じA / D f侠値Da((得ることができる。Furthermore, A/D conversion by the conventional circuit is started. At this time, the switch circuit (6) is connected to the D/A circuit (4).
), the output voltage of the adder circuit (7) is not synthesized, and A/D conversion is performed only by the output voltage of the D/A converter circuit (4), which is the same as the conventional circuit. D f chivalry value Da((can be obtained.
また、上d己電圧比較型コ/バレーメ(11の比較結果
被計測信号Saが上記基準電圧発生回路(3)の国力電
圧より萬いと判定した場合、上記ラッチ回路(8)は上
記スイッチ回路(6)を駆動せずに加算回路(7)を選
択したままとなる。さらに、加算回路(7)の出力電圧
は基準′1圧発生回路(3)の出力電圧とD / p、
変換回路(4)の国力電圧の合成1直となってA /
D変換が実mされる。したがって、A/D変侠変換bと
Daの旭を併用することにより従来のA/D変侠変換に
比べて、計測m腿を低ドさせずに2倍の計測範囲を有す
ることがでざる。In addition, when it is determined that the signal to be measured as a result of the comparison of the upper d self-voltage comparison type co/valley meter (11) is lower than the national power voltage of the reference voltage generation circuit (3), the latch circuit (8) 6) is not driven and the adder circuit (7) remains selected.Furthermore, the output voltage of the adder circuit (7) is the output voltage of the reference '1 pressure generating circuit (3) and D/p,
The national power voltage of the converter circuit (4) is combined into one shift and A/
The D transformation is performed. Therefore, by using the A/D transformation b and the Asahi of Da together, it is possible to have twice the measurement range without lowering the measurement range compared to the conventional A/D transformation. .
以上のように、この発明によれは被i’を測侶号と基準
電圧発生回路の国力電圧との比較により最上位ビットが
決定されその結果を電圧比較型コンパレータへのオフセ
ット電圧とすることができる。As described above, according to the present invention, the most significant bit is determined by comparing i' with the national power voltage of the surveyor number and the reference voltage generation circuit, and the result can be used as the offset voltage to the voltage comparison type comparator. can.
したがって計測精度を低ドさせること/ヨ(従来のA/
J)変換装置に比べ2倍の計測範囲を得ることができる
。Therefore, it is necessary to lower the measurement accuracy (conventional A/
J) A measurement range twice as large as that of a converter can be obtained.
第1図はこの発明の一実施例を示す回路の構成図、第2
図は従来の回路を示す構成図である。
図において(1)は電圧比較型コンパレータ、(2)は
遂次比軟レジスタ、(3)は基準電圧発庄回路、(4)
はD/Af挨回路、(5)はタイミング回路、(6)は
スイッチ回路、(7)はラッチ回路、+81U加真回路
である。
なお9図中同一符号は同一または相当部分を示す。FIG. 1 is a circuit diagram showing one embodiment of the present invention, and FIG.
The figure is a configuration diagram showing a conventional circuit. In the figure, (1) is a voltage comparison type comparator, (2) is a sequential ratio soft register, (3) is a reference voltage generator circuit, and (4)
(5) is a timing circuit, (6) is a switch circuit, (7) is a latch circuit, and (7) is a +81U control circuit. Note that the same reference numerals in Figure 9 indicate the same or corresponding parts.
Claims (1)
圧を電圧比較する電圧比較型コンパレータと、上記電圧
比較型コンパレータの比較結果を入力するとともにタイ
ミング回路によつて動作速度を制御される遂次比較レジ
スタと、上記遂次比較レジスタの出力電圧をアナログ電
圧に変換するD/A変換回路と、上記D/A変換回路に
基準電圧を供給する基準電圧発生回路とから構成される
A/D変換装置において、上記電圧比較型コンパレータ
の入力信号をタイミング回路の制御により、加算回路の
出力電圧とD/A変換回路の出力電圧を切り換えるスイ
ッチ回路と、上記加算回路を経由した基準電圧発生回路
の出力電圧を選択した時のA/D変換値をラッチ蓄積す
るラッチ回路と、上記基準電圧発生回路の出力電圧とD
/A変換回路の出力電圧を合成する加算回路とを備えた
A/D変換装置。A voltage comparison type comparator that compares the voltage of the measured signal given from the outside and the output voltage of the D/A conversion circuit; A/D conversion consisting of a comparison register, a D/A conversion circuit that converts the output voltage of the sequential comparison register into an analog voltage, and a reference voltage generation circuit that supplies a reference voltage to the D/A conversion circuit. In the device, the input signal of the voltage comparison type comparator is controlled by a timing circuit to switch the output voltage of the adder circuit and the output voltage of the D/A converter circuit, and the output of the reference voltage generation circuit via the adder circuit. A latch circuit that latches and stores the A/D conversion value when the voltage is selected, and the output voltage of the reference voltage generation circuit and D
An A/D converter including an adder circuit that synthesizes output voltages of the A/A converter circuits.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5815487A JPS63224414A (en) | 1987-03-13 | 1987-03-13 | A/d converter |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5815487A JPS63224414A (en) | 1987-03-13 | 1987-03-13 | A/d converter |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS63224414A true JPS63224414A (en) | 1988-09-19 |
Family
ID=13076073
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5815487A Pending JPS63224414A (en) | 1987-03-13 | 1987-03-13 | A/d converter |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63224414A (en) |
-
1987
- 1987-03-13 JP JP5815487A patent/JPS63224414A/en active Pending
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