JPS63224245A - Lead frame and semiconductor device - Google Patents
Lead frame and semiconductor deviceInfo
- Publication number
- JPS63224245A JPS63224245A JP5659087A JP5659087A JPS63224245A JP S63224245 A JPS63224245 A JP S63224245A JP 5659087 A JP5659087 A JP 5659087A JP 5659087 A JP5659087 A JP 5659087A JP S63224245 A JPS63224245 A JP S63224245A
- Authority
- JP
- Japan
- Prior art keywords
- tab
- hole
- lead frame
- mounting surface
- area
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 28
- 239000011347 resin Substances 0.000 claims abstract description 58
- 229920005989 resin Polymers 0.000 claims abstract description 58
- 238000007789 sealing Methods 0.000 claims description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 abstract description 11
- 238000005336 cracking Methods 0.000 abstract description 3
- 239000000725 suspension Substances 0.000 abstract description 3
- 230000003247 decreasing effect Effects 0.000 abstract 2
- 230000035882 stress Effects 0.000 description 19
- 238000000034 method Methods 0.000 description 12
- 239000000853 adhesive Substances 0.000 description 11
- 230000001070 adhesive effect Effects 0.000 description 11
- 230000000694 effects Effects 0.000 description 9
- 238000005530 etching Methods 0.000 description 8
- 238000005476 soldering Methods 0.000 description 7
- 238000007796 conventional method Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 230000000452 restraining effect Effects 0.000 description 4
- 229910000679 solder Inorganic materials 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 230000002265 prevention Effects 0.000 description 3
- 238000004364 calculation method Methods 0.000 description 2
- 238000006073 displacement reaction Methods 0.000 description 2
- 239000011148 porous material Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000012790 confirmation Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 230000003014 reinforcing effect Effects 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明はリードフレーム及び半導体装置に係り。[Detailed description of the invention] [Industrial application field] The present invention relates to lead frames and semiconductor devices.
特にリフロー半田付は時の加熱による樹脂クラック防止
に好適なリードフレーム及び半導体装置に関する。In particular, reflow soldering relates to lead frames and semiconductor devices suitable for preventing resin cracks due to heating.
樹脂封止型の半導体装置では従来のピン挿入タイプに代
わり、基板に直接リードを半田付けする面付実装タイプ
が主流になりつつある。このようなパッケージでは、高
温高湿環境で保存すると樹脂が水分を吸収し、半田付加
熱時（リフロ一時）に水分がタブと樹脂部との界面で蒸
気になり、タブ下面コーナ部にクラックが生じ易い、こ
のクラックは、半田リフロ一時に発生する為、俗にリフ
ロークラックと呼ばれている。Surface mounting types, in which leads are soldered directly to the substrate, are becoming mainstream in resin-sealed semiconductor devices, replacing the conventional pin insertion types. In such packages, when stored in a high-temperature, high-humidity environment, the resin absorbs water, and during soldering heat (reflow stage), the water turns into steam at the interface between the tab and the resin, causing cracks at the bottom corner of the tab. These cracks, which tend to occur, are commonly called reflow cracks because they occur during solder reflow.
このようなりフロークラックを防止する従来技術として
は、特開昭６０−２０８８４７号公報に記載のようにパ
ッケージの裏面に穴をあけ、発生する蒸気を逃がす方法
がある。As a conventional technique for preventing such flow cracks, there is a method, as described in Japanese Patent Laid-Open No. 60-208847, in which a hole is made in the back of the package to allow the generated steam to escape.
また、樹脂部とタブの界面の接着強さを向上させ、すき
まを防止する技術として、タブの反素子搭載面に凹凸を
設ける方法として特開昭５８−１９９５４８号公報、同
６０−１８６０４４号公報に示される技術、更にタブに
穴を形成したものとして同５９−１６３５７号公報に記
載の技術がある。In addition, as a technique for improving the adhesive strength at the interface between the resin part and the tab and preventing gaps, Japanese Patent Laid-Open Nos. 1987-199548 and 60-186044 disclose a method of providing unevenness on the surface of the tab opposite to the element mounting surface. There is also a technique described in Japanese Patent Publication No. 59-16357 in which a hole is formed in the tab.
上記従来技術のうち、パッケージ下面に穴をあける方法
は、リフロークラックは防げるもののパッケージ外部と
内部に水分の通路を作ることになり、チップ電極の腐食
が生じる可能性がある。Among the above-mentioned conventional techniques, the method of making holes in the bottom surface of the package can prevent reflow cracks, but it creates a passage for moisture between the outside and inside of the package, which may cause corrosion of the chip electrodes.
また、タブの反素子搭載面に単純な凹凸を設ける方法は
タブと樹脂部との接着面内の変位を拘束する効果はある
ものの、両者を引き離す方向の変位については、凹部に
入り込んだ樹脂部が簡単に抜けるために効果が期待でき
ない。Furthermore, although the method of providing simple irregularities on the surface opposite to the element mounting surface of the tab has the effect of restraining displacement within the bonding surface between the tab and the resin part, as for the displacement in the direction of separating them, the resin part that has entered the concave part The effect cannot be expected because it comes off easily.
樹脂封止半導体をリフロー半田付けする際に。For reflow soldering of resin-encapsulated semiconductors.
樹脂中に含まれた水分が気化し、この蒸気圧がタプル樹
止界面にあるボイド又は非接着部等の空孔作用し、タブ
−樹脂界面の剥離を進行させる。剥離進行によって空孔
が大きくなっても、周囲の水分が拡散により供給され、
この結果、空孔の圧力は緩和されず、樹脂部は変形し、
タブ端部の最大応力発生個所を起点にクラックを生じる
。前記の特開昭５９−１６３５７号公報ではタブの一部
を抜き去り、この部分に樹脂を充填することにより熱応
力による剥離を防ぐとともに１等価的に樹脂部の厚さが
増大することにより、耐湿性の向上がある程度は図れる
。しかし、リフロー半田付は時の蒸気圧により、樹脂部
がタブから剥離した場合に生ずる変形により、最大応力
発生個所の応力はタブの一部が抜き去られない場合と大
差なく、この梼造では、リフロー半田付けの際の樹脂部
割れに対する効果は充分ではない。Moisture contained in the resin evaporates, and this vapor pressure acts on voids or non-adhesive areas at the tuple binding interface, promoting peeling of the tab-resin interface. Even if the pores become larger due to the progress of peeling, surrounding moisture is supplied by diffusion,
As a result, the pressure in the pores is not relieved and the resin part is deformed.
Cracks occur at the point where the maximum stress occurs at the tab end. In the above-mentioned Japanese Patent Application Laid-Open No. 59-16357, a part of the tab is removed and this part is filled with resin to prevent peeling due to thermal stress and to equivalently increase the thickness of the resin part. Moisture resistance can be improved to some extent. However, in reflow soldering, the stress at the point where the maximum stress occurs is not much different from when a part of the tab is not removed due to the deformation that occurs when the resin part peels off from the tab due to the steam pressure. However, the effect on cracking of the resin part during reflow soldering is not sufficient.
本発明の目的は蒸気圧により生じるリフロークラックを
防止することにある。An object of the present invention is to prevent reflow cracks caused by vapor pressure.
上記目的は、タブに特殊な形状の貫通穴を設け、この穴
により樹脂部をタブに拘束し、リフロークラックが生じ
るタブ下面コーナ部の樹脂部に発生する応力を低減する
ことにより達成される。The above object is achieved by providing a specially shaped through hole in the tab, restraining the resin part to the tab by this hole, and reducing the stress generated in the resin part at the bottom corner of the tab where reflow cracks occur.
リフロー半田付けの際の樹脂クラックを防ぐには、樹脂
部とタブが剥離しても、タブ端の最大応力発生個所に大
きな応力が生じないようにする必要がある。この要求は
、樹脂部とタブに付着力がなくなった場合でも、樹脂部
の変形を防ぎ得る構造、すなわち、樹脂部が蒸気圧によ
りタブから抜は出ない構造により達成できる。In order to prevent resin cracks during reflow soldering, it is necessary to prevent large stress from being generated at the point where the maximum stress occurs at the tab end even if the resin part and the tab separate. This requirement can be achieved by a structure that can prevent the resin part from deforming even if the adhesive force between the resin part and the tab is lost, that is, a structure that prevents the resin part from coming out of the tab due to steam pressure.
本願第１番目の発明は、半導体素子を搭載するタブと、
該タブの周辺にてこのタブと一体に接続したリード群と
からなるリードフレームであって、タブの少なくとも一
箇所にタブの素子搭載前に対して斜めの部分（テーバ部
）を有する貫通穴が形成されていることを特徴とする
この貫通穴はタブの板厚方向に対して全体に傾斜してい
る態様、タブの板厚内にてくびれ部を形成している態様
等が挙げられる。The first invention of the present application is a tab on which a semiconductor element is mounted,
A lead frame consisting of a group of leads integrally connected to the tab around the tab, the tab having at least one through hole having an oblique portion (tapered portion) with respect to the tab before the element is mounted. This through-hole is formed in such a manner that it is entirely inclined with respect to the thickness direction of the tab, and in that it forms a constriction within the thickness of the tab.
本願第２番目の発明は、半導体素子を搭載するタブと、
このタブの周辺にてこのタブと一体に接続したリード群
とからなるリードフレームであって、タブの少なくとも
一箇所に素子搭載側面積が反素子搭載側面積よりも大と
なるような貫通穴が開いていることを特徴とする。The second invention of the present application is a tab on which a semiconductor element is mounted,
A lead frame consisting of a group of leads integrally connected to the tab around the tab, and at least one part of the tab has a through hole such that the lateral area for mounting the element is larger than the lateral area for mounting the element. Characterized by being open.
本願第３番目の発明は、半導体素子とこの半導体素子を
搭載するタブと、このタブの周辺にてこのタブと一体に
接続したリード群と、このリード群の内のインナーリー
ド部及びタブ並びに半導体素子を封止する樹脂部とを備
えた半導体装置において、タブの少なくとも一箇所にこ
のタブの素子搭載面に対して斜めの部分を有する貫通孔
が形成されていることを特徴とする。The third invention of the present application is a semiconductor element, a tab on which the semiconductor element is mounted, a group of leads integrally connected to the tab around the tab, an inner lead portion of the lead group, the tab, and the semiconductor. A semiconductor device including a resin portion for sealing an element is characterized in that a through hole having a portion oblique to the element mounting surface of the tab is formed in at least one location of the tab.
この貫通穴はタブの板厚方向に対して全体に傾斜してい
る態様、タブの板厚内にくびれ部を形成している態様、
素子搭載側の穴面積が反素子搭載側の穴面積よりも大と
なるように開けられた態様等が挙げられる。A mode in which this through hole is entirely inclined with respect to the plate thickness direction of the tab, a mode in which a constriction part is formed within the plate thickness of the tab,
Examples include a mode in which the hole area on the element mounting side is larger than the hole area on the side opposite to the element mounting side.
更に本願第１〜第３番目の発明、。共通り、１１貫通穴
の素子搭載面側面積はタブの素子搭載面側面積の２４％
以上からタブと素子との接合面積の８０％以下の範囲に
あることが望ましく、またタブの素子搭載面の貫通穴の
周囲には溝を設けることが好ましい。Furthermore, the first to third inventions of the present application. Commonly, the element mounting surface area of the 11 through hole is 24% of the element mounting surface area of the tab.
From the above, it is desirable that the area be within 80% of the bonding area between the tab and the element, and it is also preferable that a groove be provided around the through hole on the element mounting surface of the tab.
リフロークラックが生じるタブ下面コーナ部の樹脂部の
応力を概略的に求めるには、タブ下方の樹脂部を第５図
に示すように一様の圧力がかかる周辺拘束の長方形平板
にモデル化すれば良い、このとき、最大の応力は、長辺
中央に発生し、その値は次式で与えられる。To roughly determine the stress in the resin part at the bottom corner of the tab where reflow cracks occur, model the resin part at the bottom of the tab as a rectangular flat plate with peripheral restraints that are subject to uniform pressure, as shown in Figure 5. In this case, the maximum stress occurs at the center of the long side, and its value is given by the following equation.
ここで、βは長辺と短辺の長さの比で決まる応力係数、
ａは短辺の長さ、ｈは板厚、ｐは水蒸気の圧力を表わす
。（１）式から明らかなように、応力を低減するには、
短辺の長さを短くするか、或いは板厚を厚くすれば良い
、ところが、板厚を厚くするということは、パッケージ
を厚くすることになり、例えばフラットパッケージのよ
うに薄形を特徴とするパッケージには適用できない、ま
た、タブの寸法は、チップの寸法より小さくできないの
で、チップ寸法により決定される。Here, β is the stress coefficient determined by the ratio of the length of the long side and the short side,
a represents the length of the short side, h represents the plate thickness, and p represents the pressure of water vapor. As is clear from equation (1), to reduce stress,
All you have to do is shorten the length of the short side or make the board thicker. However, increasing the board thickness means making the package thicker. For example, if the package is thin, like a flat package. It is not applicable to packages, and the tab dimensions cannot be smaller than the chip dimensions, so they are determined by the chip dimensions.
そこで本発明では、タブの一部に樹脂拘束部を設け、タ
ブの剥離部分を分割した。これにより実効的なタブ寸法
ａが小さくなるので、樹脂部の応力が低減し、樹脂部の
りフロークラックを防止することができる。Therefore, in the present invention, a resin restraining portion is provided in a part of the tab, and the peeling portion of the tab is divided. This reduces the effective tab dimension a, thereby reducing stress in the resin part and preventing glue flow cracks in the resin part.
以下、本発明のリードフレーム及び半導体装置の実施例
につき図面に従って説明する。Embodiments of a lead frame and a semiconductor device of the present invention will be described below with reference to the drawings.
第１図は本発明の一実施例に係るリードフレームの部分
斜視図であり、第２図はこれを用いた半導体装置の断面
図である。FIG. 1 is a partial perspective view of a lead frame according to an embodiment of the present invention, and FIG. 2 is a sectional view of a semiconductor device using the lead frame.
本実施例ではタブ１はその両端をタブ吊リード３にて支
障され、略中央に貫通穴２を形成している。この貫通穴
２は第２図の断面からも明らかなように素子４方向に次
第に広がり素子４とは反対の側に徐々に狭くなっている
。尚、第２図において符号５は樹脂部、６は水蒸気、７
はリード、８は半田、９は基板を示す。In this embodiment, the tab 1 is blocked by tab suspension leads 3 at both ends thereof, and has a through hole 2 formed approximately in the center. As is clear from the cross section of FIG. 2, this through hole 2 gradually widens in the direction of the element 4 and gradually narrows toward the side opposite to the element 4. In FIG. 2, numeral 5 is a resin part, 6 is water vapor, and 7 is a resin part.
8 represents a lead, 8 represents solder, and 9 represents a substrate.
タブ１と樹脂部５の界面に水蒸気６が発生し、この圧力
により樹脂部５が膨らんでいる。このとき、タブ下面コ
ーナ部の樹脂部５に応力が発生するが、本実施例による
タブ１の貫通穴２が樹脂部５を拘束するので、第２図と
第６図（従来図）を比較してわかるように、８寸法は従
来のタブの２分の１以下になる。従って、（１）式より
発生する応力を４分の１以下に低減することができ、リ
フロークラックが防止できる。Water vapor 6 is generated at the interface between the tab 1 and the resin part 5, and the resin part 5 swells due to this pressure. At this time, stress is generated in the resin part 5 at the bottom corner of the tab, but the through hole 2 of the tab 1 according to this embodiment restrains the resin part 5. Compare FIG. 2 and FIG. 6 (conventional diagram). As can be seen, the 8-dimensional tab is less than half the size of the conventional tab. Therefore, the stress generated from equation (1) can be reduced to one-fourth or less, and reflow cracks can be prevented.
本発明の第２実施例、第３実施例を第３図、第４図に示
す。第２実施例では、貫通穴２の反素子搭載面における
面積よりも小さい面積の部分が貫通穴２の内部に設けら
れている。また、第３実施例では、貫通穴２がタブ１に
対して斜めに開けられている。タブに対する貫通穴の傾
き角は、概略１０°程度で充分である。両実施例とも樹
脂部が貫通穴２に入り込んでタブ１に樹脂部が拘束され
るので、第１実施例と同様にしてリフロークラックの防
止が図れる。A second embodiment and a third embodiment of the present invention are shown in FIGS. 3 and 4. In the second embodiment, a portion having an area smaller than the area of the through hole 2 on the surface opposite to the element mounting surface is provided inside the through hole 2. Further, in the third embodiment, the through hole 2 is opened diagonally with respect to the tab 1. An angle of inclination of the through hole relative to the tab of approximately 10° is sufficient. In both embodiments, the resin part enters the through hole 2 and is restrained by the tab 1, so that reflow cracks can be prevented in the same manner as in the first embodiment.
本発明の貫通穴の平面形状は、第１図に示すような円形
である必要はなく、だ円形、矩形、十字形でも同様の効
果がある。また、貫通穴の数は。The planar shape of the through-hole of the present invention does not have to be circular as shown in FIG. 1; oval, rectangular, or cruciform shapes can also have the same effect. Also, the number of through holes.
タブ１に必要な剛性を損わない程度に複数個設けること
により、より一層の効果を上げることができる。By providing a plurality of tabs to the extent that the necessary rigidity of the tab 1 is not impaired, further effects can be obtained.
貫通穴に入り込んだ樹脂部に生じる応力σゎは。What is the stress σ that occurs in the resin part that has entered the through hole?
Ａｔ
で表わされる。ここで、Ａｔはタブの面積、Ａｈは穴の
内側の面積の最小値である。この応力が、樹脂部の破壊
応力σＢを超えると、樹脂部が破壊するので、次式が成
り立たなくてはならない。It is expressed as At. Here, At is the area of the tab, and Ah is the minimum value of the area inside the hole. If this stress exceeds the breaking stress σB of the resin part, the resin part will be destroyed, so the following equation must hold true.
従って、
Ａ ｈ ＞ Ａ ｔ ・・
・（４）σ Ｂ
通常、半田リフロ一時には、パッケージは約２２０℃に
加熱され、この温度における水の飽和蒸気圧は０．２４
ｋｇｆ／ｍ”である、また、コノ温度ニオける樹脂部の
破壊応力は約１ ｋｇ ｆ ／ ｍ”であるから、これ
らの値を（４）式に代入して、Ａｈ＞０．２４Ａ！
・・・（５）すなわち、穴の最小面積
は、タブの面積の２４％以上にすることが望ましい。Therefore, A h > A t ・・
・(4) σ B Normally, during solder reflow, the package is heated to about 220°C, and the saturated vapor pressure of water at this temperature is 0.24
kgf/m", and the breaking stress of the resin part at a constant temperature is approximately 1 kgf/m", so by substituting these values into equation (4), Ah>0.24A!
(5) That is, it is desirable that the minimum area of the hole be 24% or more of the area of the tab.
また貫通穴が過度に大きくなるとタブの剛性が低下する
ので、チップ搭載面に凹凸が生じ、チップとタブとの接
合が国運となる。更にワイヤボンディングの際に、タブ
の反素子搭載面から加える熱が、チップに伝わりにくく
なる。従って貫通穴の大きさに最適には上限があり１本
発明者等の実験確認によれば貫通穴の面積は搭載するチ
ップの８０％以下が望ましい。穴上記の範囲は各貫通穴
毎にもまた貫通穴の統計に対しても適用し得る。Furthermore, if the through-hole becomes too large, the rigidity of the tab will decrease, resulting in unevenness on the chip mounting surface, and the bonding of the chip and tab will become a problem. Furthermore, during wire bonding, heat applied from the surface of the tab opposite to the element mounting surface is less likely to be transmitted to the chip. Therefore, there is an optimum upper limit to the size of the through hole, and according to experimental confirmation by the present inventors, the area of the through hole is preferably 80% or less of the chip to be mounted. Holes The above ranges can be applied for each through hole as well as for the statistics of the through holes.
次に１本発明による貫通穴の製造方法について述べる。Next, a method for manufacturing a through hole according to the present invention will be described.
第７図に従来のエツチング技術でタブに貫通穴をあける
方法を示す、タブの両側に同一形状のエツチングパター
ン１４ａ、１４ｂを密着し、エツチング液１５の中に浸
漬する。エツチングは、タブの両面から進行するので、
第８図のように、わずかに中央部が狭い穴があく、シか
し、従来の方法では、穴の内側の面積がほとんど一様な
ので。FIG. 7 shows a method of making a through hole in a tab using a conventional etching technique.Etching patterns 14a and 14b of the same shape are closely attached to both sides of the tab, and the tab is immersed in an etching solution 15. Etching progresses from both sides of the tab, so
As shown in Figure 8, in the conventional method, a hole is created that is slightly narrow in the center, but the area inside the hole is almost uniform.
樹脂が入り込んでも、これを拘束するには至らない。Even if the resin gets inside, it will not be enough to restrain it.
第９図に、本発明の第２実施例の貫通穴をあける方法を
示す。タブ上面のエツチングパターン１４ｃの穴は、下
面のエツチングパターン１４ｄの穴より大きい、このよ
うな状態でエツチング液１５に浸漬すると、第１０図の
ような穴があくので、第２実施例を実現することができ
る。FIG. 9 shows a method for making a through hole according to a second embodiment of the present invention. The holes in the etching pattern 14c on the top surface of the tab are larger than the holes in the etching pattern 14d on the bottom surface.If the tab is immersed in the etching solution 15 in this state, holes as shown in FIG. 10 will be formed, so that the second embodiment can be realized. be able to.
第１１図に、本発明の第３実施例の貫通穴をあける方法
を示す、エツチングパターン１４ｅ。FIG. 11 shows an etching pattern 14e showing a method of making a through hole according to a third embodiment of the present invention.
４ｆの穴の大きさは等しいが、位置がずれている６従っ
て、第１２図のように、タブに対して斜めにあいた穴、
すなわち、第３実施例を実現することができる。The holes 4f are of the same size, but their positions are different.6 Therefore, as shown in Figure 12, the holes diagonally to the tab,
That is, the third embodiment can be realized.
第１３図に、プレスにより本発明を実現する方法を示す
。まず、従来の技術により、タブに貫通穴をあけ、この
部分に凸形のプレス金型１６ａをプレスする。この方法
により、第１４図に示すように、反素子搭載面における
穴の内側の面積よりも大きな面積の部分を設けることが
できる・次に本発明の第４実施例を第１５図及び第１６
図に基づいて説明する。タブの貫通孔はテーパにはなっ
ていないが素子搭載面は反素子搭載面よりも穴径が大き
い、また本実施例では減肉部１７が形成されている。更
に穴は複数設けられている。FIG. 13 shows a method of implementing the invention using a press. First, using a conventional technique, a through hole is made in the tab, and a convex press die 16a is pressed into this hole. By this method, as shown in FIG. 14, it is possible to provide a portion with a larger area than the inside area of the hole on the anti-element mounting surface.Next, the fourth embodiment of the present invention is shown in FIGS.
This will be explained based on the diagram. Although the through hole of the tab is not tapered, the hole diameter on the element mounting surface is larger than that on the opposite element mounting surface, and in this embodiment, a thinned portion 17 is formed. Furthermore, multiple holes are provided.
尚符号１８はダイボンディング材である。Note that the reference numeral 18 is a die bonding material.
第１５図はタブ１に貫通穴２を設け、かつ、タブ１上部
に減肉部１７を設けたものである。この構造によれば、
ダイボンディング材１８が索子４とタブ１の間を完全に
埋めていても樹脂部５はタブ上部に充填される。リフロ
ー半田付けの際にタブ１と樹脂部５が剥離しても、タブ
上部に充填された樹脂部の為、樹脂部５はタブ１から抜
は出ることはなく、蒸気圧による変形は第１６図のよう
になる。ここで、タブ残存部の最大幅ｄを次の式で与え
られる値以下にすれば、樹脂部にクラックは生じない。In FIG. 15, a through hole 2 is provided in the tab 1, and a thinned portion 17 is provided in the upper portion of the tab 1. According to this structure,
Even if the die bonding material 18 completely fills the space between the cord 4 and the tab 1, the resin portion 5 is filled in the upper part of the tab. Even if the tab 1 and the resin part 5 peel off during reflow soldering, the resin part 5 will not come out from the tab 1 because the resin part is filled in the upper part of the tab, and deformation due to vapor pressure will occur. It will look like the figure. Here, if the maximum width d of the tab remaining portion is set to be less than or equal to the value given by the following equation, no cracks will occur in the resin portion.
ここで、Ｋｔｃ：リフロ一温度における樹脂の破壊靭性
値
ｐ：リフロ一時に発生する蒸気圧
第１７図は他の実施例で貫通穴２を上部に広がる形状と
したものを複数形成したもので、これによっても上記と
同様の効果が出せる。これらの貫通穴２は円形でも良い
が、矩形に近い形または第１８図に示すような長円に近
い形のほうが補強効果は大である。Here, Ktc: Fracture toughness value of resin at one reflow temperature p: Vapor pressure generated during reflow FIG. 17 shows another embodiment in which a plurality of through holes 2 are formed in a shape that expands upward. This also produces the same effect as above. These through-holes 2 may be circular, but the reinforcing effect is greater if they have a shape that is close to a rectangle or a shape that is close to an ellipse as shown in FIG.
最後に、本発明を実施する際の問題点とこれを解決する
方法について述べる。第１９図は、本発明のタブ１に素
子を接合するため、接着剤１８を塗布した状態を示した
ものである。第２０図は、第１９図の状態の後に、素子
４を搭載し、接合した状態を示す。図に示すように、接
着剤１８の量が過多であると、貫通穴２の側面に接着剤
１８が流れ出す恐れがある。第２０図の状態で、接着剤
が硬化した後に樹脂部をモールドすると、樹脂部と接着
剤との間にはく離が生じ易く、本発明の効果がなくなる
恐れがある。Finally, problems encountered when implementing the present invention and methods for solving them will be described. FIG. 19 shows a state in which an adhesive 18 is applied to the tab 1 of the present invention in order to bond an element. FIG. 20 shows a state in which the element 4 is mounted and bonded after the state shown in FIG. 19. As shown in the figure, if the amount of adhesive 18 is too large, there is a risk that adhesive 18 will flow out onto the side surface of through hole 2. If the resin part is molded after the adhesive has hardened in the state shown in FIG. 20, peeling is likely to occur between the resin part and the adhesive, and the effect of the present invention may be lost.
このような問題点を解決するには、第２１図に示すよう
に、タブ１の素子搭載面の貫通穴のまわりに接着剤１７
の流出防止溝１９を設ければ良い。In order to solve this problem, as shown in FIG.
What is necessary is to provide the outflow prevention groove 19.
第２２図は、接着剤流出防止溝１９を設けたタブ１に素
子４を搭載した状態を示す。図に示すように、余分な接
着剤は、溝１８に留められるので。FIG. 22 shows a state in which the element 4 is mounted on the tab 1 provided with the adhesive outflow prevention groove 19. As shown in the figure, excess adhesive is retained in the groove 18.
貫通穴に流れ出すことはなくなる。It will no longer flow out into the through hole.
本発明によれば、タブと樹脂部が剥離したときのタブ下
方の樹脂部を拘束する距離が短くなるので、水蒸気の圧
力による樹脂部の応力が低減し、リフロークラックを防
止することができる。According to the present invention, when the tab and the resin part are separated, the distance for restraining the resin part below the tab is shortened, so stress in the resin part due to water vapor pressure is reduced, and reflow cracks can be prevented.
第１図、第１８図は夫々本発明の一実施例に係るリード
フレームの一部分を示す斜視図、第２図は第１図の実施
例を適用した半導体装置の一実施例の断面図、第３図及
び第４図は夫々本発明の他の実施例に係るリードフレー
ムの部分断面図、第５図はリードフレームの応力計算に
用いる計算モデルの斜視図、第６図は従来例に係る半導
体装置の断面図、第７図及び第８図は夫々従来例に係る
リードフレームの貫通穴形成工程を示すリードフレーム
の部分断面図、第９図、第１０図、第１１図、第１２図
、第１４図、第１９図、第２１図は夫々本発明の実施例
に係るリードフレームの貫通穴形成工程を示すリードフ
レームの部分断面図。
第１３図は同じく貫通穴形成工程を示すリードフレーム
及びプレス金型の部分断面図、第１５図。
第１６図、第１７図は夫々本発明の他の実施例に係る半
導体装置の断面図、第２０図は第１９図の実施例に係る
リードフレームに素子を搭載した状態の断面図、第２２
図は第２１図の実施例に係るリードフレームに素子を搭
載した状態の断面図である。
１・・・タブ、２・・・貫通穴、３・・・タブ吊リード
、４・・・素子、５・・・樹脂部、６・・・水蒸気、７
・・・リード、８・・・半田、９・・・基板、１８・・
・グイボンディング材、１９・・・接着剤流出防止溝。
゛ ・°ンｉ、’ 、−ｊ′：
′。
代理人 弁理士 小川勝男゛・−と゛ノ第１凹
！・・・表本夕、
第牛図
１６°゛７ルス毫閂1 and 18 are respectively perspective views showing a part of a lead frame according to an embodiment of the present invention, and FIG. 2 is a sectional view of an embodiment of a semiconductor device to which the embodiment of FIG. 1 is applied. 3 and 4 are partial cross-sectional views of lead frames according to other embodiments of the present invention, FIG. 5 is a perspective view of a calculation model used for stress calculation of the lead frame, and FIG. 6 is a diagram of a semiconductor according to a conventional example. 7 and 8 are partial sectional views of the lead frame, respectively, showing the step of forming a through hole in a lead frame according to a conventional example; FIG. 9, FIG. 10, FIG. 11, and FIG. 12; FIG. 14, FIG. 19, and FIG. 21 are partial cross-sectional views of a lead frame showing a step of forming a through hole in the lead frame according to an embodiment of the present invention. FIG. 13 is a partial sectional view of the lead frame and press mold, similarly showing the through hole forming process, and FIG. 15. 16 and 17 are respectively sectional views of semiconductor devices according to other embodiments of the present invention, FIG. 20 is a sectional view of a state in which an element is mounted on a lead frame according to the embodiment of FIG. 19, and FIG.
This figure is a sectional view of a state in which an element is mounted on the lead frame according to the embodiment of FIG. 21. DESCRIPTION OF SYMBOLS 1...Tab, 2...Through hole, 3...Tab suspension lead, 4...Element, 5...Resin part, 6...Water vapor, 7
... Lead, 8... Solder, 9... Board, 18...
・Gui bonding material, 19...Adhesive outflow prevention groove.゛ ・°ni,' ,−j′:
'. Agent Patent Attorney Katsuo Ogawa゛・- and ゛No.1 concavity!・・・Omotemoto Yu, No. 16°
Claims (1)
タブと一体に接続したリード群とからなるリードフレー
ムにおいて、前記タブの少なくとも一箇所に該タブの素
子搭載前に対して斜めの部分を有する貫通穴が形成され
ていることを特徴とするリードフレーム。 ２、前記貫通穴がタブの板厚方向に対して全体に傾斜し
ていることを特徴とする特許請求の範囲第１項記載のリ
ードフレーム。 ３、前記貫通穴がタブの板厚内にてくびれ部を形成して
いることを特徴とする特許請求の範囲第１項記載のリー
ドフレーム。 ４、前記貫通穴の素子搭載面側面積はタブの素子搭載面
側面積の２４％以上からタブと素子との接合面積の８０
％以下までの範囲にあることを特徴とする特許請求の範
囲第１項乃至第３項いずれか記載のリードフレーム。 ５、前記タブの素子搭載面の貫通穴の周囲に溝を設ける
ことを特徴とする特許請求の範囲第１項乃至第４項いず
れか記載のリードフレーム。 ６、半導体素子を搭載するタブと、該タブの周辺にて該
タブと一体に接続したリード群とからなるリードフレー
ムにおいて、前記タブの少なくとも一箇所に素子搭載側
面積が反素子搭載側面積よりも大となるような貫通穴が
開いていることを特徴とするリードフレーム。 ７、前記貫通穴の素子搭載面側面積はタブの素子搭載面
側面積の２４％以上からタブと素子との接合面積の８０
％以下までの範囲にあることを特徴とする特許請求の範
囲第６項記載のリードフレーム。 ８、前記タブの素子搭載面の貫通穴の周囲に溝を設ける
ことを特徴とする特許請求の範囲第６項又は第７項記載
のリードフレーム。 ９、半導体素子と、該半導体素子を搭載するタブと、該
タブの周辺にて該タブと一体に接続したリード群と、該
リード群の内のインナーリード部及びタブ並びに半導体
素子を封止する樹脂部とを備えた半導体装置において、
前記タブの少なくとも一箇所に該タブの素子搭載面に対
して斜めの部分を有する貫通穴が形成されていることを
特徴とする半導体装置。 １０、前記貫通穴がタブの板厚方向に対して全体に傾斜
していることを特徴とする特許請求の範囲第９項記載の
半導体装置。 １１、前記貫通穴がタブの板厚内にくびれ部を形成して
いることを特徴とする特許請求の範囲第９項記載の半導
体装置。 １２、前記貫通穴の素子搭載面側面積が反素子搭載側面
積よりも大となるように開けられていることを特徴とす
る特許請求の範囲第９項記載の半導体装置。 １３、前記貫通穴の素子搭載面側面積はタブの素子搭載
面側面積の２４％以上からタブと素子との接合面積の８
０％以下までの範囲にあることを特徴とする特許請求の
範囲第９項乃至第１２項いずれか記載の半導体装置。 １４、前記タブの素子搭載面の貫通穴の周囲に溝を設け
ることを特徴とする特許請求の範囲第９項乃至第１３項
いずれか記載の半導体装置。[Claims] 1. In a lead frame consisting of a tab on which a semiconductor element is mounted and a group of leads integrally connected to the tab around the tab, the element of the tab is mounted on at least one part of the tab. A lead frame characterized in that a through hole is formed with a portion oblique to the front. 2. The lead frame according to claim 1, wherein the through hole is entirely inclined with respect to the thickness direction of the tab. 3. The lead frame according to claim 1, wherein the through hole forms a constriction within the thickness of the tab. 4. The device mounting surface area of the through hole is 24% or more of the device mounting surface area of the tab to 80% of the bonding area between the tab and the device.
The lead frame according to any one of claims 1 to 3, characterized in that the lead frame is within a range of % or less. 5. The lead frame according to any one of claims 1 to 4, wherein a groove is provided around the through hole in the element mounting surface of the tab. 6. In a lead frame consisting of a tab on which a semiconductor element is mounted and a group of leads integrally connected to the tab around the tab, at least one part of the tab has a side area on which the element is mounted, which is larger than an area on the opposite side where the element is mounted. A lead frame characterized by a through hole that is large in size. 7. The device mounting surface area of the through hole is 24% or more of the device mounting surface area of the tab to 80% of the bonding area between the tab and the device.
7. The lead frame according to claim 6, wherein the lead frame is within a range of up to %. 8. The lead frame according to claim 6 or 7, wherein a groove is provided around the through hole in the element mounting surface of the tab. 9. Sealing a semiconductor element, a tab on which the semiconductor element is mounted, a lead group integrally connected to the tab around the tab, an inner lead part of the lead group, the tab, and the semiconductor element. In a semiconductor device equipped with a resin part,
A semiconductor device characterized in that a through hole having a portion oblique to an element mounting surface of the tab is formed in at least one location of the tab. 10. The semiconductor device according to claim 9, wherein the through hole is entirely inclined with respect to the thickness direction of the tab. 11. The semiconductor device according to claim 9, wherein the through hole forms a constriction within the thickness of the tab. 12. The semiconductor device according to claim 9, wherein the through hole is formed so that the side area of the element mounting surface is larger than the side area opposite the element mounting surface. 13. The element mounting surface area of the through hole is 24% or more of the element mounting surface area of the tab to 8% of the bonding area between the tab and the element.
13. The semiconductor device according to any one of claims 9 to 12, characterized in that the amount is within a range of 0% or less. 14. The semiconductor device according to any one of claims 9 to 13, wherein a groove is provided around the through hole in the element mounting surface of the tab.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62056590A JPH0680760B2 (en) | 1987-03-13 | 1987-03-13 | Lead frame and semiconductor device |
| US07/158,673 US4942452A (en) | 1987-02-25 | 1988-02-22 | Lead frame and semiconductor device |
| US08/448,881 USRE37690E1 (en) | 1987-02-25 | 1995-05-24 | Lead frame and semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62056590A JPH0680760B2 (en) | 1987-03-13 | 1987-03-13 | Lead frame and semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63224245A true JPS63224245A (en) | 1988-09-19 |
| JPH0680760B2 JPH0680760B2 (en) | 1994-10-12 |
Family
ID=13031403
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62056590A Expired - Lifetime JPH0680760B2 (en) | 1987-02-25 | 1987-03-13 | Lead frame and semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0680760B2 (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH036851A (en) * | 1989-06-03 | 1991-01-14 | Shinko Electric Ind Co Ltd | Lead frame |
| JPH03178153A (en) * | 1989-12-07 | 1991-08-02 | Matsushita Electron Corp | Semiconductor device |
| EP0533137A2 (en) * | 1991-09-18 | 1993-03-24 | Fujitsu Limited | Leadframe and resin-sealed semiconductor device |
| JPH0722550U (en) * | 1993-09-22 | 1995-04-21 | サンケン電気株式会社 | Semiconductor device |
| US5982028A (en) * | 1995-02-28 | 1999-11-09 | Siemens Aktiengesellschaft | Semiconductor device with good thermal behavior |
| US6242802B1 (en) * | 1995-07-17 | 2001-06-05 | Motorola, Inc. | Moisture enhanced ball grid array package |
| JP2002058841A (en) * | 2000-08-22 | 2002-02-26 | Heiwa Corp | Synthetic resin unit for game machine and crack occurrence preventing method for synthetic resin unit |
| JP2009231742A (en) * | 2008-03-25 | 2009-10-08 | Shindengen Electric Mfg Co Ltd | Semiconductor device |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5253665A (en) * | 1975-10-29 | 1977-04-30 | Hitachi Ltd | Semiconductor device |
| JPS5332672A (en) * | 1976-09-07 | 1978-03-28 | Matsushita Electronics Corp | Lead frame for semiconductor device |
| JPS59177953A (en) * | 1983-03-28 | 1984-10-08 | Toshiba Corp | Semiconductor device |
| JPS6011825U (en) * | 1983-07-06 | 1985-01-26 | 富士重工業株式会社 | Vehicle roof opening structure |
| JPS60118252U (en) * | 1984-01-18 | 1985-08-09 | 沖電気工業株式会社 | Lead frame for resin-sealed semiconductor devices |
| JPS6215845A (en) * | 1985-07-12 | 1987-01-24 | Shinko Electric Ind Co Ltd | Manufacture of lead frame |
-
1987
- 1987-03-13 JP JP62056590A patent/JPH0680760B2/en not_active Expired - Lifetime
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5253665A (en) * | 1975-10-29 | 1977-04-30 | Hitachi Ltd | Semiconductor device |
| JPS5332672A (en) * | 1976-09-07 | 1978-03-28 | Matsushita Electronics Corp | Lead frame for semiconductor device |
| JPS59177953A (en) * | 1983-03-28 | 1984-10-08 | Toshiba Corp | Semiconductor device |
| JPS6011825U (en) * | 1983-07-06 | 1985-01-26 | 富士重工業株式会社 | Vehicle roof opening structure |
| JPS60118252U (en) * | 1984-01-18 | 1985-08-09 | 沖電気工業株式会社 | Lead frame for resin-sealed semiconductor devices |
| JPS6215845A (en) * | 1985-07-12 | 1987-01-24 | Shinko Electric Ind Co Ltd | Manufacture of lead frame |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH036851A (en) * | 1989-06-03 | 1991-01-14 | Shinko Electric Ind Co Ltd | Lead frame |
| JPH03178153A (en) * | 1989-12-07 | 1991-08-02 | Matsushita Electron Corp | Semiconductor device |
| EP0533137A2 (en) * | 1991-09-18 | 1993-03-24 | Fujitsu Limited | Leadframe and resin-sealed semiconductor device |
| US5367191A (en) * | 1991-09-18 | 1994-11-22 | Fujitsu Limited | Leadframe and resin-sealed semiconductor device |
| US5753535A (en) * | 1991-09-18 | 1998-05-19 | Fujitsu Limited | Leadframe and resin-sealed semiconductor device |
| JPH0722550U (en) * | 1993-09-22 | 1995-04-21 | サンケン電気株式会社 | Semiconductor device |
| US5982028A (en) * | 1995-02-28 | 1999-11-09 | Siemens Aktiengesellschaft | Semiconductor device with good thermal behavior |
| US6242802B1 (en) * | 1995-07-17 | 2001-06-05 | Motorola, Inc. | Moisture enhanced ball grid array package |
| JP2002058841A (en) * | 2000-08-22 | 2002-02-26 | Heiwa Corp | Synthetic resin unit for game machine and crack occurrence preventing method for synthetic resin unit |
| JP2009231742A (en) * | 2008-03-25 | 2009-10-08 | Shindengen Electric Mfg Co Ltd | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0680760B2 (en) | 1994-10-12 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |