JPH0680760B2 - Lead frame and semiconductor device - Google Patents

Lead frame and semiconductor device

Info

Publication number
JPH0680760B2
JPH0680760B2 JP62056590A JP5659087A JPH0680760B2 JP H0680760 B2 JPH0680760 B2 JP H0680760B2 JP 62056590 A JP62056590 A JP 62056590A JP 5659087 A JP5659087 A JP 5659087A JP H0680760 B2 JPH0680760 B2 JP H0680760B2
Authority
JP
Japan
Prior art keywords
tab
hole
slit
shaped
mounting surface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP62056590A
Other languages
Japanese (ja)
Other versions
JPS63224245A (en
Inventor
誠 北野
末男 河合
朝雄 西村
英生 三浦
昭弘 立道
千加子 北林
一男 清水
俊雄 初田
敏範 尾崎
敏雄 服部
荘司 坂田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP62056590A priority Critical patent/JPH0680760B2/en
Priority to US07/158,673 priority patent/US4942452A/en
Publication of JPS63224245A publication Critical patent/JPS63224245A/en
Publication of JPH0680760B2 publication Critical patent/JPH0680760B2/en
Priority to US08/448,881 priority patent/USRE37690E1/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はリードフレーム及び半導体装置に係り、特にリ
フロー半田付け時の加熱による樹脂クラツク防止に好適
なリードフレーム及び半導体装置に関する。
Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lead frame and a semiconductor device, and more particularly to a lead frame and a semiconductor device suitable for preventing resin crack due to heating during reflow soldering.

〔従来の技術〕[Conventional technology]

樹脂封止型の半導体装置では従来のピン挿入タイプに代
わり、基板に直接リードを半田付けする面付実装タイプ
が主流になりつつある。このようなパツケージでは、高
温高湿環境で保存すると樹脂が水分を吸収し、半田付加
熱時(リフロー時)に水分がタブ(素子搭載部のこと。
以下本願において同じ。)と樹脂部との界面で蒸気にな
り、タブ下面コーナ部にクラツクが生じ易い。このクラ
ツクは、半田リフロー時に発生する為、俗にリフローク
ラツクと呼ばれている。
In the resin-sealed semiconductor device, a surface mounting type in which leads are directly soldered to a substrate is becoming the mainstream instead of the conventional pin insertion type. In such a package, the resin absorbs water when stored in a high-temperature and high-humidity environment, and when the heat is applied to the solder (during reflow), the water is a tab (element mounting part).
The same applies hereinafter in this application. ) And the resin portion form steam at the interface, and cracks are likely to occur at the tab bottom corner portion. Since this crack occurs during solder reflow, it is commonly called a reflow crack.

このようなリフロークラツクを防止する従来技術として
は、特開昭60−208847号公報に記載のようにパツケージ
の裏面に穴をあけ、発生する蒸気を逃がす方法がある。
As a conventional technique for preventing such a reflow crack, there is a method of making a hole in the back surface of the package and allowing the generated vapor to escape, as described in JP-A-60-208847.

また、樹脂部とタブの界面の接着強さを向上させ、すき
まを防止する技術として、タブの反素子搭載面に凹凸を
設ける方法として特開昭58−199548号公報,同60−1860
44号公報に示される技術、更にタブ相当部に穴を形成し
たものとして同59−16357号公報に記載の技術がある。
Further, as a technique for improving the adhesive strength at the interface between the resin portion and the tab and preventing the clearance, as a method of providing unevenness on the anti-element mounting surface of the tab, JP-A-58-199548 and 60-1860.
There is a technique disclosed in JP-A-44-16357 and a technique described in JP-A-59-16357 in which a hole is formed in a portion corresponding to a tab.

〔発明が解決しようとする課題〕[Problems to be Solved by the Invention]

上記従来技術のうち、パツケージ下面に穴をあける方法
は、リフロークラツクは妨げるもののパツケージ外部と
内部に水分の通路を作ることになり、チツプ電極の腐食
が生じる可能性がある。
Among the above-mentioned conventional techniques, the method of forming a hole in the lower surface of the package, although it interferes with the reflow crack, creates a moisture passage inside and outside the package, which may cause corrosion of the chip electrode.

また、タブの反素子搭載面(素子搭載側面の裏側面のこ
と。以下同じ。)に単純な凹凸を設ける方法はタブと樹
脂部との接着面内の変位を拘束する効果はあるものの、
両者を引き離す方向の変位については、凹部に入り込ん
だ樹脂部が簡単に抜けるために効果が期待できない。
Further, although a method of providing a simple unevenness on the anti-element mounting surface of the tab (the back surface of the element mounting side surface; the same applies hereinafter) has the effect of restraining the displacement within the bonding surface between the tab and the resin portion,
With respect to the displacement in the direction in which the two are separated, the effect cannot be expected because the resin portion that has entered the recess is easily removed.

樹脂封止半導体をリフロー半田付けする際に、樹脂中に
含まれた水分が気化し、この蒸気圧がタブ〜樹止界面に
あるボイド又は非接着部等の空孔作用し、タブー樹脂界
面の剥離を進行させる。剥離進行によつて空孔が大きく
なつても、周囲の水分が拡散により供給され、この結
果、空孔の圧力は緩和されず、樹脂部は変形し、タブ端
部の最大応力発生個所を起点にクラツクを生じる(第6
図のクラツク10参照)。前記の特開昭59−16357号公報
ではタブの一部を抜き去り、この部分に樹脂を充填する
技術が開示されている。この技術を用いて熱応力による
剥離を防ぐとともに、等価的に樹脂部の厚さを増大させ
ることにより、耐湿性の向上がある程度は図れる。しか
し、リフロー半田付け時の蒸気圧により、樹脂部がタブ
から剥離した場合に生ずる変形により、最大応力発生個
所の応力はタブの一部を抜き去られない場合と大差な
く、この構造では、リフロー半田付けの際の樹脂部割れ
に対する効果は充分ではない。
When the resin-sealed semiconductor is reflow-soldered, the water contained in the resin is vaporized, and this vapor pressure acts as voids in the tab-resin interface or voids in the non-adhesive interface, etc. Let the peeling proceed. Even if the holes become larger as the peeling progresses, the surrounding water is supplied by diffusion, and as a result, the pressure in the holes is not relaxed, the resin part deforms, and the point where the maximum stress occurs at the tab end is the starting point. A crack is generated (6th
(See crack 10 in the figure). The aforementioned Japanese Patent Laid-Open No. 59-16357 discloses a technique of removing a part of the tab and filling the part with resin. By using this technique to prevent peeling due to thermal stress and equivalently increase the thickness of the resin portion, the moisture resistance can be improved to some extent. However, due to the vapor pressure during reflow soldering, the resin part is deformed when it is separated from the tab, and the stress at the maximum stress generation point is not much different from when the tab cannot be partially removed. The effect of cracking the resin portion during soldering is not sufficient.

実開昭60−118252号公報記載のように貫通孔をうず巻き
状(同公報第2図),X状(同公報第4図)にしたり、特
開昭53−32672号公報第3図(a)記載のように十字状
にしたりする提案があるが、めくれや上下方向のずれを
生じてタブの平滑度が維持できない。特開昭53−32672
号公報第2図,第3図(b)ではスリットが提案されて
いるが、その位置はタブの中心線に合致せず熱応力によ
る樹脂破壊を解消しきれない。
As described in Japanese Utility Model Laid-Open No. 60-118252, the through-holes may be formed in a spiral shape (Fig. 2 of the same publication) or an X shape (Fig. 4 of the same publication), or in Fig. 3 (a) of JP-A-53-32672. ), There is a proposal to make it a cross shape, but it is not possible to maintain the smoothness of the tab due to turning up and shifting in the vertical direction. JP-A-53-32672
Although a slit is proposed in FIGS. 2 and 3 (b) of the publication, the position thereof does not coincide with the center line of the tab, and the resin destruction due to thermal stress cannot be eliminated.

本発明の目的は蒸気圧により生じるリフロークラツク
を、タブをスリツトで分割して実効的なタブの短辺寸法
aを小さくすることにより防止することにある。
An object of the present invention is to prevent reflow cracks caused by vapor pressure by dividing the tabs with slits to reduce the effective short-side dimension a of the tabs.

〔課題を解決するための手段〕[Means for Solving the Problems]

上記目的は、タブに特殊な形状の貫通穴を設け、この穴
により樹脂部をタブに拘束し、リフロークラツクが生じ
るタブ下面コーナ部の樹脂部に発生する応力を低減する
ことにより達成される。
The above object is achieved by providing a through hole having a special shape in the tab, restraining the resin portion to the tab by this hole, and reducing the stress generated in the resin portion of the tab lower surface corner portion where reflow crack occurs. .

リフロー半田付けの際の樹脂クラツクを防ぐには、樹脂
部とタブが剥離しても、タブ端の最大応力発生個所に大
きな応力が生じないようにする必要がある。この要求
は、樹脂部とタブに付着力がなくなつた場合でも、樹脂
部の変形を防ぎ得る構造、すなわち、樹脂部が蒸気圧に
よりタブから抜け出ない構造により達成できる。
In order to prevent resin cracking during reflow soldering, it is necessary to prevent large stress from being generated at the maximum stress generation point at the tab end even if the resin portion and the tab are separated. This requirement can be achieved by a structure capable of preventing the deformation of the resin portion even when the resin portion and the tab lose their adhesive force, that is, a structure in which the resin portion does not come out of the tab due to vapor pressure.

本願第1番目の発明は、半導体素子を搭載するタブと、
該タブの周辺にてタブ吊りリードにより該タブと一体に
接続したリード群とからなり、1個または複数個の貫通
穴を備えたリードフレームにおいて、前記タブ全面の
内、少なくとも前記半導体素子が搭載される部位直下に
前記タブの長手方向に伸びる略長円のスリット状貫通穴
を形成し、かつスリット状貫通穴は素子搭載面側から反
素子搭載面側の方向への封止樹脂の抜け出るのを防止す
るように、貫通穴の素子搭載面側開口面と、反素子搭載
面側開口面と、板厚内の貫通穴で前記各開口面と平行な
任意の面との3つの内、いずれかが他の面と異なる面積
となるように形成しており、しかも少なくとも一本の前
記スリット状貫通穴の長手方向と前記タブの長辺に平行
な中心線の方向とが一致しており、かつこのスリット状
貫通穴は前記中心線上に位置することを特徴とする。
A first invention of the present application is a tab on which a semiconductor element is mounted,
At least the semiconductor element is mounted on the entire tab surface in a lead frame having one or a plurality of through holes around the tab and integrally connected to the tab by tab suspension leads. A slit-like through hole having a substantially oval shape extending in the longitudinal direction of the tab is formed immediately below the portion to be formed, and the slit-like through hole prevents the sealing resin from escaping from the element mounting surface side in the direction opposite to the element mounting surface side. In order to prevent the above, any of the three of the element mounting surface side opening surface of the through hole, the non-element mounting surface side opening surface, and an arbitrary surface parallel to each opening surface in the through hole within the plate thickness Is formed to have an area different from that of the other surface, and moreover, the longitudinal direction of at least one of the slit-shaped through holes and the direction of the center line parallel to the long side of the tab are aligned, And this slit-shaped through hole is the center line Characterized in that located.

この貫通穴はタブの板厚方向に対して全体に傾斜してい
る態様、タブの板厚内にてくびれ部を形成している態様
等が挙げられる。
Examples of the through hole include a mode in which the tab is entirely inclined with respect to the plate thickness direction and a mode in which a constricted portion is formed within the tab plate thickness.

本願第2番目の発明は、半導体素子と、該半導体素子を
搭載しかつ1個または複数個の貫通穴付きのタブと、該
タブの周辺に配置されるリード群と、該リード群の内の
インナーリード部及びタブ並びに前記半導体素子を封止
する樹脂部とを備えた半導体装置において、前記タブ全
面の内、少なくとも前記半導体素子が搭載される部位直
下に前記タブの長手方向に伸びる略長円のスリット状貫
通穴を形成し、かつスリット状貫通穴は素子搭載面側か
ら反素子搭載面側の方向への封止樹脂の抜け出るのを防
止するように、貫通穴の素子搭載面側開口面と、反素子
搭載面側開口面と、板厚内の貫通穴で前記各開口面と平
行な任意の面との3つの内、いずれかが他の面と異なる
面積となるように形成しており、しかも少なくとも一本
の前記スリット状貫通穴の長手方向と前記タブの長辺に
平行な中心線の方向とが一致しており、かつこのスリッ
ト状貫通穴は前記中心線上に位置することを特徴とす
る。
A second invention of the present application is to provide a semiconductor element, a tab on which the semiconductor element is mounted and which has one or a plurality of through holes, a lead group arranged around the tab, and a lead group among the lead group. In a semiconductor device including an inner lead portion, a tab, and a resin portion that seals the semiconductor element, a substantially oval shape extending in the longitudinal direction of the tab at least immediately below a portion on which the semiconductor element is mounted on the entire tab surface. The slit-shaped through hole is formed, and the slit-shaped through hole prevents the sealing resin from escaping from the element mounting surface side to the direction opposite to the element mounting surface side. And an anti-element mounting surface side opening surface and a through hole in the plate thickness, which is an arbitrary surface parallel to each opening surface, formed so that one of them has an area different from the other surface. And at least one of the slits The direction of the center line parallel to the long sides of the longitudinal direction as the tabs of the throughbore are matched, and the slit-shaped through hole and being located on said center line.

この貫通穴はタブの板厚方向に対して全体に傾斜してい
る態様、タブの板厚内にくびれ部を形成している態様、
素子搭載側の穴面積が反素子搭載側の穴面積よりも大と
なるように開けられた態様等が挙げられる。
This through hole is a mode in which the tab is entirely inclined with respect to the plate thickness direction, a mode in which a constricted portion is formed in the tab plate thickness,
Examples include a mode in which the hole area on the element mounting side is larger than the hole area on the non-element mounting side.

更に本願発明に共通して、貫通穴の素子搭載面側面積は
タブの素子搭載面側面積の24%以上からタブと素子との
接合面積の80%以下の範囲にあることが望ましく、また
タブの素子搭載面の貫通穴の周囲には溝を設けることが
好ましい。
Further, in common with the present invention, it is desirable that the area of the through hole on the element mounting surface side is within the range of 24% or more of the area on the element mounting surface side of the tab to 80% or less of the bonding area of the tab and the element. It is preferable to provide a groove around the through hole on the element mounting surface.

〔作用〕[Action]

リフロークラツクが生じるタブ下面コーナ部の樹脂部の
応力を概略的に求めるには、タブ下方の樹脂部を第5図
に示すように一様の圧力がかかる周辺拘束の長方形平板
にモデル化すれば良い。このとき、最大の応力は、長辺
中央に発生し、その値は次式で与えられる。
In order to roughly determine the stress in the resin portion of the tab underside corner where the reflow crack occurs, the resin portion under the tab should be modeled into a rectangular flat plate with peripheral restraint to which uniform pressure is applied as shown in FIG. Good. At this time, the maximum stress occurs at the center of the long side, and its value is given by the following equation.

ここで、βは長辺と短辺の長さの比で決まる応力係数、
aは短辺の長さ、hは板厚、pは水蒸気の圧力を表わ
す。(1)式から明らかなように、タブサイズaの2乗
で発生応力は増加する。従つて素子寸法が大きくなる
と、半田リフロークラツク(第6図符号10)が生じ易く
なる。従つて、応力を低減するには、短辺の長さを短く
するか、或いは板厚を厚くすれば良い。ところが、板厚
を厚くするということは、パツケージを厚くすることに
なり、例えばフラツトパツケージのように薄形を特徴と
するパツケージには適用できない。また、タブの寸法
は、チツプの寸法より小さくできないので、チツプ寸法
により決定される。
Where β is the stress coefficient determined by the ratio of the length of the long side to the length of the short side,
a is the length of the short side, h is the plate thickness, and p is the pressure of water vapor. As is clear from the equation (1), the generated stress increases with the square of the tab size a. Therefore, as the element size increases, solder reflow crack (reference numeral 10 in FIG. 6) easily occurs. Therefore, in order to reduce the stress, the length of the short side may be shortened or the plate thickness may be increased. However, increasing the plate thickness means increasing the thickness of the package, and cannot be applied to a package characterized by a thin shape, such as a flat package. Also, the size of the tab cannot be smaller than the size of the chip, so it is determined by the chip size.

そこで本発明では、タブの一部に樹脂拘束部としてタブ
の長手方向に伸びるスリットとして設け、a寸法を分割
して小さくすることによりタブの剥離部分を分割した。
これにより実効的なタブ寸法が小さくなるので、樹脂部
の応力が低減し、樹脂部のリフロークラックを防止する
ことができる。
Therefore, in the present invention, a peeled portion of the tab is divided by providing a resin restraining portion on a part of the tab as a slit extending in the longitudinal direction of the tab and dividing the dimension a to make it smaller.
As a result, the effective tab size is reduced, so that the stress in the resin portion is reduced and reflow cracks in the resin portion can be prevented.

単に丸穴の如く、距離を持たない貫通穴では、複数開口
としたとしてもタブ端面でaを分割できない位置があ
り、熱応力によりスリット間の樹脂の破壊が生じる恐れ
がある。
In a through hole having no distance, such as a round hole, there is a position where a cannot be divided at the tab end face even if a plurality of openings are formed, and there is a risk that the resin between the slits will be broken due to thermal stress.

少なくともタブの長手方向に設けたスリットが一本は必
要である。発生する応力はタブの短辺aで効くからであ
り、寸法aの分割こそ有効だからである。
At least one slit provided in the longitudinal direction of the tab is required. This is because the generated stress is effective on the short side a of the tab, and the division of the dimension a is effective.

また、スリットは第1図に示した通り、周辺を閉じられ
た直線状のものを示す。タブは平滑度を要するからであ
り、タブの加工時、保管時等のめくれ上がりを防ぐ趣旨
である。
Further, as shown in FIG. 1, the slit has a linear shape whose periphery is closed. This is because the tab requires smoothness and is intended to prevent the tab from being turned up when the tab is processed or stored.

タブの長手方向に設けるスリット状の貫通穴の位置は、
タブの長手方向の中心線上とする。第1の理由は、スリ
ット状貫通穴を設けるとタブは短辺の長さの異なる2つ
の長方形に分割されるが、これが中心線からずれると樹
脂に発生する応力が大きくなるからであり、第2の理由
は、チップの線膨張係数より樹脂の線膨張係数の方が大
きいことから貫通穴内の樹脂にせん断応力が発生して樹
脂を破壊し、樹脂拘束困難となるからであり、熱変形の
中心であるタブの中心線上にある限り熱応力はほとんど
0となってこの問題は免れる。
The position of the slit-shaped through hole provided in the longitudinal direction of the tab is
On the center line of the tab in the longitudinal direction. The first reason is that when the slit-shaped through hole is provided, the tab is divided into two rectangles having different short side lengths, but if this is deviated from the center line, the stress generated in the resin becomes large. The reason for No. 2 is that since the linear expansion coefficient of the resin is larger than the linear expansion coefficient of the chip, shear stress is generated in the resin in the through hole to break the resin and it becomes difficult to restrain the resin, which causes thermal deformation. As long as it is on the center line of the tab, which is the center, the thermal stress becomes almost zero, and this problem is avoided.

また、丸穴を複数設けることも考えられるが、素子とタ
ブとの接着面積を確保できなくなり、特に接着剤(ダイ
ボンディング剤)を付着させる領域と量が非常に限定さ
れてしまう。仮に貫通穴に接着剤が入り込めば係止効果
がなくなる。
Although it is conceivable to provide a plurality of round holes, it becomes impossible to secure the adhesion area between the element and the tab, and the area and amount to which the adhesive (die bonding agent) is attached are extremely limited. If the adhesive enters the through hole, the locking effect will be lost.

〔実施例〕〔Example〕

以下、本発明のリードフレーム及び半導体装置の実施例
につき図面に従つて説明する。
Embodiments of a lead frame and a semiconductor device of the present invention will be described below with reference to the drawings.

第1図は本発明の一実施例に係るリードフレームの部分
斜視図であり、第2図はこれを用いた半導体装置の断面
図である。
FIG. 1 is a partial perspective view of a lead frame according to an embodiment of the present invention, and FIG. 2 is a sectional view of a semiconductor device using the same.

本実施例ではタブ1はその両端をタブ吊リード3にて支
吊され、略中央にスリット状貫通穴(第1図に示したよ
うに、スリット内周は互いに平行な直線部分と、両端の
曲線部分とからなるものであり、長円に近いものとして
以下これを略長円と称する。略長円の貫通穴は補強効果
が大であり、タブの応力分割に効を奏し、かつタブの平
滑度を維持できる。)2を形成している。この貫通穴2
は第2図の断面からも明らかなように素子4方向に次第
に広がり素子4とは反対の側に徐々に狭くなつている。
尚、第2図において符号5は樹脂部、6は水蒸気、7は
リード、8は半田、9は基板を示す。
In this embodiment, the tab 1 is suspended at both ends by tab suspension leads 3, and a slit-shaped through hole is formed substantially in the center (as shown in FIG. 1, the slit inner circumferences are parallel straight portions and both ends are Since it is composed of a curved portion and is close to an ellipse, it is hereinafter referred to as a substantially ellipse.The through hole of the substantially ellipse has a large reinforcing effect, is effective in dividing the stress of the tab, and The smoothness can be maintained.) 2 is formed. This through hole 2
As is clear from the cross section of FIG. 2, the element gradually expands in the direction of the element 4 and becomes gradually narrower on the side opposite to the element 4.
In FIG. 2, reference numeral 5 is a resin portion, 6 is water vapor, 7 is a lead, 8 is solder, and 9 is a substrate.

タブ1と樹脂部5の界面に水蒸気6が発生し、この圧力
により樹脂部5が膨らんでいる。このとき、タブ下面コ
ーナ部の樹脂部5に応力が発生するが、本実施例による
タブ1の貫通穴2が樹脂部5を拘束するので、第2図と
第6図(従来図)を比較してわかるように、a寸法は従
来のタブの2分の1以下になる。従って、(1)式より
発生する応力を4分の1以下に低減することができ、リ
フロークラツクが防止できる。
Water vapor 6 is generated at the interface between the tab 1 and the resin portion 5, and the pressure causes the resin portion 5 to swell. At this time, stress is generated in the resin portion 5 at the corner portion of the lower surface of the tab, but the through hole 2 of the tab 1 according to the present embodiment restrains the resin portion 5, so that FIG. 2 and FIG. 6 (conventional drawing) are compared. As can be seen, the dimension a is less than half that of the conventional tab. Therefore, the stress generated by the equation (1) can be reduced to 1/4 or less, and reflow cracking can be prevented.

本発明の第2実施例,第3実施例を第3図,第4図に示
す。第2実施例では、貫通穴2の反素子搭載面における
面積よりも小さい面積の部分が貫通穴2の内部に設けら
れている。また、第3実施例では、貫通穴2がタブ1に
対して斜めに開けられている。タブに対する貫通穴の傾
き角は、概略10゜程度で充分である。両実施例とも樹脂
部が貫通穴2に入り込んでタブ1に樹脂部が拘束される
ので、第1実施例と同様にしてリフロークラツクの防止
が図れる。
A second embodiment and a third embodiment of the present invention are shown in FIGS. In the second embodiment, a portion having an area smaller than the area of the anti-element mounting surface of the through hole 2 is provided inside the through hole 2. In addition, in the third embodiment, the through hole 2 is formed obliquely with respect to the tab 1. The inclination angle of the through hole with respect to the tab is about 10 °. In both of the embodiments, the resin portion enters the through hole 2 and is restrained by the tab 1, so that the reflow crack can be prevented as in the first embodiment.

本発明の貫通穴の数は、タブ1に必要な剛性を損わない
程度に複数個設けることにより、より一層の効果を上げ
ることができる。
The effect of the present invention can be further improved by providing a plurality of through holes so that the tab 1 does not lose the necessary rigidity.

貫通穴に入り込んだ樹脂部に生じる応力σhは、 で表わされる。ここで、Atはタブの面積、Ahは穴の内側
の面積の最小値である。この応力が、樹脂部の破壊応力
σを超えると、樹脂部が破壊するので、次式が成り立
たなくてはならない。
The stress σh generated in the resin part that has entered the through hole is It is represented by. Here, At is the area of the tab and Ah is the minimum value of the area inside the hole. When this stress exceeds the fracture stress σ B of the resin portion, the resin portion breaks, and therefore the following equation must be established.

従つて、 通常、半田リフロー時には、パツケージは約220℃に加
熱され、この温度における水の飽和蒸気圧は0.24kgf/mm
2である。また、この温度における樹脂部の破壊応力は
約1kgf/mm2であるから、これらの値を(4)式に代入し
て、 Ah>0.24At …(5) すなわち、穴の最小面積は、タブの面積24%以上にする
ことが望ましい。
Therefore, Normally, during solder reflow, the package is heated to about 220 ° C, and the saturated vapor pressure of water at this temperature is 0.24 kgf / mm.
Is 2 . Also, the fracture stress of the resin part at this temperature is about 1 kgf / mm 2 , so substitute these values into the equation (4), Ah> 0.24At (5) That is, the minimum area of the hole is the tab It is desirable that the area is 24% or more.

また貫通穴が過度に大きくなるとタブの剛性が低下する
ので、チツプ搭載面に凹凸が生じ、チツプとタブとの接
合が困難となる。更にワイヤボンデイングの際に、タブ
の反素子搭載面から加える熱が、チツプに伝わりにくく
なる。従つて貫通穴の大きさに最適には上限があり、本
発明者等の実験確認によれば貫通穴の面積は搭載するチ
ツプの80%以下が望ましい。上記穴の範囲は各貫通穴毎
にもまた貫通穴の合計に対しても適用し得る。
Further, if the through hole is excessively large, the rigidity of the tab is lowered, so that the chip mounting surface becomes uneven, and it becomes difficult to join the chip and the tab. Further, during wire bonding, heat applied from the surface of the tab opposite to the element mounting surface is less likely to be transmitted to the chip. Therefore, there is an upper limit to the optimum size of the through hole, and according to the experiments and confirmation by the present inventors, the area of the through hole is preferably 80% or less of the chip to be mounted. The range of holes described above can be applied to each through hole as well as to the total number of through holes.

次に、本発明による貫通穴の製造方法について述べる。Next, a method of manufacturing a through hole according to the present invention will be described.

第7図に従来のエツチング技術でタブに貫通穴をあける
方法を示す。タブの両側に同一形状のエツチングパター
ン14a,14bを密着し、エツチング液15の中に浸漬する。
エツチングは、タブの両面から進行するので、第8図の
ように、わずかに中央部が狭い穴があく。しかし、従来
の方法では、穴の内側の面積がほとんど一様なので、樹
脂が入り込んでも、これを拘束するには至らない。
FIG. 7 shows a method of forming a through hole in a tab by a conventional etching technique. Etching patterns 14a and 14b having the same shape are closely attached to both sides of the tab and immersed in the etching liquid 15.
Since the etching progresses from both sides of the tab, as shown in FIG. 8, there is a hole with a slightly narrow central portion. However, in the conventional method, since the area inside the hole is almost uniform, even if the resin enters, it cannot be restricted.

第9図に、本発明の第2実施例の貫通穴をあける方法を
示す。タブ上面のエツチングパターン14cの穴は、下面
のエツチングパターン14dの穴より大きい。このような
状態でエツチング液15に浸漬すると、第10図のような穴
があくので、第2実施例をを実現することができる。
FIG. 9 shows a method of forming a through hole according to the second embodiment of the present invention. The holes in the etching pattern 14c on the upper surface of the tab are larger than the holes in the etching pattern 14d on the lower surface. When immersed in the etching liquid 15 in such a state, holes are formed as shown in FIG. 10, so that the second embodiment can be realized.

第11図に、本発明の第3実施例の貫通穴をあける方法を
示す。エツチングパターン14e,14fの穴の大きさは等し
いが、位置がずれている。従つて、第12図のように、タ
ブに対して斜めにあいた穴、すなわち、第3実施例を実
現することができる。
FIG. 11 shows a method of forming a through hole according to the third embodiment of the present invention. The holes of the etching patterns 14e and 14f have the same size, but their positions are deviated. Therefore, as shown in FIG. 12, it is possible to realize a hole that is oblique to the tab, that is, the third embodiment.

第13図に、プレスにより本発明を実現する方法を示す。
まず、従来の技術により、タブに貫通穴をあけ、この部
分に凸形のプレス金型16aをプレスする。この方法によ
り、第14図に示すように、反素子搭載面における穴の内
側の面積よりも大きな面積の部分を設けることができ
る。
FIG. 13 shows a method for realizing the present invention by pressing.
First, according to a conventional technique, a through hole is formed in the tab, and a convex press die 16a is pressed on this portion. By this method, as shown in FIG. 14, a portion having an area larger than the area inside the hole on the anti-element mounting surface can be provided.

次に本発明の第4実施例を第15図及び第16図に基づいて
説明する。タブの貫通孔はテーパにはなつていないが素
子搭載面は反素子搭載面よりも穴径が大きい。また本実
施例では減肉部17が形成されている。更に穴は複数設け
られている。尚符号18はダイボンデイング材である。
Next, a fourth embodiment of the present invention will be described with reference to FIGS. 15 and 16. The through hole of the tab is not tapered, but the element mounting surface has a larger hole diameter than the anti-element mounting surface. Further, in this embodiment, the thinned portion 17 is formed. Further, a plurality of holes are provided. Reference numeral 18 is a die bonding material.

第15図はタブ1に貫通穴2を設け、かつ、タブ1上部に
減肉部17を設けたものである。この構造によれば、ダイ
ボンデイング材18が素子4とタブ1の間を完全に埋めて
いても樹脂部5はタブ上部に充填される。リフロー半田
付けの際にタブ1と樹脂部5が剥離しても、タブ上部に
充填された樹脂部の為、樹脂部5はタブ1から抜け出る
ことはなく、蒸気圧による変形は第16図のようになる。
ここで、タブ残存部の最大幅dを次の式で与えられる値
以下にすれば、樹脂部にクラツクは生じない。
In FIG. 15, the tab 1 is provided with the through hole 2 and the thin portion 17 is provided on the upper portion of the tab 1. According to this structure, even if the die bonding material 18 completely fills the space between the element 4 and the tab 1, the resin portion 5 is filled in the upper portion of the tab. Even if the tab 1 and the resin part 5 are separated during reflow soldering, the resin part 5 does not come out of the tab 1 because the resin part is filled in the upper part of the tab, and the deformation due to the vapor pressure is as shown in FIG. Like
Here, if the maximum width d of the tab remaining portion is set to be equal to or less than the value given by the following equation, cracking does not occur in the resin portion.

ここで、KIC:リフロー温度における樹脂の破壊靭性値 p:リフロー時に発生する蒸気圧 第17図は他の実施例で貫通穴2を上部に広がる形状とし
たものを複数形成したもので、これによつても上記と同
様の効果が出せる。
Here, K IC : Fracture toughness value of resin at reflow temperature p: Vapor pressure generated during reflow FIG. 17 shows a case where a plurality of through holes 2 having a shape expanding to the upper side are formed in another embodiment. According to this, the same effect as described above can be obtained.

最後に、本発明を実施する際の問題点とこれを解決する
方法について述べる。第18図は、本発明のタブ1に素子
を接合するため、接着剤18を塗布した状態を示したもの
である。第19図は、第18図の状態の後に、素子4を搭載
し、接合した状態を示す。図に示すように、接着剤18の
量が過多であると、貫通穴2の側面に接着剤18が流れ出
す恐れがある。第19図の状態で、接着剤が硬化した後に
樹脂部をモールドすると、樹脂部と接着剤との間にはく
離が生じ易く、本発明の効果がなくなる恐れがある。
Finally, a problem in implementing the present invention and a method for solving the problem will be described. FIG. 18 shows a state in which an adhesive 18 is applied to bond the element to the tab 1 of the present invention. FIG. 19 shows a state in which the element 4 is mounted and joined after the state shown in FIG. As shown in the figure, when the amount of the adhesive 18 is excessive, the adhesive 18 may flow out to the side surface of the through hole 2. In the state shown in FIG. 19, if the resin portion is molded after the adhesive has hardened, peeling easily occurs between the resin portion and the adhesive, and the effect of the present invention may be lost.

このような問題点を解決するには、第20図に示すよう
に、タブ1の素子搭載面の貫通穴のまわりに接着剤17の
流出防止溝19を設ければ良い。第21図は、接着剤流出防
止溝19を設けたタブ1に素子4を搭載した状態を示す。
図に示すように、余分な接着剤は、溝18に留められるの
で、貫通穴に流れ出すことはなくなる。
To solve such a problem, as shown in FIG. 20, an outflow preventing groove 19 for the adhesive 17 may be provided around the through hole on the element mounting surface of the tab 1. FIG. 21 shows a state in which the element 4 is mounted on the tab 1 provided with the adhesive outflow prevention groove 19.
As shown, the excess adhesive is retained in the groove 18 so that it will not flow out into the through hole.

〔発明の効果〕〔The invention's effect〕

本発明によれば、タブと樹脂部が剥離したときのタブ下
方の樹脂部を拘束する距離が短くなるので、水蒸気の圧
力による樹脂部の応力が低減し、リフロークラツクを防
止することができる。
According to the present invention, when the tab and the resin portion are separated, the distance for restraining the resin portion under the tab is shortened, so that the stress of the resin portion due to the pressure of water vapor is reduced and reflow cracking can be prevented. .

【図面の簡単な説明】[Brief description of drawings]

第1図は夫々本発明の一実施例に係るリードフレームの
一部分を示す斜視図、第2図は第1図の実施例を適用し
た半導体装置の一実施例の断面図、第3図及び第4図は
夫々本発明の他の実施例に係るリードフレームの部分断
面図、第5図はリードフレームの応力計算に用いる計算
モデルの斜視図、第6図は従来例に係る半導体装置の断
面図、第7図及び第8図は夫々従来例に係るリードフレ
ームの貫通穴形成工程を示すリードフレームの部分断面
図、第9図,第10図,第11図,第12図,第14図,第18
図,第20図は夫々本発明の実施例に係るリードフレーム
の貫通穴形成工程を示すリードフレームの部分断面図、
第13図は同じく貫通穴形成工程を示すリードフレーム及
びプレス金型の部分断面図、第15図,第16図,第17図は
夫々本発明の他の実施例に係る半導体装置の断面図、第
19図は第18図の実施例に係るリードフレームに素子を搭
載した状態の断面図、第21図は第20図の実施例に係るリ
ードフレームに素子を搭載した状態の断面図である。 1……タブ、2……貫通穴、3……タブ吊リード、4…
…素子、5……樹脂部、6……水蒸気、7……リード、
8……半田、9……基板、18……ダイボンデイング材、
19……接着剤流出防止溝。
1 is a perspective view showing a part of a lead frame according to an embodiment of the present invention, and FIG. 2 is a sectional view of an embodiment of a semiconductor device to which the embodiment of FIG. 1 is applied, FIG. 3 and FIG. 4 is a partial sectional view of a lead frame according to another embodiment of the present invention, FIG. 5 is a perspective view of a calculation model used for stress calculation of the lead frame, and FIG. 6 is a sectional view of a semiconductor device according to a conventional example. , FIG. 7 and FIG. 8 are partial cross-sectional views of the lead frame showing the through-hole forming process of the lead frame according to the conventional example, respectively, FIG. 9, FIG. 10, FIG. 10, FIG. 11, FIG. 18th
FIG. 20 is a partial cross-sectional view of the lead frame showing a through-hole forming process of the lead frame according to the embodiment of the present invention,
FIG. 13 is a partial cross-sectional view of a lead frame and a press die showing the through-hole forming process, FIG. 15, FIG. 16, and FIG. 17 are cross-sectional views of a semiconductor device according to another embodiment of the present invention, respectively. First
FIG. 19 is a sectional view showing a state where an element is mounted on the lead frame according to the embodiment of FIG. 18, and FIG. 21 is a sectional view showing a state where an element is mounted on the lead frame according to the embodiment of FIG. 1 ... tab, 2 ... through hole, 3 ... tab suspension lead, 4 ...
… Element, 5 …… resin part, 6 …… water vapor, 7 …… lead,
8 ... Solder, 9 ... Board, 18 ... Die bonding material,
19 …… Adhesive outflow prevention groove.

───────────────────────────────────────────────────── フロントページの続き (72)発明者 三浦 英生 茨城県土浦市神立町502番地 株式会社日 立製作所機械研究所内 (72)発明者 立道 昭弘 茨城県土浦市神立町502番地 株式会社日 立製作所機械研究所内 (72)発明者 北林 千加子 茨城県土浦市神立町502番地 株式会社日 立製作所機械研究所内 (72)発明者 清水 一男 群馬県高崎市西横手町111番地 株式会社 日立製作所高崎工場内 (72)発明者 初田 俊雄 茨城県土浦市神立町502番地 株式会社日 立製作所機械研究所内 (72)発明者 尾崎 敏範 茨城県土浦市神立町502番地 株式会社日 立製作所機械研究所内 (72)発明者 服部 敏雄 茨城県土浦市神立町502番地 株式会社日 立製作所機械研究所内 (72)発明者 坂田 荘司 茨城県土浦市神立町502番地 株式会社日 立製作所機械研究所内 (56)参考文献 特開 昭53−32672(JP,A) 特開 昭59−177953(JP,A) 特開 昭52−53665(JP,A) 特開 昭62−15845(JP,A) 実開 昭60−11825(JP,U) ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hideo Miura 502 Jinritsu-cho, Tsuchiura-shi, Ibaraki Hiritsu Manufacturing Co., Ltd.Mechanical Research Institute (72) Inventor Akihiro Tachimichi 502 Jinritsu-cho, Tsuchiura-shi, Ibaraki Hiritsu Manufacturing Co., Ltd. Mechanical Research Laboratory (72) Inventor Chikako Kitabayashi 502 Kintatecho, Tsuchiura City, Ibaraki Prefecture Hiritsu Manufacturing Co., Ltd.Mechanical Research Laboratory (72) Inventor Kazuo Shimizu 111 Nishiyokotemachi, Takasaki City, Gunma Hitachi Takasaki Plant ( 72) Inventor Toshio Hatta, 502 Jintamachi, Tsuchiura-shi, Ibaraki Machinery Research Laboratory, Hiritsu Manufacturing Co., Ltd. (72) Toshinori Ozaki, 502, Jinmachi-cho, Tsuchiura City, Ibaraki Machinery Research Institute, Hiritsu Manufacturing Co., Ltd. (72) Invention Toshio Hattori 502 Jinrachi-cho, Tsuchiura-shi, Ibaraki Machinery Research Laboratory, Hiritsu Manufacturing Co., Ltd. (72) Inventor Sakata Shoji, 502, Jinritsu-cho, Tsuchiura-shi, Ibaraki Machinery Research Laboratory, Hiritsu Manufacturing Co., Ltd. (56) References JP-A-53-32672 (JP, A) JP-A-59-177953 (JP, A) JP-A-52-53665 (JP, A) JP 62-15845 (JP, A) Actually developed 60-11825 (JP, U)

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】半導体素子を搭載するタブと、該タブの周
辺にてタブ吊りリードにより該タブと一体に接続したリ
ード群とからなり、1個または複数個の貫通穴を備えた
リードフレームにおいて、前記タブ全面の内、少なくと
も前記半導体素子が搭載される部位直下に前記タブの長
手方向に伸びる略長円のスリット状貫通穴を形成し、か
つスリット状貫通穴は素子搭載面側から反素子搭載面側
の方向への封止樹脂の抜け出るのを防止するように、貫
通穴の素子搭載面側開口面と、反素子搭載面側開口面
と、板厚内の貫通穴で前記各開口面と平行な任意の面と
の3つの内、いずれかが他の面と異なる面積となるよう
に形成しており、しかも少なくとも一本の前記スリット
状貫通穴の長手方向と前記タブの長辺に平行な中心線の
方向とが一致しており、かつこのスリット状貫通穴は前
記中心線上に位置することを特徴とするリードフレー
ム。
1. A lead frame comprising a tab on which a semiconductor element is mounted and a lead group integrally connected to the tab by tab suspension leads around the tab, the lead frame having one or more through holes. In the entire surface of the tab, at least immediately below the portion where the semiconductor element is mounted, a substantially elliptic slit-shaped through hole extending in the longitudinal direction of the tab is formed, and the slit-shaped through hole is an anti-element from the element mounting surface side. In order to prevent the sealing resin from slipping out in the direction of the mounting surface, the element mounting surface side opening surface of the through hole, the counter element mounting surface side opening surface, and the through holes in the plate thickness And any of the parallel surfaces are formed so that one of them has an area different from that of the other surface, and moreover, in the longitudinal direction of at least one slit-shaped through hole and the long side of the tab. If the directions of the parallel center lines match And the lead frame the slit-shaped through-hole, characterized in that located on the center line.
【請求項2】半導体素子と、該半導体素子を搭載しかつ
1個または複数個の貫通穴付きのタブと、該タブの周辺
に配置されるリード群と、該リード群の内のインナーリ
ード部及びタブ並びに前記半導体素子を封止する樹脂部
とを備えた半導体装置において、前記タブ全面の内、少
なくとも前記半導体素子が搭載される部位直下に前記タ
ブの長手方向に伸びる略長円のスリット状貫通穴を形成
し、かつスリット状貫通穴は素子搭載面側から反素子搭
載面側の方向への封止樹脂の抜け出るのを防止するよう
に、貫通穴の素子搭載面側開口面と、反素子搭載面側開
口面と、板厚内の貫通穴で前記各開口面と平行な任意の
面との3つの内、いずれかが他の面と異なる面積となる
ように形成しており、しかも少なくとも一本の前記スリ
ット状貫通穴の長手方向と前記タブの長辺に平行な中心
線の方向とが一致しており、かつこのスリット状貫通穴
は前記中心線上に位置することを特徴とする半導体装
置。
2. A semiconductor element, a tab on which the semiconductor element is mounted and having one or more through holes, a lead group arranged around the tab, and an inner lead portion in the lead group. And a tab and a resin portion that seals the semiconductor element, in a slit-shaped substantially oval shape extending in the longitudinal direction of the tab at least immediately below a portion where the semiconductor element is mounted, in the entire tab surface. The through hole is formed, and the slit-shaped through hole prevents the sealing resin from escaping from the element mounting surface side in the direction opposite to the element mounting surface side. The element mounting surface side opening surface and any of the through holes in the plate thickness, which are parallel to the opening surfaces, are formed so that one of them has a different area from the other surface. Length of at least one slit-shaped through hole The semiconductor device direction coincides and the direction of the center line parallel to the long sides of the tub, and the slit-shaped through-hole, characterized in that located on the center line.
【請求項3】前記リード群の内のアウターリード部の折
り曲げ面において基板に半田付けする面付け実装タイプ
であることを特徴とする特許請求の範囲第2項記載の半
導体装置。
3. The semiconductor device according to claim 2, wherein the semiconductor device is of an imposition mounting type in which a bent surface of an outer lead portion of the lead group is soldered to a substrate.
JP62056590A 1987-02-25 1987-03-13 Lead frame and semiconductor device Expired - Lifetime JPH0680760B2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP62056590A JPH0680760B2 (en) 1987-03-13 1987-03-13 Lead frame and semiconductor device
US07/158,673 US4942452A (en) 1987-02-25 1988-02-22 Lead frame and semiconductor device
US08/448,881 USRE37690E1 (en) 1987-02-25 1995-05-24 Lead frame and semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62056590A JPH0680760B2 (en) 1987-03-13 1987-03-13 Lead frame and semiconductor device

Publications (2)

Publication Number Publication Date
JPS63224245A JPS63224245A (en) 1988-09-19
JPH0680760B2 true JPH0680760B2 (en) 1994-10-12

Family

ID=13031403

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62056590A Expired - Lifetime JPH0680760B2 (en) 1987-02-25 1987-03-13 Lead frame and semiconductor device

Country Status (1)

Country Link
JP (1) JPH0680760B2 (en)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2749124B2 (en) * 1989-06-03 1998-05-13 新光電気工業株式会社 Lead frame
JPH03178153A (en) * 1989-12-07 1991-08-02 Matsushita Electron Corp Semiconductor device
JPH0575006A (en) * 1991-09-18 1993-03-26 Fujitsu Ltd Lead frame and resin sealed semiconductor device
JPH0722550U (en) * 1993-09-22 1995-04-21 サンケン電気株式会社 Semiconductor device
DE19506958C2 (en) * 1995-02-28 1998-09-24 Siemens Ag Semiconductor device with good thermal behavior
US6242802B1 (en) * 1995-07-17 2001-06-05 Motorola, Inc. Moisture enhanced ball grid array package
JP2002058841A (en) * 2000-08-22 2002-02-26 Heiwa Corp Synthetic resin unit for game machine and crack occurrence preventing method for synthetic resin unit
JP5202062B2 (en) * 2008-03-25 2013-06-05 新電元工業株式会社 Semiconductor device

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5253665A (en) * 1975-10-29 1977-04-30 Hitachi Ltd Semiconductor device
JPS5332672A (en) * 1976-09-07 1978-03-28 Matsushita Electronics Corp Lead frame for semiconductor device
JPS59177953A (en) * 1983-03-28 1984-10-08 Toshiba Corp Semiconductor device
JPS6011825U (en) * 1983-07-06 1985-01-26 富士重工業株式会社 Vehicle roof opening structure
JPS60118252U (en) * 1984-01-18 1985-08-09 沖電気工業株式会社 Lead frame for resin-sealed semiconductor devices
JPS6215845A (en) * 1985-07-12 1987-01-24 Shinko Electric Ind Co Ltd Manufacture of lead frame

Also Published As

Publication number Publication date
JPS63224245A (en) 1988-09-19

Similar Documents

Publication Publication Date Title
US6913948B2 (en) Partially captured oriented interconnections for BGA packages and a method of forming the interconnections
JP2009507394A (en) Semiconductor package die pad
US20010015012A1 (en) Structure of conductive bump in wiring board
JPH0680760B2 (en) Lead frame and semiconductor device
KR20000071421A (en) Semiconductor apparatus and semiconductor apparatus manufacturing method
EP0459831A2 (en) Method and device for mounting components on a printed circuit board
JP2924840B2 (en) Tape-BGA type semiconductor device
US4754912A (en) Controlled collapse thermocompression gang bonding
JPS63239967A (en) Resin sealed semiconductor device and manufacture thereof
US6527163B1 (en) Methods of making bondable contacts and a tool for making such contacts
USRE37690E1 (en) Lead frame and semiconductor device
JPH07161896A (en) Lead frame and manufacture of it
JP2546472B2 (en) Semiconductor device
JP2570209B2 (en) Semiconductor device
EP0146330A2 (en) Integrated circuit device with textured bar pad
JP3633364B2 (en) Manufacturing method of BGA type semiconductor device
JPH10270618A (en) Lead frame, manufacture thereof and semiconductor device
JP2000031371A (en) Lead frame and semiconductor device comprising the same
KR0125197Y1 (en) A semiconductor equipment
JPH06224353A (en) Electrode structure of electronic component
JP3294738B2 (en) Lead pin mounting structure
JP2998179B2 (en) Method for manufacturing film carrier type semiconductor device
JP2504187B2 (en) Lead frame
KR100246352B1 (en) Structure for bonding wire of semiconductor
JP3395654B2 (en) Bonding tools

Legal Events

Date Code Title Description
EXPY Cancellation because of completion of term