KR0125197Y1 - A semiconductor equipment - Google Patents
A semiconductor equipment Download PDFInfo
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- KR0125197Y1 KR0125197Y1 KR2019950015768U KR19950015768U KR0125197Y1 KR 0125197 Y1 KR0125197 Y1 KR 0125197Y1 KR 2019950015768 U KR2019950015768 U KR 2019950015768U KR 19950015768 U KR19950015768 U KR 19950015768U KR 0125197 Y1 KR0125197 Y1 KR 0125197Y1
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- substrate
- epoxy resin
- solder
- semiconductor device
- warpage
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
본 고안은 반도체 장치에 관한 것으로서, 기판의 휨(warpage)정도를 줄이기 위해 기판에 금속패턴의 외부쪽에 다수의 홀을 형성하여 고온의 에폭시 몰딩시 열팽창에 의한 기판의 휨을 줄일 수 있는 반도체 장치를 개시된다. 기판에 다수의 홀을 형성하므로써 기판의 신장량이 줄어들어 기판의 휨 정도가 줄어들며, 기판 저면에 형성된 볼의 평면성을 유지하여 또다른 기판에 대한 안정적인 실장이 가능해진다. 또한 각 홀 내부에 에폭시 수지가 채워져 에폭시 수지와 기판과의 점착강도가 강화되는 부수적인 효과를 얻을 수 있다.The present invention relates to a semiconductor device, which discloses a semiconductor device capable of reducing the warpage of a substrate due to thermal expansion during high temperature epoxy molding by forming a plurality of holes on the outside of the metal pattern in the substrate to reduce the warpage of the substrate. do. By forming a plurality of holes in the substrate, the amount of elongation of the substrate decreases, thereby reducing the degree of warpage of the substrate, and maintaining the planarity of the balls formed on the bottom of the substrate, thereby enabling stable mounting on another substrate. In addition, the epoxy resin is filled in each hole to obtain a side effect of strengthening the adhesive strength between the epoxy resin and the substrate.
Description
제1도는 종래의 프라스틱 볼 그리드 어레이의 몰딩공정시 발생하는 프라스틱의 휨상태를 도시한 정면도.1 is a front view showing the bending state of the plastic generated during the molding process of a conventional plastic ball grid array.
제2a도는 본 고안에 따른 반도체 장치의 평면도.2a is a plan view of a semiconductor device according to the present invention.
제2b도는 제2a도의 A-A'선을 따라 절취한 상태의 단면도.FIG. 2B is a cross-sectional view taken along the line AA ′ of FIG. 2A.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
11 : 기판 12 : 금속 패턴11: substrate 12: metal pattern
13 : 홀 14 : 땜납 방식제13 hole 14 solder anticorrosive
15,16 : 에폭시 수지 17 : 칩15,16: epoxy resin 17: chip
18 : 와이어 19 : 납땜 볼18: wire 19: soldering ball
본 고안은 반도체 장치에 관한 것으로, 특히 몰딩과정에서 발생하는 기판의 휨 정도를 줄일 수 있도록 구성한 반도체 장치에 관한 것이다.The present invention relates to a semiconductor device, and more particularly to a semiconductor device configured to reduce the degree of warpage of the substrate generated in the molding process.
일반적으로 프라스틱 볼 그리드 어레이(plastic ball grid array)의 몰딩(encapsulation)공정시 발생되는 문제점은 몰딩재료인 에폭시 수지와 기판의 재료인 프라스틱의 열팽창 계수의 차이로 인한 프라스틱 기판의 휨(warpage)의 발생이다. 이 휨의 발생원인과 이로인한 문제점을 제1도를 통하여 상세히 설명하면 다음과 같다.In general, a problem that occurs during the encapsulation process of a plastic ball grid array is a warpage of a plastic substrate due to a difference in the coefficient of thermal expansion of an epoxy resin as a molding material and a plastic as a substrate material. to be. The cause of the warpage and the problems caused by this will be described in detail with reference to FIG. 1 as follows.
제1도는 종래의 프라스틱 볼 그리드 어레이의 몰딩공정시 발생하는 프라스틱 기판의 휨상태를 도시한 정면도로서, 칩(도시되지 않음)과 기판의 패턴을 와이어 본딩(wire bonding)을 통하여 연결한후 칩 상부에 에폭시 수지(Epoxy Resin; 2)를 몰딩한 상태를 도시하고 있다.FIG. 1 is a front view illustrating a bending state of a plastic substrate generated in a molding process of a conventional plastic ball grid array. The top of the chip after connecting a chip (not shown) and a pattern of the substrate through wire bonding. The state where the epoxy resin (2) was molded in is shown.
겔(gel) 상태의 몰딩된 에폭시 수지(2)는 고온으로서, 에폭시 수지(2)의 온도 및 에폭시 수지(2)와 기판(1)의 열팽창 계수의 차이에 의하여 기판(1)은 제1도에 도시된 바와같이 중앙부를 향하여 오목한 상태로 휘어지게 된다. 한편, 기판(1)의 저면에는 또다른 외부 기판 표면에 형성된 패턴과 접속하기 위한 납땜 볼(solder ball)이 형성되어 있으며, 상술한 기판(1)의 휨 현상은 기판(1) 저면에 형성된 납땜 볼의 기능에 심각한 장애를 초래하게 된다. 즉, 제1도에 도시된 바와같이 기판(1)의 휨 현상으로 인하여 그 저면에 형성된 납땜 볼(3)은 수평면상에 위치하지 않게되며, 따라서 납땜 볼(3)과 또다른 기판 표면의 패턴의 접속은 이루어지지 않게 된다.The molded epoxy resin (2) in a gel state is a high temperature, and the substrate (1) is shown in FIG. 1 due to the difference in the temperature of the epoxy resin (2) and the coefficient of thermal expansion of the epoxy resin (2) and the substrate (1). As shown in FIG. 3, the curved portion is bent in a concave state toward the center portion. On the other hand, a solder ball for connecting with a pattern formed on the surface of another outer substrate is formed on the bottom of the substrate 1, the above-described warpage phenomenon of the substrate 1 is a solder formed on the bottom of the substrate 1 It will cause serious impairment of ball function. That is, as shown in FIG. 1, due to the warpage of the substrate 1, the solder ball 3 formed on the bottom thereof is not located on the horizontal plane, and thus the pattern of the solder ball 3 and another substrate surface Is not connected.
본 고안은 기판에 고온의 에폭시 수지를 몰딩하는 과정에서 발생하는 상술한 문제점을 해결하기 위한 것으로서, 에폭시 수지의 몰딩시 기판의 휨 정도를 줄일 수 있는 반도체 장치를 제공하는데 그 목적이 있다.The object of the present invention is to solve the above-described problems caused by molding a high temperature epoxy resin on a substrate, and to provide a semiconductor device capable of reducing the degree of warpage of the substrate when molding the epoxy resin.
상술한 목적을 달성하기 위한 본 고안은 기본부재인 땜납 방식제상에 구리박막의 금속패턴, 절연체인 에폭시 수지, 구리박막으로 된 금속패턴 및 땜납 방식제가 순차적으로 증착되며, 상기 땜납 방식제 하부에는 외부 기판의 표면에 형성된 패턴과 접속되는 다수의 납땜 볼이 형성된 기판으로 이루어진 반도체 소자에 있어서, 상기 기판의 가장자리부에는 상기 각 부재를 관통하는 다수의 홀을 형성하여 고온의 에폭시 수지의 몰딩시 열팽창으로 인한 기판의 신장을 방지하고 에폭시 수지와의 점착력을 강화시킬 수 있도록 구성한 것을 특징으로 한다.The present invention for achieving the above object is sequentially deposited a metal pattern of a copper thin film, an epoxy resin as an insulator, a metal pattern made of a copper thin film and a solder anticorrosive on a solder anticorrosive, which is a basic member, and an external portion under the solder anticorrosive A semiconductor device comprising a substrate having a plurality of solder balls connected to a pattern formed on a surface of the substrate, wherein a plurality of holes penetrate each member at the edges of the substrate to form thermal expansion during molding of a high temperature epoxy resin. It is characterized in that it is configured to prevent the elongation of the substrate and to enhance the adhesive strength with the epoxy resin.
이하, 본 고안을 첨부한 도면을 참고하여 상세히 설명한다.Hereinafter, with reference to the accompanying drawings of the present invention will be described in detail.
본 고안에서는 에폭시 수지보다 큰 기판의 열팽창 계수로 인하여 기판의 신장 및 수축 양이 에폭시 수지보다 크다는 원리를 착안한 것으로서, 물체에 열을 가함으로서 신장되는 양과 그 물체의 형상과의 상관관계는The present invention is based on the principle that the amount of elongation and shrinkage of the substrate is larger than that of the epoxy resin due to the coefficient of thermal expansion of the substrate larger than the epoxy resin, the correlation between the amount of elongation by applying heat to the object and the shape of the object
λα 1/ A ---(식1)으로 표현된다.It is represented by λα 1 / A --- (Equation 1).
여기서, λ : 늘어나는 양Where λ: increasing amount
1 : 물체의 길이1: length of object
A : 물체의 면적A: area of the object
그러므로 상기 식 1을 응용하기 위해 제2a도에 도시된 바와같이 기판(11)의 면적(A)을 줄이고, 길이(1)를 줄이기 위해 금속패턴(12)이 형성된 기판(11)에 원형 또는 각형의 홀(13)을 일정간격으로 형성하므로서 가능해진다. 즉, 홀(13)에 의해 기판(11)의 면적이 줄어들고 길이가 줄어드는 효과가 생겨 홀(13)이 형성되지 않았을 때보다 늘어나는 양(λ)의 값이 작게 된다. 또한 몰딩을 하였을 때 상기 홀(13)에도 절연체인 에폭시 수지가 채워짐으로서 기판(11)에 대한 에폭시 수지의 점착강도가 강해진다.Therefore, in order to apply the above equation 1, as shown in FIG. 2A, the area A of the substrate 11 is reduced, and the circular or square shape is formed on the substrate 11 on which the metal pattern 12 is formed to reduce the length 1. This is possible by forming the holes 13 at regular intervals. That is, the area of the substrate 11 is reduced and the length is reduced by the hole 13, so that the value of the amount λ that is increased becomes smaller than when the hole 13 is not formed. In addition, when molding, the hole 13 is filled with an epoxy resin as an insulator, thereby increasing the adhesion strength of the epoxy resin to the substrate 11.
제2b도는 제2a도의 A-A'선을 따라 절단한 상태의 단면도로서, 제2도에 도시된 기판(11)에 칩을 부착한후 와이어 본딩 및 몰딩 공정을 실시한 상태의 단면을 도시한다.FIG. 2B is a cross-sectional view taken along the line A-A 'of FIG. 2A, and shows a cross section in which a wire bonding and molding process is performed after a chip is attached to the substrate 11 shown in FIG.
기본부재인 땜납 방식제(14)상에는 구리박막의 금속패턴(12A), 절연체인 에폭시 수지(15), 구리박막으로 된 금속패턴(12) 및 땜납 방식제(14A)가 순차적으로 증착되며, 금속패턴(12)의 중앙부는 제거되어 에폭시 수지(15)의 중앙부는 외부로 노출된다. 또한 최상부의 땜납 방식제(14A) 역시 그 중앙부가 제거됨으로서 금속패턴(12)의 내측가장자리부가 일정 폭으로 노출된다. 한편, 기판(11)의 가장자리부에는 다수의 홀(13)이 형성한 되며, 각 홀(13)은 상기 각 부재를 관통한 상태이다.On the solder anticorrosive 14 as a basic member, a metal pattern 12A of a copper thin film, an epoxy resin 15 as an insulator, a metal pattern 12 made of a copper thin film, and a solder anticorrosive 14A are sequentially deposited. The center portion of the pattern 12 is removed so that the center portion of the epoxy resin 15 is exposed to the outside. In addition, the uppermost solder anticorrosive 14A is also removed from the center thereof so that the inner edge of the metal pattern 12 is exposed to a predetermined width. On the other hand, a plurality of holes 13 are formed in the edge portion of the substrate 11, each hole 13 is in a state penetrating the respective members.
노출된 에폭시 수지(15)의 중앙부에는 접착제를 이용하여 칩(17)을 부착시키며, 칩(17)과 노출된 패턴(12)을 와이어(18)로서 연결한다. 와이어(18)의 연결후 각 홀(13)을 포함하는 상태로 기판(11)의 상부에 에폭시 수지(16)를 몰딩하여 패캐이지화 한후, 기판(11)의 저면에 형성된 납땜 볼(19)을 또다른 기판의 패턴에 솔더링 함으로써 모든 조립공정은 완료된다.The chip 17 is attached to the center of the exposed epoxy resin 15 using an adhesive, and the chip 17 and the exposed pattern 12 are connected as the wire 18. After the connection of the wires 18, the epoxy resin 16 is molded and packaged on the upper part of the substrate 11 in a state including each hole 13, and then the solder ball 19 formed on the bottom surface of the substrate 11 is removed. All assembly processes are completed by soldering to another substrate pattern.
상술한 바와같은 본 고안에 의하면 기판의 금속패턴 외측에 일정한 간격으로 다수의 홀(hole)을 형성하므로써, 기판의 면적이 줄어들게 되며 고온의 에폭시 수지 몰딩시 열팽창에 의한 신장량이 줄어들어 기판 저면에 형성된 납땜 볼(Ball)의 평면성이 유지된다. 따라서 납땜 볼을 이용한 또다른 기판과의 접속이 원활해져 안정적인 실장이 가능해지며, 또한 각 홀 내부에 에폭시 수지가 충진되어 에폭시 수지와 기판과의 점착강도가 강화되어 제품의 신뢰성을 향상시킬 수 있는 우수한 효과를 기대할 수 있다.According to the present invention as described above, by forming a plurality of holes at regular intervals on the outside of the metal pattern of the substrate, the area of the substrate is reduced and the amount of elongation due to thermal expansion during the molding of a high temperature epoxy resin is reduced, the solder formed on the bottom of the substrate The planarity of the ball is maintained. Therefore, it is possible to connect with another board using solder balls, so that stable mounting is possible. Also, the epoxy resin is filled in each hole, and the adhesive strength between the epoxy resin and the board is strengthened to improve the reliability of the product. You can expect.
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Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019950015768U KR0125197Y1 (en) | 1995-06-30 | 1995-06-30 | A semiconductor equipment |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019950015768U KR0125197Y1 (en) | 1995-06-30 | 1995-06-30 | A semiconductor equipment |
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| Publication Number | Publication Date |
|---|---|
| KR970003228U KR970003228U (en) | 1997-01-24 |
| KR0125197Y1 true KR0125197Y1 (en) | 1999-02-18 |
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| KR2019950015768U KR0125197Y1 (en) | 1995-06-30 | 1995-06-30 | A semiconductor equipment |
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| KR100524480B1 (en) * | 1998-07-29 | 2005-12-30 | 삼성전자주식회사 | Tape Carrier Package |
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1995
- 1995-06-30 KR KR2019950015768U patent/KR0125197Y1/en not_active IP Right Cessation
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| Publication number | Publication date |
|---|---|
| KR970003228U (en) | 1997-01-24 |
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