JPH0432254A - Semiconductor package - Google Patents
Semiconductor packageInfo
- Publication number
- JPH0432254A JPH0432254A JP2138941A JP13894190A JPH0432254A JP H0432254 A JPH0432254 A JP H0432254A JP 2138941 A JP2138941 A JP 2138941A JP 13894190 A JP13894190 A JP 13894190A JP H0432254 A JPH0432254 A JP H0432254A
- Authority
- JP
- Japan
- Prior art keywords
- adhesive
- semiconductor chip
- diffusion plate
- hole
- semiconductor package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 41
- 239000000853 adhesive Substances 0.000 claims abstract description 30
- 230000001070 adhesive effect Effects 0.000 claims abstract description 30
- 239000011347 resin Substances 0.000 claims abstract description 8
- 229920005989 resin Polymers 0.000 claims abstract description 8
- 238000009792 diffusion process Methods 0.000 claims description 21
- 230000000694 effects Effects 0.000 description 6
- 230000035882 stress Effects 0.000 description 5
- 230000017525 heat dissipation Effects 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 239000012790 adhesive layer Substances 0.000 description 3
- 229920002379 silicone rubber Polymers 0.000 description 2
- 239000004945 silicone rubber Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 239000012466 permeate Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 210000002784 stomach Anatomy 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体チップの熱放散に関する技術、特に、発
熱量の大きい大型の半導体装置の放熱を効率良く行わせ
るための技術に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a technology related to heat dissipation of a semiconductor chip, and particularly to a technology for efficiently dissipating heat from a large-sized semiconductor device that generates a large amount of heat.
例えば、半導体装置の1つに、放熱板として機能する熱
拡散板に半導体チップを搭載し、さらに半導体チップを
中心部に露出させた状態で熱拡散板上にピンを立設した
ベースを搭載したパッケージ構造を用いたものがある。For example, one type of semiconductor device has a semiconductor chip mounted on a heat diffusion plate that functions as a heat sink, and a base with pins set up on the heat diffusion plate with the semiconductor chip exposed in the center. Some use a package structure.
ところで、本発明者は、半導体チップと他の部材との間
の接合上の問題について検討した。By the way, the present inventor has studied the problem of bonding between a semiconductor chip and other members.
以下は、本発明者によって検討された技術であり、その
概要は次の通りである。The following are the techniques studied by the present inventor, and the outline thereof is as follows.
すなわち、半導体チップの実装密度が高(なると発熱量
が多くなり、何らかの放熱対策が必要になる。このため
、熱拡散板を用いて半導体チップの放熱を行っているが
、熱拡散板と半導体チップとでは熱膨張係数が異なるた
めに、はんだ接続を行うことばでrきない。In other words, if the packaging density of semiconductor chips is high (the amount of heat generated will increase and some kind of heat dissipation measure will be required).For this reason, a heat diffusion plate is used to dissipate heat from the semiconductor chip, but the heat diffusion plate and the semiconductor chip Since the coefficient of thermal expansion is different between the two, it is not possible to make a solder connection.
そこで、シリコーンゴムなどの柔軟な接着材を用いて接
合を行っている。これにより、熱拡散板と半導体チップ
の熱膨張係数が異なる場合でも、接合部が!MIIiシ
たりするのを防止することができる。Therefore, bonding is performed using a flexible adhesive such as silicone rubber. As a result, even if the thermal expansion coefficients of the thermal diffusion plate and the semiconductor chip are different, the bonding area can be fixed! MIIi can be prevented from occurring.
ところが、前記の如く接着剤を用いて接合を行う半導体
装置のパッケージ構造に右いては、接着剤が軍くなると
熱伝導性が悪くなり、可能な限り薄くする必要があるが
現状では20〜30μmが限界である。However, as mentioned above, in the case of semiconductor device package structures that are bonded using adhesive, the thermal conductivity deteriorates when the adhesive becomes thicker, so it is necessary to make it as thin as possible, but currently the thickness is 20 to 30 μm. is the limit.
接着層を薄くするために荷重をかけることも行われてい
るが、適当な厚みを確保することが難しく、かけ過ぎる
と半導体チップの破損を招くなどの問題のあることが本
発明者によって見い出された。The inventors have discovered that although it has been attempted to apply a load to thin the adhesive layer, it is difficult to ensure an appropriate thickness, and that applying too much load may cause damage to the semiconductor chip. Ta.
そこで、本発明の目的は、接合に接着剤を用いながら十
分な熱伝導性及び応力緩和を達成することのできる技術
を提供することにある。Therefore, an object of the present invention is to provide a technique that can achieve sufficient thermal conductivity and stress relaxation while using an adhesive for bonding.
本発明の前記目的と新規な特徴は、本明細書の記述及び
添付図面から明らかになるであろう。The above objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.
本願において開示される発明のうち、代表的なものの概
要を簡単に説明すれば、以下の通りである。A brief overview of typical inventions disclosed in this application is as follows.
すなわち、熱拡散板に樹脂接着剤を用いて半導体チップ
が接合される半導体パッケージであって、前記半導体チ
ップの接合部に前記樹脂接着剤の逃げ部を前記熱拡散板
に形成するようにしている。That is, in a semiconductor package in which a semiconductor chip is bonded to a heat diffusion plate using a resin adhesive, an escape portion for the resin adhesive is formed in the heat diffusion plate at a joint portion of the semiconductor chip. .
上記した手段によれば、半導体チップとの接合面に塗布
された接着剤は、半導体チップを押圧した際に余分な接
着剤が逃げ部に侵入し、接合面には必要な量だけが残さ
れる。したがって、接合面の接着剤層を極めて薄くする
ことが可能になり、接合部の熱抵抗を小さくできるので
、熱膨張による応力の緩和を達成しながら放熱特性を向
上させることができる。According to the above-mentioned method, when the semiconductor chip is pressed, excess adhesive applied to the surface to be bonded to the semiconductor chip enters the relief part, leaving only the necessary amount on the bonding surface. . Therefore, it is possible to make the adhesive layer on the joint surface extremely thin, and the thermal resistance of the joint can be reduced, so that it is possible to improve heat dissipation characteristics while achieving relaxation of stress caused by thermal expansion.
〔実施例1〕
第1図は本発明による半導体パッケージの一実施例を示
す断面図である。[Embodiment 1] FIG. 1 is a sectional view showing an embodiment of a semiconductor package according to the present invention.
銅などの熱伝導性に優れる金属材料による熱拡散板1の
中央部には台形の凸部1aが形成され、この凸部1aに
一定間隔に複数の貫通孔2が設けられている。この貫通
孔2の孔径は、接着剤が侵入可能でかつ溢れ出ない程度
に設定する。凸部1aには、半導体チップ3が接着材を
用いて固定膜蓋される。さらに、凸部1aを除く熱拡散
板1上にはビスマレイドリアジン(BTレジン)などを
用いたペース4が、同様に接着材を用いて固定設萱され
る。A trapezoidal convex portion 1a is formed in the center of a heat diffusion plate 1 made of a metal material with excellent thermal conductivity such as copper, and a plurality of through holes 2 are provided in this convex portion 1a at regular intervals. The diameter of the through hole 2 is set to a size that allows the adhesive to enter and not overflow. The semiconductor chip 3 is covered with a fixed film on the convex portion 1a using an adhesive. Further, a paste 4 made of bismaleid riazine (BT resin) or the like is similarly fixed on the heat diffusion plate 1 except for the convex portions 1a using an adhesive.
な右、このように凸部1aが設けられているのは、半導
体チップ3の厚みとペース4の厚みとが異なることから
、表面高さを同一にしてワイヤボンディングに支障を及
ぼさないようにするためである。As shown on the right, the reason why the convex portion 1a is provided like this is that the thickness of the semiconductor chip 3 and the thickness of the paste 4 are different, so the surface height is made to be the same so as not to interfere with wire bonding. It's for a reason.
ペース40周辺には複数のリードピン5が立設され、更
にリードピン5に電気的に接続される配線パターンがベ
ース4に形成されており、その端部は半導体チップ3の
近傍に露出している。この配線パターンの端部と半導体
チップ3の電極部とは、ボンディングワイヤ6によって
接続されている。A plurality of lead pins 5 are erected around the pad 40, and a wiring pattern electrically connected to the lead pins 5 is formed on the base 4, the end of which is exposed near the semiconductor chip 3. The ends of this wiring pattern and the electrode portions of the semiconductor chip 3 are connected by bonding wires 6.
次に、以上の構成による実施例の組み立て工程について
説明す。Next, the assembly process of the embodiment with the above configuration will be explained.
まず、予めリードピン5を立設したベース4を熱拡散板
1に接合し、ついで熱拡散板1の凸部la上に適当量の
接着剤7 (シリコーンゴム、銀ペーストなど)を塗布
する。こののち、凸部la上に半導体チップ3を搭載し
、半導体チップ3に適度の荷重を付与しながら乾燥させ
る。この抑圧により、塗布した接着剤7の内の余剰分が
貫通孔2に流れ込み、必要量のみが接合面に残される。First, the base 4 on which the lead pins 5 have been set up in advance is joined to the heat diffusion plate 1, and then an appropriate amount of adhesive 7 (silicone rubber, silver paste, etc.) is applied onto the convex portions la of the heat diffusion plate 1. Thereafter, the semiconductor chip 3 is mounted on the convex portion la, and is dried while applying an appropriate load to the semiconductor chip 3. Due to this suppression, the excess of the applied adhesive 7 flows into the through hole 2, leaving only the necessary amount on the bonding surface.
したがって、接合面の接着剤7の厚みを、例えば10μ
m程度にまで薄くすることができる。Therefore, the thickness of the adhesive 7 on the joint surface should be set to 10 μm, for example.
It can be made as thin as about m.
このとき、貫通孔2は、予め接着剤7がこぼれ落ちない
ような径に設定されているので、貫通孔2の途中で止ま
り、熱拡散板lの底面に出ることはない。なお、貫通孔
2は径を調整するほか、予め熱拡散板1の裏面に当て板
をしておくなどの対策をしても同様な効果が得られる。At this time, the diameter of the through-hole 2 is set in advance to prevent the adhesive 7 from spilling out, so it stops midway through the through-hole 2 and does not come out on the bottom surface of the heat diffusion plate l. In addition to adjusting the diameter of the through holes 2, the same effect can be obtained by taking measures such as placing a patch plate on the back surface of the heat diffusion plate 1 in advance.
また、貫通孔2の上端には面取り加工を施し、余剰接着
剤7が流入し易いようにすれば、更に効果を上げること
ができる。Moreover, the effect can be further improved by chamfering the upper end of the through hole 2 so that the excess adhesive 7 can easily flow in.
以上により、たとえパッケージに変形や熱応力が生じた
としても、これを接着剤7が吸収するため、半導体チッ
プ3に無理な力が加わることはない。As described above, even if deformation or thermal stress occurs in the package, the adhesive 7 absorbs this, so that no unreasonable force is applied to the semiconductor chip 3.
〔実施例2〕
第2図は本発明の第2実施例の主要部を示す斜視図であ
る。[Embodiment 2] FIG. 2 is a perspective view showing the main parts of a second embodiment of the present invention.
本実施例は、前記実施例が凸部1aに貫通孔2を設けて
接着剤7の逃げ部を形成していたのに対し、凸部1aの
中心から放射状に溝8を形成したところに特徴がある。This embodiment is characterized in that grooves 8 are formed radially from the center of the protrusion 1a, whereas in the previous embodiment, the through hole 2 was provided in the protrusion 1a to form an escape part for the adhesive 7. There is.
この構成により、接合時に接着剤7の余剰分が溝8内を
水平方向(凸部1aの幅方向)へ浸透し、接合面に溜ま
ることがなく、接合面の接着剤7を前記実施例と同様に
薄くすることができる。With this configuration, the surplus of the adhesive 7 permeates into the groove 8 in the horizontal direction (width direction of the convex portion 1a) during bonding, and does not accumulate on the bonding surface. It can be made thin as well.
〔実施例3〕
第3図は本発明の第3実施例の主要部を示す斜視図であ
る。[Embodiment 3] FIG. 3 is a perspective view showing the main parts of a third embodiment of the present invention.
本実施例は、第2図の実施例が熱拡散板1」−に台形の
凸部1aを形成していたのに対し、円柱状の小径の突起
9を複数個整列配置したものである。In contrast to the embodiment shown in FIG. 2 in which trapezoidal projections 1a are formed on the heat diffusion plate 1'', this embodiment has a plurality of cylindrical small-diameter projections 9 arranged in a row.
突起9を形成するに際しては、型プレスを用い、或いは
個々に製作した円柱体を熱拡散板1上に密着状態に配設
して接合〈はんだ接合或いは溶着)することにより作ら
れる。この場合、円柱体は密接させず、胴体間に隙間が
形成されるようにし、接合時に接着剤70余剰分が流れ
込みやすいようにする。なお、円柱体の例を示したが、
これに限定されるものではなく、例えば、六角柱などと
してもよい。The protrusions 9 are formed using a mold press or by placing individually manufactured cylindrical bodies on the heat diffusion plate 1 in close contact and joining them (soldering or welding). In this case, the cylindrical bodies are not brought into close contact with each other, but a gap is formed between the bodies so that the excess adhesive 70 can easily flow in during joining. Although we have shown an example of a cylindrical body,
It is not limited to this, but may be a hexagonal prism, for example.
この実施例による作用効果は、第2図の実施例と同一で
あるので、重複する説明は省略する。The effects of this embodiment are the same as those of the embodiment shown in FIG. 2, so redundant explanation will be omitted.
以上、本発明者によってなされた発明を実施例に基づき
具体的に説明したが、本発明は前記実施例に限定される
ものではなく、その要旨を逸脱しない範囲で種々変更可
能であることは言うまでもない。Above, the invention made by the present inventor has been specifically explained based on Examples, but it goes without saying that the present invention is not limited to the Examples and can be modified in various ways without departing from the gist thereof. stomach.
例えば、第2図の実施例では、凸部1aに溝8を放射状
に設けるものとしたが、第4図に示すような基盤の目状
にしてもよいし、第5図に示すように縦または横方向に
一定間隔に複数溝を設ける形状であってもよい。For example, in the embodiment shown in FIG. 2, the grooves 8 are provided radially in the convex portion 1a, but they may be provided in the shape of a base plate as shown in FIG. 4, or vertically as shown in FIG. Alternatively, it may have a shape in which a plurality of grooves are provided at regular intervals in the lateral direction.
また、第1図の実施例においては、貫通孔2を垂直に設
けるものとしたが、第6図に示すように、接合面から板
厚方向に放射状に貫通孔2を形成することにより、横方
向の熱膨張差に起因する応力を緩和させることができる
。In addition, in the embodiment shown in FIG. 1, the through holes 2 are provided vertically, but as shown in FIG. Stress caused by directional thermal expansion differences can be alleviated.
さらに、接合部の逃げ部は、場所にかかわらず均一に形
成するものとしたが、接合部の周辺を中心に比べて多く
なるように貫通孔2(或いは溝)を設けることにより、
大型の半導体チップで生じやすい周辺の大きな応力を緩
和させることができる。Furthermore, although it was assumed that the relief part of the joint part is formed uniformly regardless of the location, by providing the through holes 2 (or grooves) so that the number of relief parts is larger around the joint part than in the center,
It is possible to alleviate the large stress around the periphery that tends to occur with large semiconductor chips.
本願において開示される発明のうち、代表的なものによ
って得られる効果を簡単に説明すれば、下記の通りであ
る。Among the inventions disclosed in this application, the effects obtained by typical ones are as follows.
すなわち、熱拡散板に樹脂接着剤を用いて半導体チップ
が接合される半導体パッケージであって、前記半導体チ
ップの接合部に前記樹脂接着剤の逃げ部を熱拡散板に形
成するようにしたので、接合面の接着剤層を極めて薄く
することができる結果、接合部の熱抵抗を小さくでき、
熱膨張による応力の緩和を達成しながら放熱特性を向上
させることができる。That is, in a semiconductor package in which a semiconductor chip is bonded to a heat diffusion plate using a resin adhesive, an escape portion for the resin adhesive is formed in the heat diffusion plate at the bonding portion of the semiconductor chip. As a result of being able to make the adhesive layer on the joint surface extremely thin, the thermal resistance of the joint can be reduced.
Heat dissipation characteristics can be improved while achieving relaxation of stress due to thermal expansion.
第1図は本発明による半導体パッケージの一実施例を示
す断面図、
第2図は本発明の第2実施例の主要部を示す斜視図、
第3図は本発明の第3実施例の主要部を示す斜視図、
第4図は熱拡散板の凸部に設ける溝の他の例を示す平面
図、
第5図は凸部に設ける溝の更に他の例を示す平面図、
第6図は第1図における貫通孔の他の形成状態を示す断
面図である。
1・・・熱拡散板、1a・・・凸部、2・・・貫通孔、
3・・・半導体チップ、4・・・ペース、5・・・リー
ドピン、6・・φボンディングワイヤ、7・・・接着剤
、8・・・溝、9・・・突起。
代理人 弁理士 筒 井 大 和
第
図
9:突起
第
図
第5FIG. 1 is a sectional view showing one embodiment of a semiconductor package according to the present invention, FIG. 2 is a perspective view showing main parts of a second embodiment of the invention, and FIG. 3 is a main part of a third embodiment of the invention. FIG. 4 is a plan view showing another example of grooves provided in the convex portion of the heat diffusion plate; FIG. 5 is a plan view showing still another example of grooves provided in the convex portion; FIG. 6 2 is a sectional view showing another state of formation of the through hole in FIG. 1. FIG. DESCRIPTION OF SYMBOLS 1... Heat diffusion plate, 1a... Convex part, 2... Through hole,
3...Semiconductor chip, 4...Pace, 5...Lead pin, 6...φ bonding wire, 7...Adhesive, 8...Groove, 9...Protrusion. Agent Patent Attorney Daiwa Tsutsui Figure 9: Protrusion Figure 5
Claims (1)
される半導体パッケージであって、前記半導体チップの
接合部に前記樹脂接着剤の逃げ部を前記熱拡散板に形成
したことを特徴とする半導体パッケージ。 2、前記逃げ部が、一定間隔に設けられた複数の貫通孔
であることを特徴とする請求項1記載の半導体パッケー
ジ。 3、前記逃げ部が、複数の溝であることを特徴とする請
求項1記載の半導体パッケージ。 4、前記逃げ部は、相互に隙間を有するようにして前記
接合部に配設された複数の柱状体の集合によることを特
徴とする請求項1記載の半導体パッケージ。[Scope of Claims] 1. A semiconductor package in which a semiconductor chip is bonded to a heat diffusion plate using a resin adhesive, wherein a relief part of the resin adhesive is provided to the heat diffusion plate at a bonded portion of the semiconductor chip. A semiconductor package characterized by forming. 2. The semiconductor package according to claim 1, wherein the relief portion is a plurality of through holes provided at regular intervals. 3. The semiconductor package according to claim 1, wherein the relief portion is a plurality of grooves. 4. The semiconductor package according to claim 1, wherein the relief portion is a collection of a plurality of columnar bodies arranged at the joint portion with gaps between them.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2138941A JPH0432254A (en) | 1990-05-29 | 1990-05-29 | Semiconductor package |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2138941A JPH0432254A (en) | 1990-05-29 | 1990-05-29 | Semiconductor package |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0432254A true JPH0432254A (en) | 1992-02-04 |
Family
ID=15233732
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2138941A Pending JPH0432254A (en) | 1990-05-29 | 1990-05-29 | Semiconductor package |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0432254A (en) |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2001029509A1 (en) * | 1999-10-18 | 2001-04-26 | Matsushita Electric Industrial Co., Ltd. | Angular speed sensor |
JP2005247027A (en) * | 2004-03-02 | 2005-09-15 | Nissan Motor Co Ltd | Mounting structure of fuel filter of automobile |
JP2013051386A (en) * | 2011-07-29 | 2013-03-14 | Kobe Steel Ltd | Heat sink and manufacturing method of the same |
WO2016009635A1 (en) * | 2014-07-16 | 2016-01-21 | セイコーエプソン株式会社 | Sensor unit, electronic apparatus, and mobile body |
JP2016023931A (en) * | 2014-07-16 | 2016-02-08 | セイコーエプソン株式会社 | Sensor unit, electronic apparatus, and mobile body |
JP2017020829A (en) * | 2015-07-08 | 2017-01-26 | セイコーエプソン株式会社 | Sensor unit, electronic apparatus, and movable body |
KR20220068878A (en) * | 2020-11-19 | 2022-05-26 | 칩본드 테크놀러지 코포레이션 | Circuit board and thermal paste thereof |
-
1990
- 1990-05-29 JP JP2138941A patent/JPH0432254A/en active Pending
Cited By (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2001029509A1 (en) * | 1999-10-18 | 2001-04-26 | Matsushita Electric Industrial Co., Ltd. | Angular speed sensor |
US6619122B1 (en) | 1999-10-18 | 2003-09-16 | Matsushita Electric Industrial Co., Ltd. | Angular speed sensor |
JP2005247027A (en) * | 2004-03-02 | 2005-09-15 | Nissan Motor Co Ltd | Mounting structure of fuel filter of automobile |
JP2013051386A (en) * | 2011-07-29 | 2013-03-14 | Kobe Steel Ltd | Heat sink and manufacturing method of the same |
WO2016009635A1 (en) * | 2014-07-16 | 2016-01-21 | セイコーエプソン株式会社 | Sensor unit, electronic apparatus, and mobile body |
JP2016023931A (en) * | 2014-07-16 | 2016-02-08 | セイコーエプソン株式会社 | Sensor unit, electronic apparatus, and mobile body |
US10551194B2 (en) | 2014-07-16 | 2020-02-04 | Seiko Epson Corporation | Sensor unit, electronic apparatus, and moving body |
US11041723B2 (en) | 2014-07-16 | 2021-06-22 | Seiko Epson Corporation | Sensor unit, electronic apparatus, and moving body |
JP2017020829A (en) * | 2015-07-08 | 2017-01-26 | セイコーエプソン株式会社 | Sensor unit, electronic apparatus, and movable body |
KR20220068878A (en) * | 2020-11-19 | 2022-05-26 | 칩본드 테크놀러지 코포레이션 | Circuit board and thermal paste thereof |
JP2022081373A (en) * | 2020-11-19 | 2022-05-31 | ▲き▼邦科技股▲分▼有限公司 | Circuit board |
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