JPS63220666A - Image processing device - Google Patents

Abstract

PURPOSE:To attain the picture element density conversion of a compressed code at a high speed processing speed by thinning and inputting an image synchronizing signal to a signal means, inputting the image data of a preceding line to an encoding means and executing the encoding processing. CONSTITUTION:A control part D for picture element density conversion, in the scope where one line of image data is effective in accordance with a picture element density, thins and inputs an image synchronizing signal CLK to a decoding device A, the image synchronizing signal CLK is inputted to an encoding device E without thinning, and thus, the picture element density in a main scanning direction is raised, a line synchronizing signal BD-DR inputted to a decoding device B in accordance with the picture element density is thinned and a decoding processing is stopped. In addition, the image data of the preceding line are inputted to the encoding device E, the encoding processing is executed, and thus, from the image data encoded already by raising the picture element in the sub-scanning direction, the compressed code to raise the picture element density is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to an image processing device that processes image data.

[Prior art]

Conventionally, devices for encoding and decoding compressed codes have been composed of microcomputer ROMs, RAMs, etc., and pixel density conversion, which is essential for facsimile machines, has also been performed using microcomputer ROMs, RAMs, etc. Therefore, since the conversion process of the pixel density of the compressed image data is also performed by software processing, high-speed processing cannot be expected.

[eyes]

The present invention has been made in view of the above points, and it is an object of the present invention to provide an image processing apparatus capable of converting the pixel density of a compressed coat at a high processing speed.

〔Example] The details of the present invention will be explained using the drawings.

FIG. 1 is a block diagram showing an embodiment of an image processing apparatus to which the present invention is applied. In FIG. 1, A is a storage circuit in which compressed codes of image data are stored. B decodes the compressed code in real time, for example, in Japanese Patent Application 1986-1.
This is a decoding device as shown in 75306. C is RO
M is a control section consisting of a RAM microcomputer, etc., and D is a pixel density conversion control section. The operation of the decoding device B is controlled by the control section C as well as the pixel density conversion control section, and the decoding device B is operated by the storage circuit A.
Take out the compression coat from the image synchronization clock CLKD.
The decryption process is executed in synchronization with the

E encodes the compressed code in real time, for example,
0-170803. The coding device E is controlled by the pixel density conversion control of the control unit C, and performs coding processing in synchronization with the image synchronization clock CLKE based on the image data decoded by the decoding device B. The compressed code data is output and stored in the memory bag ff/I'F.

Here, the VSYNC number does not indicate that the image signal page 1 is valid, but the page synchronization signal, and the VEN, VEN
E im is a line synchronization signal indicating that one line of image data is valid.

Further, VIDEOl and VIDEO2+j are image data, CLKD, CLKE, and CLK are image synchronization signals, and BD-DR-D is a line synchronization signal requesting decoding device B to start decoding one line.

In the configuration shown in FIG. 1, the pixel density conversion control section inputs the image synchronization signal CLK to the decoding device A in a muted manner within the range where the image data line is valid according to the pixel density, and converts the image synchronization signal CLK to the decoding device A. The image synchronization signal CLK is sent to the conversion device E.
The pixel density in the main scanning direction is increased by inputting without paralyzing the line synchronization signal BD-DR input to the decoding device B according to the pixel density, the decoding process is stopped, and the pixel density is increased in the main scanning direction. By inputting the image data of the previous line into the image data and increasing the pixel density in the sub-scanning direction by executing the encoding process, the pixel density is lowered from the image data that has already been encoded. This is number 7.

Next, FIG. 2 shows a specific circuit configuration of the pixel density conversion control section shown in FIG. 1. As an example of operation, pixel density or 2
FIG. 3 shows the pixel density conversion operation when the density is doubled.

ρ FIG. 2 is an example of a circuit that can increase the pixel density to u-1-(2≦l≦16). First, the control unit C instructs the decoding device B that the number of pixels in one line is m, and also instructs the encoding device E that the number of pixels in one line is Qm or 7'.Next, Control unit C issues an instruction to start decoding to decoding device B. Decoding device B outputs a VSYNC signal, which is a page synchronization signal, as shown in FIG. wait for it to happen.

Now, the pixel density is set to 2 in registers 21 and 22 in Figure 2.
If we consider the case where the number is 4, the complement of 2 of 2 is input, and the counter (F163, etc. manufactured by Fairgilt Inc., USA) 23
．． 24 will work as a binary counter.

When considered in the sub-scanning direction, the counter 24 functions as a binary counter as shown in FIG. 3, and functions to paralyze the BD-DR signal input from the control section C to L. The BD-DR signal spread over the two is input to the decoding device B as a BD-DR-D signal, and the decoding device B decodes one line of the compressed two']. However, since the image data output from the decoding device B does not indicate a valid range and is only half of the VEN signal, it is output from the buffer memory 25 by the line I non-guess address counter 26. The address No. 18 is controlled by RWP, which is a write pulse, and outputs image data of all lines in synchronization with the VEN signal.

As shown in ``2'', the image data of the number of lines adjacent to the number of lines output from the decoding device B is input to the encoding device E in the sub-scanning direction at L).

Next, considering the main scanning direction, the counter 23 works as a binary counter in synchronization with the VEN signal, and halves the image synchronization clock CLK input to the decoding device B. However, since the image synchronization clock CLK is input as is to the encoding device E, 1 b i of the VIDEO2 signal output from the decoding device B or the line buffer memory 25
70 encoding is performed with minutes as 2 bits.

As described above, a compressed code with twice the number of pixels in the main scanning direction and the sub-scanning direction is output from the encoding device E, and pixel density conversion is realized.

As described above, by setting values corresponding to the desired pixel density conversion ratio in the registers 21 and 22, pixel density conversion is executed at high speed by the hardware configuration.

! In the example, a circuit capable of converting the pixel density of -F-T-T (2≦℃≦16) was shown. -1° ft
An arbitrary pixel density conversion of -2° to -3 is possible.

〔effect〕

As described above, according to the present invention, it is possible to convert the pixel density of compressed image data at high speed.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an image processing device to which the present invention is applied, FIG. 2 is a block diagram showing the configuration of a pixel density conversion control section, and FIG. 3 is a timing diagram showing the circuit operation shown in FIG. , B is a decoding device, D is a pixel density conversion control unit, and E is an encoding device.

Claims (1)

[Claims] It has a decoding means for decoding the compressed code, a compression means for encoding the image data, and a control means for controlling the operations of the compression means and the decoding means, and the control means controls the image data according to the pixel density. Within the range where one line is valid,
The pixel density in the main scanning direction is increased by inputting an image synchronization signal to the decoding means without being mixed, and inputting the image synchronization signal to the encoding means without being mixed, and the decoding means according to the pixel density. The pixel density in the sub-scanning direction is increased by inputting a line synchronization signal to be input to the encoder, stopping the decoding process, inputting the image data of the previous line to the encoding means, and causing the encoder to execute the encoding process. Image processing device.