JPS63220667A - Image processing device - Google Patents

Abstract

PURPOSE:To attain the picture element density conversion of a compressed code at a high speed processing speed by thinning a line enable signal outputted from an image synchronizing clock and a decoding means in accordance with the rate to decrease a picture element density and inputting it to a compressing means. CONSTITUTION:A control circuit C for picture element density conversion is controlled by a control circuit F, and outputs, in accordance with the rate to be converted, a page synchronizing signal VSYNC to input, a VEN to show a scope in which the image data of one line are effective, decoded image data VIDEO1, a CLKE signal to thin a CLK signal from the CLK signal which is an image synchronizing clock, a VENE signal to thin a VEN signal and a VIDEO2 signal. An encoding circuit D encodes image data from the VSYNC, VENE, VIDEO2 and CLKE signals as the number of picture elements of m (m<n) per one line by the control circuit F and outputs the compressed code to a memory circuit E. Thus, the data to encode to the compressed code to provide a picture element density with the same image data are obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to an image processing device that processes image data.

[Prior art]

Conventionally, devices for encoding and decoding compressed data 1 to 1 have been configured with microcomputer ROM, RAM, etc., and pixel density conversion has also been performed using microcomputer ROM, RAM, etc. Therefore, since the conversion process of the pixel density of the compressed image data is also performed by software processing, high-speed processing cannot be expected.

(Objective) The present invention has been made in view of the above points, and it is an object of the present invention to provide an image processing device capable of converting the pixel density of a compressed code at high processing speed.

〔Example〕

Details of the wood invention will be explained using drawings.

FIG. 1 is a block diagram showing an outline of an embodiment of an image processing apparatus to which the tree invention is applied.

A is a storage circuit in which compressed codes are stored. Patent application 17530/1986 for decoding compressed codes in real time
The decoding circuit B as shown in No. 6 is controlled by a control unit F consisting of a ROM, a RAM microcomputer, etc., and sequentially reads compressed codes from the storage circuit A as n pixels per line, and reads out the compressed code from the storage circuit A as an image synchronization clock signal CLKD. Execute decryption in synchronization with

The decoding circuit B outputs the page synchronization signal VSYNC11 line image data, the VEN signal indicating the valid range, and the decoded image data VI.
Outputs DEOI signal.

The pixel density conversion control circuit C is controlled by the control circuit F, and input VSYNC, VEN,
VIDEOl and image synchronization clock output CLK signal from the CLK signal (CLKE signal with paralyzed No. 8, VENE signal with paralyzed VEN signal, and VIDEO2 signal (VIDEOI=VIDEO2).

Patent application 1708/1986 for encoding compressed codes in real time
The code circuit as shown in No. 03 is the control circuit FJ:S1
VSYNC as the number of m (m<n) pixels per line,
Image data is encoded from the VENE and VIDEO2°CLKE signals, and a compressed code is output to the storage circuit E.

In the configuration shown in FIG. 1, the compressed code that encodes the image data is decoded by the decoding circuit B, and the image synchronization clock CLK and one line of image data outputted from the decoding circuit B at F14 are within the effective range. By inputting the line enable signal VEN to the pixel density conversion control circuit C and to the encoding circuit according to the rate at which the pixel density is decreased, a compressed code with a different pixel density is generated using the same image data. This method obtains data encoded into .

Next, as an example -C-L:''-(2<, n<: ]
6) +7) Figure 2 is a concrete circuit of a pixel density conversion control circuit that can convert pixel density, and the pixel density is set to 1.
The relationship between CLK and CLKE, and between VEN and VENE will be shown in detail using FIG.

Let us now consider the case where the pixel density is set to 1-1.The two's complement number is stored in the registers 21 and 22 using the signals D7 to Do and WP from the control section. Here, if ρ-3, then D, which is the two's complement of 3, is stored. Counter (for example, US Fairdale] manufactured by FI63) 2
3.24 continues the operation from Callan 1 according to the LD and CLK inputs as shown in FIG.

Now, considering the main scanning direction, the VEN signal or Hi
g h (When D, the number of edges in the CLKE signal is 1 compared to the CLK signal, so CLKE (m
The encoder circuit that receives the signal or the image synchronization clock signal quantizes the VIDEO2 signal in terms of the number of pixels, and can automatically calculate the pixel density. Similarly, since the VENE signal in the sub-scanning direction is more powerful than the VEN signal, the encoding circuit that encodes one line according to the VENE signal can also reduce the number of lines of image data. 7], and the pixel density can also be reduced in the sub-scanning direction.

In the example, a circuit capable of converting the pixel density of -7-(2≦x≦16) was shown, but by adding a plurality of counters, the pixel density of a residence of 12In-2n23----- was shown. Conversion is possible.

In this way, the value corresponding to the pixel density conversion rate is calculated by counter 2.
+, 22 allows arbitrary pixel density conversion to be performed at high speed depending on the hardware configuration.1. f
Ru.

〔effect〕

As described above, according to the present invention, pixel density conversion of compressed image data can be performed at high speed.

4 Brief Description of the Drawings FIG. 1 is a block diagram of an image processing device to which the present invention is applied, FIG. 2 is a specific circuit diagram of the pixel density conversion control circuit shown in FIG. FIG. 1 is a timing chart 1 when converting density.

B is a decoding circuit, C is a pixel density conversion control circuit, D is a coding circuit, and F is a control section.

Claims (1)

[Claims] It has a decoding means for decoding the compressed code, a compression means for encoding the image data, and a control means for controlling the operation of the decoding means and the compression means, and the control means has an image synchronization clock and the decoding means. converting the pixel density using the same image data by scattering a line enable signal indicating a valid range of one line of image data to be output in accordance with the rate at which the pixel density is reduced and inputting it to the compression means; An image processing device characterized by: