JPS6322056B2 - - Google Patents
Info
- Publication number
- JPS6322056B2 JPS6322056B2 JP54156789A JP15678979A JPS6322056B2 JP S6322056 B2 JPS6322056 B2 JP S6322056B2 JP 54156789 A JP54156789 A JP 54156789A JP 15678979 A JP15678979 A JP 15678979A JP S6322056 B2 JPS6322056 B2 JP S6322056B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- semiconductor film
- single crystal
- amorphous
- grain boundaries
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
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- 239000004065 semiconductor Substances 0.000 claims description 35
- 239000013078 crystal Substances 0.000 claims description 34
- 238000000034 method Methods 0.000 claims description 17
- 239000000758 substrate Substances 0.000 claims description 13
- 239000002344 surface layer Substances 0.000 claims description 6
- 238000010438 heat treatment Methods 0.000 claims description 4
- 238000005468 ion implantation Methods 0.000 claims description 4
- 230000001678 irradiating effect Effects 0.000 claims 1
- 239000010408 film Substances 0.000 description 55
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 10
- 229910004298 SiO 2 Inorganic materials 0.000 description 5
- 229910021417 amorphous silicon Inorganic materials 0.000 description 5
- 230000007547 defect Effects 0.000 description 5
- 229910052594 sapphire Inorganic materials 0.000 description 4
- 239000010980 sapphire Substances 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 238000000137 annealing Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000001747 exhibiting effect Effects 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/0242—Crystalline insulating materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02488—Insulating materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02587—Structure
- H01L21/0259—Microstructure
- H01L21/02598—Microstructure monocrystalline
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02609—Crystal orientation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
- H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Materials Engineering (AREA)
- Optics & Photonics (AREA)
- Recrystallisation Techniques (AREA)
Description
【発明の詳細な説明】
本発明は、単結晶半導体膜形成法に関し、特に
アモルフアス誘電体上に実質的に結晶粒界性の結
晶欠陥を含まない単結晶半導体膜を形成する方法
に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for forming a single crystal semiconductor film, and more particularly to a method for forming a single crystal semiconductor film substantially free from grain boundary crystal defects on an amorphous dielectric.
従来、誘電体基板又は誘電体膜上に単結晶半導
体膜を形成する方法としてはいくつかのものが提
案されているが、それぞれ問題点を含んでいる。
例えば、単結晶サフアイア基板上に単結晶シリコ
ン膜をエピタキシヤル成長させるいわゆるSOS
（シリコン・オン・サフアイア）技術は、基板誘
電体と成長半導体との格子定数の差に起因して成
長半導体膜に多数の結晶欠陥が生ずる欠点があ
る。また、他の例として、誘電体膜上に形成した
多結晶状又はアモルフアス状の半導体膜をレーザ
ー・ビームの如きエネルギービームで照射加熱し
ながら走査して単結晶半導体膜に変換する技術が
公知である（例えば、K.F.Lee、J.F.Gibbons
and K.C.Saraswat、“Thin Film MOS FETs
fabricated inLaser−annealed poly silicon”A.
P.L.35(2)、p.p.173〜175（1979）参照）。しかし、
これには、断面スポツト状のレーザービームを用
いているため隣接する走査領域のつなぎ目におい
てアニール処理が不均一になり、結晶粒界性の結
晶欠陥が生ずる欠点がある。さらに他の例とし
て、単結晶シリコン又は単結晶サフアイアからな
る基板上に成長させた単結晶シリコン膜をイオン
打込処理してアモルフアス半導体膜に変換した
後、このアモルフアス半導体膜を加熱処理して単
結晶半導体膜に変換する技術が公知である（例え
ば、S.S.Lanetal.“improvement of crystalline
quality of epitaxial Si layers by
ioninplantation techniques”A.P.L.34(1)．p.
p.76−78（1979）参照）。しかし、これにおいて
も、単結晶半導体膜の下地としての基板が単結晶
体でなければならないという制限がある。 Conventionally, several methods have been proposed for forming a single crystal semiconductor film on a dielectric substrate or a dielectric film, but each method has its own problems.
For example, so-called SOS, which epitaxially grows a single-crystal silicon film on a single-crystal sapphire substrate,
The (silicon-on-sapphire) technology has the disadvantage that a large number of crystal defects occur in the grown semiconductor film due to the difference in lattice constant between the substrate dielectric and the grown semiconductor. As another example, there is a known technique in which a polycrystalline or amorphous semiconductor film formed on a dielectric film is scanned while being irradiated and heated with an energy beam such as a laser beam to convert it into a single crystal semiconductor film. (e.g. KFLee, JFGibbons
and KCSaraswat, “Thin Film MOS FETs
fabricated inLaser−annealed poly silicon”A.
(See PL35(2), pp173-175 (1979)). but,
This method uses a laser beam with a spot-shaped cross section, so the annealing process becomes non-uniform at the joints between adjacent scan areas, resulting in crystal defects at grain boundaries. As yet another example, a single crystal silicon film grown on a substrate made of single crystal silicon or single crystal sapphire is converted into an amorphous semiconductor film by ion implantation, and then this amorphous semiconductor film is heat treated to form a single crystal silicon film. Technologies for converting crystalline semiconductor films into crystalline semiconductor films are known (for example, SSLanetal. “improvement of crystalline
quality of epitaxial Si layers by
ioninplantation techniques”APL34(1).p.
(See p. 76-78 (1979)). However, even in this case, there is a restriction that the substrate as the base of the single crystal semiconductor film must be a single crystal.
本発明の目的は、上記した従来技術の欠点をな
くし、SiO2膜等のアモルフアス誘電体上であつ
ても無欠陥の単結晶半導体膜を形成することので
きる新規な単結晶半導体膜形成法を提供すること
にある。 The purpose of the present invention is to eliminate the drawbacks of the above-mentioned conventional techniques and to provide a new method for forming a single crystal semiconductor film that is capable of forming a defect-free single crystal semiconductor film even on an amorphous dielectric such as a SiO 2 film. It is about providing.
本発明の方法は、誘電体基板又は誘電体膜上に
形成された多結晶状又はアモルフアス状の半導体
膜をエネルギービームで照射加熱しながら走査す
ることにより結晶粒界を含む単結晶半導体膜に変
換する工程と、前記単結晶半導体膜をイオン打込
処理してアモルフアス半導体膜に変換する工程
と、前記アモルフアス半導体膜の表面層を除去す
る工程と、前記アモルフアス半導体膜を加熱処理
して実質的に結晶粒界を含まない単結晶半導体膜
に変換する工程とを含むことを特徴とするもの
で、以下、添付図面に示す実施例について詳述す
る。 The method of the present invention converts a polycrystalline or amorphous semiconductor film formed on a dielectric substrate or dielectric film into a single crystal semiconductor film containing crystal grain boundaries by scanning it with an energy beam while heating it. a step of converting the single crystal semiconductor film into an amorphous semiconductor film by ion implantation; a step of removing a surface layer of the amorphous semiconductor film; and a step of heat-treating the amorphous semiconductor film to substantially The method is characterized in that it includes a step of converting it into a single crystal semiconductor film that does not contain grain boundaries.Hereinafter, embodiments shown in the accompanying drawings will be described in detail.
第１ａ図乃至第１ｅ図は本発明の一実施例を示
すもので、各々の図に対応する工程ａ〜ｅは次の
通りである。 Figures 1a to 1e show an embodiment of the present invention, and steps a to e corresponding to each figure are as follows.
(a) まず、単結晶シリコン（Si）基板１０の表面
に公知の熱酸化法により約1μｍの厚さにSiO2
膜１１を形成する。(a) First, SiO 2 is deposited on the surface of a single crystal silicon (Si) substrate 10 to a thickness of approximately 1 μm using a known thermal oxidation method.
A film 11 is formed.
(b) 次に、SiO2膜１１上にSiH4の分解により多
結晶状もしくはアモルフアス状のSi膜１２を約
0.5μｍの厚さに形成する。(b) Next, a polycrystalline or amorphous Si film 12 is formed on the SiO 2 film 11 by decomposing SiH 4 .
Form to a thickness of 0.5 μm.
(c) 次に、Si膜１２をレーザービーム１３で照射
加熱しながら走査して熱処理（アニール）し、
それによつてSi膜１２を、（100）結晶面を呈す
る単結晶Si膜１２Ａに変換する。このとき、Si
膜１２Ａにおいて隣接する走査領域のつなぎ目
には結晶粒界GBが生成されるので、ここには
結晶粒界性の結晶欠陥が存在する。(c) Next, the Si film 12 is scanned and heat-treated (annealed) while being irradiated and heated with the laser beam 13.
Thereby, the Si film 12 is converted into a single crystal Si film 12A exhibiting a (100) crystal plane. At this time, Si
Since a grain boundary GB is generated at the joint between adjacent scan areas in the film 12A, a grain boundary crystal defect exists there.
(d) 次いで、Si膜１２ＡにSiイオン１４を打込
み、Si膜１２ＡをアモルフアスSi膜１２Ｂに変
換する。ここで、Si膜１２Ｂの表面層には若干
の結晶粒界GBが残存することがあるので、そ
の結晶粒界を除去すべくSi膜１２Ｂの表面層を
エツチ除去する。これによつて、後述の加熱処
理によりこのアモルフアスSi膜１２Ｂ全体を結
晶粒界を有しない無欠陥の単結晶Si膜１２Ｃに
確実に変換することができる。(d) Next, Si ions 14 are implanted into the Si film 12A to convert the Si film 12A into an amorphous Si film 12B. Here, since some grain boundaries GB may remain in the surface layer of the Si film 12B, the surface layer of the Si film 12B is etched to remove the grain boundaries. Thereby, the entire amorphous Si film 12B can be reliably converted into a defect-free single-crystal Si film 12C having no crystal grain boundaries by the heat treatment described below.
(e) この後、第１ｄ図の構成になる基板１０を熱
処理炉に入れ、不活性ガス雰囲気中において約
550℃の温度で約30分間熱処理し、Si膜１２Ｂ
を単結晶Si膜１２Ｃに変換する。このとき形成
されるSi膜１２Ｃは（100）結晶面を呈し、し
かも実質的に結晶粒界を有しないので結晶粒界
性の結晶欠陥を実質的に含まないものである。(e) After this, the substrate 10 having the configuration shown in FIG.
Heat treated at a temperature of 550℃ for about 30 minutes to form Si film 12B.
is converted into a single crystal Si film 12C. The Si film 12C formed at this time exhibits a (100) crystal plane and has substantially no crystal grain boundaries, so it contains substantially no crystal defects due to grain boundaries.
上記した本発明の方法によれば、SiO2の如き
アモルフアス誘電体上に無欠陥の単結晶半導体膜
を形成することができるので、この単結晶半導体
膜を用いてPN接合デバイス等を構成すればその
デバイスは接合リーク電流が少なく且つキヤリヤ
ライフタイム等の諸特性が優れたものとなる。ま
た、イオン打込処理により変換されたアモルフア
ス半導体膜の表面層を除去しているので、この表
面層に残存することがある結晶粒界を完全に除去
することができ、従つてその後の加熱処理により
このアモルフアス半導体膜全体を結晶粒界を有し
ない無欠陥の単結晶半導体膜に確実に変換するこ
とができる。 According to the method of the present invention described above, a defect-free single crystal semiconductor film can be formed on an amorphous dielectric such as SiO 2 , so if a PN junction device or the like is constructed using this single crystal semiconductor film, The device has low junction leakage current and excellent characteristics such as carrier lifetime. Furthermore, since the surface layer of the amorphous semiconductor film converted by the ion implantation process is removed, it is possible to completely remove the grain boundaries that may remain in this surface layer. This allows the entire amorphous semiconductor film to be reliably converted into a defect-free single crystal semiconductor film having no crystal grain boundaries.
なお、上記実施例において、第１ｃ図〜第１ｅ
図の工程は何回かくりかえしてもよく、このよう
にすれば一層結晶性を改善することができる。 In addition, in the above embodiment, FIGS. 1c to 1e
The process shown in the figure may be repeated several times, and by doing so, the crystallinity can be further improved.
また、上記した本発明の方法は、単結晶サフア
イア基板などの表面に形成したSi膜の結晶性改善
のためにも適用することができる。 Furthermore, the method of the present invention described above can also be applied to improve the crystallinity of a Si film formed on the surface of a single crystal sapphire substrate or the like.
第１ａ図乃至第１ｅ図は、本発明の一実施例を
示す基板断面図である。
１０……Si基板、１１……SiO2膜、１２……
多結晶Si又はアモルフアスSi膜、１２Ａ……結晶
粒界を有する単結晶Si膜、１２Ｂ……アモルフア
スSi膜、１２Ｃ……結晶粒界を有しない単結晶Si
膜、１３……レーザービーム、１４……Siイオ
ン。
FIGS. 1a to 1e are cross-sectional views of a substrate showing an embodiment of the present invention. 10...Si substrate, 11...SiO 2 film, 12...
Polycrystalline Si or amorphous Si film, 12A...Single crystal Si film with grain boundaries, 12B...Amorphous Si film, 12C...Single crystal Si without grain boundaries
Film, 13... Laser beam, 14... Si ion.
Claims (1)
晶状又はアモルフアス状の半導体膜をエネルギー
ビームで照射加熱しながら走査することにより結
晶粒界を含む単結晶半導体膜に変換する工程と、
前記単結晶半導体膜をイオン打込処理してアモル
フアス半導体膜に変換する工程と、前記アモルフ
アス半導体膜の表面層を除去する工程と、前記ア
モルフアス半導体膜を加熱処理して実質的に結晶
粒界を含まない単結晶半導体膜に変換する工程と
を含むことを特徴とする単結晶半導体膜形成法。1. A step of converting a polycrystalline or amorphous semiconductor film formed on a dielectric substrate or a dielectric film into a single crystal semiconductor film including crystal grain boundaries by scanning the polycrystalline or amorphous semiconductor film formed on the dielectric substrate or dielectric film while irradiating and heating it with an energy beam;
A step of converting the single crystal semiconductor film into an amorphous semiconductor film by ion implantation, a step of removing a surface layer of the amorphous semiconductor film, and a heat treatment of the amorphous semiconductor film to substantially remove crystal grain boundaries. A method for forming a single crystal semiconductor film, comprising the step of converting the film into a single crystal semiconductor film that does not contain the same.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15678979A JPS5680126A (en) | 1979-12-05 | 1979-12-05 | Formation of monocrystalline semiconductor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15678979A JPS5680126A (en) | 1979-12-05 | 1979-12-05 | Formation of monocrystalline semiconductor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5680126A JPS5680126A (en) | 1981-07-01 |
| JPS6322056B2 true JPS6322056B2 (en) | 1988-05-10 |
Family
ID=15635334
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15678979A Granted JPS5680126A (en) | 1979-12-05 | 1979-12-05 | Formation of monocrystalline semiconductor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5680126A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0423046U (en) * | 1990-06-15 | 1992-02-25 |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5837913A (en) * | 1981-08-28 | 1983-03-05 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
| JPS5861622A (en) * | 1981-10-09 | 1983-04-12 | Hitachi Ltd | Manufacture of single crystal thin film |
| JPS58175827A (en) * | 1982-04-07 | 1983-10-15 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
| JPH0817157B2 (en) * | 1984-11-30 | 1996-02-21 | ソニー株式会社 | Method for manufacturing thin film transistor |
| JPH0824103B2 (en) * | 1984-11-26 | 1996-03-06 | ソニー株式会社 | Method for manufacturing thin film transistor |
| US4749660A (en) * | 1986-11-26 | 1988-06-07 | American Telephone And Telegraph Company, At&T Bell Laboratories | Method of making an article comprising a buried SiO2 layer |
| JPH0397224A (en) * | 1989-09-11 | 1991-04-23 | Toshiba Corp | Manufacture of semiconductor device |
| KR0124626B1 (en) * | 1994-02-01 | 1997-12-11 | 문정환 | Thin filem transistor manufacturing method |
-
1979
- 1979-12-05 JP JP15678979A patent/JPS5680126A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0423046U (en) * | 1990-06-15 | 1992-02-25 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5680126A (en) | 1981-07-01 |
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