JPS63220476A - Data recording and reproducing system - Google Patents

Abstract

PURPOSE:To surely perform a reproducing operation at the time of losing a data mark, by providing the same trigger signal generation function as that of the data mark on plural resynchronizing codes following after the rear of the data mark. CONSTITUTION:In the titled system, a data signal input line 1, a 2-7 encoder 25, a clock signal input line 27, a demodulation data line 3, a change-over switch 24, a composite data line 4, a recording signal line 5, an RS pattern generator 6, a counter 7, and a recording amplifier 8 are provided. And a signal string regulated to violate to a signal recording string rule obtained by the modulation of an original data in advance is recorded as a resynchronizing signal at the time of recording. And when reproduction is performed normally, the finding of (signal string violating to rule) is set as opportunity to reset a demodulation circuit, and at the time of reproduction when the data mark is lost, the finding of the (signal string violating to rule) is set as the opportunity to start the demodulation of the whole of sectors consisting of data field groups. In such a way, since an alternate means for a lost data mark can be offered, it is possible to lower a rate impossible to read the sector.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a data recording and reproducing method for a disk type recording device such as an optical disk device.

In particular, the present invention relates to a data recording and reproducing method for a disk-type recording device that is not easily affected by many defects on the medium.

(Prior Art) In the recording/reproducing operation of a conventional optical disk device, demodulation of recorded data is started based on a single data mark existing at the beginning of a data sector.

(Problem to be Solved by the Invention) Therefore, even if a data mark cannot be found due to a media shortage occurring near the beginning of a data sector, there is a drawback that demodulation of the entire data sector becomes impossible. .

This has been a weak point in the optical disc subsystem, which is configured to maintain the integrity of reproduced data by using multiple redundancy means such as error correction codes, resulting in a significant lack of balance.

The purpose of the present invention is to utilize the power of error correction codes to enable demodulation of the entire data sector in cases where data marks such as those described above cannot be found. ) It is an object of the present invention to provide a data recording and reproducing method for a storage device that enables the use of media and reduces the cost of the entire system.

Another object of the present invention is to provide a data recording and reproducing method for a storage device that uses a medium of the same quality and has a lower error rate.

(Means and Effects for Solving the Problems) In the present invention, recording is performed using a resynchronization code designed to prevent the loss of data marks from immediately leading to reading errors for the entire sector, as in the prior art. In other words, the main feature is that the resynchronization codes that follow the data mark have the same trigger signal generation function as the data mark, so that the regeneration operation can be performed reliably even when the data mark is lost. shall be.

(Embodiment) FIG. 1 shows a first embodiment of the present invention, in which 1 is a data signal input line, 25 is a 2-7 encoder, 2 is a clock signal line, 3 is a demodulation data line, and 24 is a switching line. switch,
4 is a composite data line, 5 is a recording signal line, 6 is an RSS butter generator, 7 is a counter, and 8 is a recording amplifier.

FIG. 2 is an explanatory diagram of the encoding method common to each of the following embodiments.

Embodiment 1 In preparation for explaining the embodiment, first, a method of configuring a known error correction code (ECC) used in this embodiment will be briefly explained. FIG. 2 illustrates the case of a long φ distance code, which is a type of interleaved Reed-Solomon code, in which one sector is constructed by adding 160 bytes of parity to 1040 bytes of user data. One frame in this ECC consists of 104 bytes of user data and 16 bytes of user data.
It is 120 bytes consisting of byte parity, and encoding φ decoding is performed in units of frames. The entire sector has a structure in which these frames are stacked in 10 stages.

Although it is known that in the FCC having such a structure, an error of up to 8 bytes can be tolerated within the n-th ECC frame, but the present invention is not limited to the ECC capacity.

Also, when recording one-dimensionally on a medium, the recording order should be in the direction of the thick white arrow in Figure 2 (interleaving).
It is also known that by doing this, even if an error occurs due to a large medium defect, it is observed and processed as a discrete error within each ECC frame, thereby improving the ECC performance.

The present invention improves the reliability of reproduced data for a data group having an ECC structure as described below.

Recording operation (1) In general, when recording on a rotating disk such as an optical disk, access is performed in units of sectors on a track.
The beginning of the sector contains an address code, a synchronization code (VFO) used as a synchronization signal, and a data mark (
DM) is added and recorded in the arrangement shown in FIG.

The present invention is characterized in that a code that does not occur according to the modulation rules is assigned as a resynchronization code indicated by RS in FIG. 3, thereby facilitating discovery during reproduction. That is, after 2-7 modulation, the R8 part in FIG. 2 is ootoooooootooto.

Allocate 1 byte of virtual data such that

Please be careful. Although the present invention is not limited to this pattern, the present virtual data (1) is 1 byte in terms of data bytes, so it is easy to insert and extract.

(2) Since it does not occur under normal modulation rules, it does not occur in the data portion.

(3) Since the autocorrelation function is relatively sharp, timing can be determined accurately.

It has the following advantages.

In reality, there is no actual data that has such a pattern after modulation, so it is recorded using several methods as described below.

One of them is to switch between the 2-7 encoder and the pattern generator as shown in FIG. That is, immediately after the recording of recording fields 1 and 2 in FIG. 3 is completed, the pattern generator 6 is activated by switch 4.
000000010 (switch to l100” signal, 1
After a time corresponding to 6 bits, the signal is returned to the 2-7 encoder signal side. Immediately after finishing the recording of recording fields 3 and 4, the same operation is performed to "switch" by one data byte.Then, the same operation is repeated until just before recording field 120, and the recording operation is completed.Other methods This will be explained in Example 2.

Playback operation (1) There are two main types of playback operation, one being D.
The other case is when M (data mark) can be found normally, and the other case is when DM cannot be found.

When the DM is normal In this case, the purpose of R8 is to "prevent bit slip" and "prevent error propagation", and as is well known, it operates as follows.

That is, if we follow the playback operation during normal operation in chronological order, first, DM is detected after VFO synchronization, playback of fields 1 and 2 is completed normally, R5I is discovered, and 2
-7 After the decoder reset, playback of fields 3 and 4 is normally started.

On the other hand, for example, a burst error may occur at the beginning of field 2, and the VFO may become out of synchronization. In most cases, the VFO will resynchronize shortly, but since the 2-7 decoder uses past history, it will not necessarily return to normal operation.

Therefore, with the discovery of the first RS (3) that appears next, 2-
There is a known method for resetting the 7 decoder and returning it to normal operation from field 3 onwards. In this case, data equivalent to about one field is lost, but since it is within the ECC's repair capability, it can actually be decoded normally. The above is publicly known.

In case of DM abnormality The present invention is effective in this case.

That is, since the ability of this ECC can repair up to the first eight missing frames, R8 only needs to seize the opportunity to decode by the fourth R5. Therefore, in the case of DM abnormality, substantially normal decoding is completed as follows.

As an example, the case of FIG. 5 where a medium defect occurs in the VFO and DM portions and demodulation cannot be started by fields 1 and 2.3 will be described.

The operation is shown in FIG. 4, where 11 is a reproduction binary signal line, and first a clock is extracted by VFOlB. The 2-field counting counter 19 is connected to S of the address part detection circuit 10.
It is reset by the waveform (A) generated at M or AM, starts clock counting, and connects the RS scheduled gate to the R5 scheduled gate signal line 18 every two fields.
The ND circuit 17 punches out the reproduced binary signal of the part where the RS is likely to be present and sends it to the RS pattern detector 15. . The reason for using the gate signal (B) is to reduce the probability that an RS pattern that does not normally occur within the field will be erroneously generated due to dropout. Therefore, the VFO starts synchronization in the middle of field 4 and R52 can be discovered as described above. First, the 2-7 decoder is reset and decoding is started. Next, the value of the 2-field counting counter 19 is read and it is learned that the discovered R8 is RS (2).

As a result, it is known that decoding has started from field 5 onwards, and the decoded data is input from the position next to RC2 in FIG. After all the data have been input, the factory correction process is started using a known method.

With these sequences, fields 5 and onwards can be successfully demodulated, and missing fields 1 to 4 can also be restored with the help of ECC. Note that the data lost at this time was 4 fields, but this ECC can decrypt up to 8 lost fields.

At this time, the RS of the present invention can be detected without using the decoder 14 (2-'7 demodulation) of the data demodulation circuit, and ■ Since it uses a modulation rule violation pattern, a gate signal prepared in advance is not required. , even if the data mark cannot be detected and the demodulation system is not activated, the decoding circuit reset signal is sent to the RS.
Since it can be generated independently on the pattern detection signal line 12, it can be used as an alternative to DM.

Furthermore, there are multiple resynchronization codes R8 (59 in the example), so if RSI is not good, RS 2, if that is not good, RS
3. You are allowed to retreat in sequence.

The permissible number is determined by the ECC capability, and in this embodiment, erasure of less than the first eight fields is permissible.

Together with true DM, this is equivalent to 5 multiplexing of DM. That is, due to the limit of ECC correction ability, in this example, normal decoding is possible only when the demodulation system is activated by RS4.

Embodiment 2 In the embodiment described above, RS insertion and discovery were performed in a 2-7 modulated code space. Although this method is easy to understand and reliable, it tends to require a rather large amount of hardware. In some cases, it is convenient to insert in the data space before modulation and discover in the data space after demodulation, as shown below.

FIG. 6 shows a second embodiment, and 21 is an EC (not shown).
Recording binary data input line from circuit C, 24 is a switch, 25 is a 2-7 encoder, 26 is a 1-byte pattern generator, 27 is a gate signal generation circuit, 28 is a 1-byte period counter, 29 is a decoder, 30 is a composite data line.

Recording operation (2) According to the 2-7 modulation rule in Figure 7, after modulation, ......0010000000100100
The original data string does not exist. However, the preceding Nth
Regardless of the contents of the original data of the field (remaining data is “none”, “1”, “0”, “OO”, “01”, “0”)
01''), and if the original data (011) is continued, in either case, from the rules of the m7 diagram, --------0010000xxxxxxxxx
This means that around the first half of the 16 code pits of R3 have been generated.

When modulating the next N+l field, data (0010) is prefixed and modulation is started, so that ......001000xx00100100
. . . Nth field l resync pattern 1 This becomes the N+1th field, and the 8 code pits in the latter half of R8 are completed.

In other words, the data (0IIX
By inserting OOIO), a code pit string approximately similar to RS can be obtained. However, 7 to 8 of the encoding period of R8
Since it is necessary to forcibly generate "00" only at the code pit, a reset signal is created by the 1-byte cycle counter 28 and the "3" decoder 29, and the...
- xx...The 2-7 encoder 25 is held in the initial state only during the period.

Through these series of operations, RS (
It is possible to create the Kinsoku pattern required for resynchronization code). This allows processing in a slower data space rather than a faster code space with twice the bit rate.

The recording code string with the RS (resynchronization code) inserted in this way is sent to a recording circuit (not shown) via the line 30,
This is recorded on an optical disc.

Reproduction operation (2) Since the original purpose of the resynchronization code is to prevent bit slips, it is necessary to discover it in a block before the demodulation circuit and to notify the demodulation circuit block of the synchronization state. However, as media quality improves, RS is becoming more popular as a backup for DM.
It is conceivable that this function may become unnecessary in the future. In such a case, it is sufficient to simply discover the RS after the demodulation circuit block and reset the demodulation circuit itself. In this case, similar to the recording operation sequence, high-speed code space processing can be replaced with low-speed data space processing. However, the defect relief ability is somewhat inferior.

FIG. 8 shows such an embodiment, where line 11...
...I)0100(10(1(l I001)
DO・・・・・・Nth field l resyn
c] When a reproduced binary signal such as turn 1 N+1 field is applied, since data (011) is continuously modulated during recording, the first part of R3 "001000..." is naturally reproduced. Data (01
1...) and output to line 36. However, the following “0Ω001001...
・” is a prohibited code, so it is regarded as data (XXXX), that is, unknown 4-bit data, and it is followed by “00.
..." can be demodulated as (・0・) regardless of its continuation part, and the whole is demodulated into 8 bits (Oll -XXXX・0). Therefore, in 1 byte of the RS part, ■
R3 can be detected by utilizing the occurrence of a special sequence of demodulation of data (OILXXXXO) and demodulation of 4-bit prohibited data.

This RS sequence detection signal is generated as follows using the shift register 31 or the like.

32 is a decoder that detects data (...0ILXXXXO...), line 33 is a prohibited code detection signal, and line 18 is R
S scheduled gate signal line. AND these three
When generated by the ND circuit 34, a pulse is generated on its output line 35 at the moment the final bit (0) of R3 appears, and the decoder 14 itself is reset.

As a result, even if the RS code does not match the byte boundary, normal 2-7
Demodulation continues.

In this method, one code bit slip cannot be repaired, but it is not inconvenient because it can be detected by the 2-7 decoder itself as a succession of prohibited codes. Rather, the 2-7 decoder is effective when the byte boundary is incorrect even though the decoder continues to operate normally, and has the advantage of returning to normal in the middle of a sector.

Note that in the first embodiment, RS insertion/discovery is limited to the code space, and in the second embodiment, it is limited to the data space. However, the present invention is not limited to this combination, and it is obvious that insertion and discovery may be performed in separate spaces.

In addition, R3 (resynchronization code) is not limited to the above example, but may include “0010000000010000” or 0
010000000001000”001000000
It goes without saying that a pattern such as 0000100' can also be used.

(Effects of the Invention) As explained above, the data recording and reproducing method of the present invention has the advantage of being able to reduce the rate of unreadable sectors because it can provide a substitute for lost data marks.

In addition, since insertion and detection can be easily realized using relatively simple circuits in both code space and data space, it is possible to use an appropriate method according to the reliability of the medium without changing the recording pattern. It has the advantage of being selectable.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a first embodiment of the present invention;
The figure is an explanatory diagram of the encoding method common to each embodiment of the present invention.
FIG. 4 is an explanatory diagram showing an example of a recording format on a medium according to the present invention, FIG. 4 is a block diagram showing an example of a detection circuit according to the present invention,
5 is a diagram showing an example of a timing chart according to the present invention, FIG. 6 is a block diagram showing an example of a code insertion circuit according to the present invention, FIG. 7 is a diagram for explaining a known modulation rule, and FIG. The figure is a block diagram showing another example of the detection circuit according to the present invention. DESCRIPTION OF SYMBOLS 1... Data signal input line, 2... Clock signal input line, 3... Demodulated data line, 4... Composite data line, 5
... Recording signal line, 6... Pattern generator, 7...
Counter, 8... Recording amplifier, 10... Address detection circuit, 11... Reproduction binary signal line, 12... RS pattern detection signal line, 14... 2-7 decoder, 15.
...Pattern detector, 16-VFo, 17=-AND circuit, 18-...R5 scheduled gate signal line, 19...Counter, 21...Data input line, 24...Switch,
25... 2-7 encoder, 26... Byte pattern generator, 27... Gate signal generation circuit, 28...
Counter, 29...State "3" Decoder, 30...
1 (combination data line, 31...shift register, 32...
・4-bit decoder, 33... prohibited code detection signal line,
34...3-AND circuit. Applicant's agent Patent attorney Takehiko Suzue III Tsune

Claims (2)

[Claims] (1) One data mark that displays the beginning of the data,
In a data recording and reproducing method that records or reproduces m data fields each consisting of n bytes and a plurality of resynchronization codes, it is predetermined in advance to violate the recording signal sequence rules obtained by modulating the original data during recording. The signal sequence that violates the rules is recorded as a resynchronization signal, and during normal playback, the ``signal sequence that violates the rules'' is recorded.
The discovery of the "signal sequence that violates the rules" shall be used as a trigger to reset the demodulation circuit, and during playback when a data mark has been lost, the discovery of the "signal sequence violating the rules" shall be used as a trigger to start demodulating the entire sector consisting of a data field group. A data recording and reproducing method featuring: (2) A data record according to claim 1, characterized in that a "signal string that violates a rule" is discovered by matching a predetermined number of K bits or more in the signal string J bits. Playback method.