JPS63219231A - Data error detecting circuit - Google Patents

Abstract

PURPOSE:To reduce the number of components while simplifying circuit constitution by reading a symbol from a RAM and using a timing signal calculating a syndrome and a timing signal applying prescribed arithmetic processing so as to detect an error. CONSTITUTION:Syndrome calculation means 3-6 obtain a syndrome from a symbol of a RAM 1, the result is subjected to repetitive division by roots 1, alpha-alpha<3> of the 8-th order primitive polynomial to obtain S'0, S'1-S'3. Adder means 7-9 obtain the sum S'0+S'1, S'2+S3 to input the result to a single and a double error detection means 11, 12. The number of times of divisions is counted and stored in the counter means 15. In detecting the relation of S'0+S'1=...=S'2+S'3=0 by the means 11, the presence of one error is detected and the error location (j) is discriminated by the content of the means 15. In case of S'0+S'1=(S'1+S'2)/alpha<a>=(S'2+S'3), the means 12 detects the presence of two data errors to decide error location difference a=i-j, j and i. In this case, a preset means 55 sets 0, 4 to a counter 16 respectively at the detection of C1, C2 error to make the detection operation equal to each other.

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to a data error detection circuit built into a signal processing circuit used in a compact disc (CD) playback device.

(b) Conventional technology CD playback devices create 8-bit symbols from data read in the form of EFM signals from the disc and restore music signal data, but data errors occur in these symbols. Sometimes. This is caused by defects when pits are written on the disc, defects caused by scratches etc. that occur during handling of the disc, or defects caused by mechanical fluctuations or disturbances in the playback device. Therefore, in order to detect and correct data errors, a system called a cross-linterleave Reed-Solomon code (CIRC) is used in CDs.

This method will be briefly explained. First, when recording data on a disk, six pieces of 16-bit music signal data for each of the right and left channels are divided into 8-bit symbols, creating a total of 24 symbols. After being selectively delayed and recombined, these are the parity data Q of C2 based on Reed-Solomon coding. , Q,
, Q, , Qs (8 bits each) are assigned. Furthermore, these 28 symbols are each delayed by a different time and are used as parity data P of CI. +p++p2+rs (8 bits each) can be created and added based on the Reed-Solomon coding method in the same way as the input. Then, a total of 32 symbols are selectively delayed, of which parity data Qo+Q
+.

Q, , Q, and Po, P, , P, , P,
is inverted and becomes a data group for writing, and EFM (8
-14 modulation) and recorded on the disk together with a frame synchronization signal.

Furthermore, when a disc is reproduced, 32 8-bit symbols are created from the read EFM signal, and these are processed in the opposite manner to that during recording.

That is, the 32 symbols are selectively delayed and the parity data Qo, Q, , Q, , Q, and P
O+PI+P2 TP3 is inverted and decoded into C. In the C1 decoding process, syndrome unevenness is calculated based on each symbol, and error detection and error correction are performed from the calculated syndrome according to the Reed-Solomon coding method. Furthermore, the 28 symbols that have been subjected to CI decoding are each delayed by a different time and then subjected to C2 decoding. Similarly, in the C2 code processing, a syndrome is calculated from each symbol, and error detection and error correction are performed from the calculated syndrome according to the Reed and Solomon coding methods. Then, C. The 24 symbols after decoding are rearranged, selectively delayed, and returned to the original music signal data.

Regarding the CD system using the cross-interleaved Reed-Solomon coding method, the November 25, 1981
It is described in detail on pages 103 to 110 of the ``Illustrated Compact Disc Reader'' (Ohmsha) published on the 1st.

Conventionally, when error detection is performed based on the Reed-Solomon coding method, syndromes are calculated according to the following equation.

In addition, α is an 8th order primitive polynomial% expression % As a result of the above calculation, syndrome S is obtained. , Sr, Sz, Ss
``If it is OJ, it can be determined that there is no error.''

On the other hand, if there is an error only in the first data D, then Sr”=So・S2+ Sg”=S+・53S0≠O
,S,≠0. S2≠0. By detecting that S3≠0 holds true, the determination is made.The error data position is obtained by calculating and taking the logarithm.

Also, if there is an error in data D and Dl, 0
≦j, i≦31. Since j≠i holds true, it is therefore determined that a double error occurs when j and i are determined. Furthermore, the data error E
, and El are determined.

Detection and correction of CD data errors using the above-mentioned Reed-Solomon encoding method is described in detail in Japanese Patent Application Laid-open No. 77529/1983.

(c) Problems to be Solved by the Invention However, the circuit for performing the data error detection and correction described above requires a ROM for logarithmic conversion and a large number of multiplication/division circuits, and is especially important when performing double error detection. In addition, since multiplication and division must be repeated, it takes time to detect errors and calculate error positions, and the number of timing signals required for calculations increases.

(d) Means for solving the problems The present invention has been made in view of the following two points:
Syndrome S from the input data. , Sl.

S,,S, is calculated, and the syndromes,s,,s,,
s,,s.

1. α, α2. Syndrome calculation means for dividing by α3 (α is the root of an 8th order primitive polynomial) and syndrome So.

1°α, error zero detection means that detects that So, Sa, and Ss are all “0” and syndrome calculation means.
α2. A counting means for counting and holding the number of times j divided by α8, a presetting means for setting "0" and "4" in the counting means, and a result S of the arithmetic means. ZSI'+s,',s,
'Based on So'+S+', S+'+S*'',
an addition means for calculating Sx'+Ss'; and the S. '
10S,', 5+'+5x'+S%+Ss
A simple error detection means for detecting that all ' have become 0, and dividing the above S+'+SQ' and St'+Ss' by α and α2 respectively, and calculating , i, j are error positions), error position calculation means for calculating i from j held in the counting means and the a, and an error component based on the So'+s+' and a. and error calculation means for calculating.

(f) Effect: According to the above-described means, the syndrome calculating means applies 1 to each symbol depending on the timing at which the symbols are sequentially applied. α, α2. Multiply by α3, find the sum of the multiplication result and the symbol to be applied next, and add 1 to the sum. α,
α2. By multiplying by α3, the equation (1) described above is calculated, and the syndrome S is obtained. , Sl, Sa, and Ss are determined. Calculated syndromes S0, Sl, St, Ss
If all are "0", the error zero detection circuit determines that all the read data is correct. On the other hand, if there is an error, the arithmetic means calculates the syndrome s
, s, ,s, ,s, respectively, are 1°α, α2 . Divide by α3 and add the previous calculation result to 1. α,α
2. Repeat the operation of dividing by α3. Also, each time this division is executed, the division results S, ', 51', 52'
, 5m' by the adding means. '+S+',
S+'+S*', St'+Ss' are calculated,
Furthermore, So'+S+', S+'+52', Sa
'+Ss' is applied to the single error detection means as well as to the double error detection means. Further, the number of divisions is counted and held in a counting means. That is, S
o' + Sr' = SI' + 52' = St
When '+Ss'=O is detected, it is detected that there is one data error, and the error position j can be determined from the contents of the counting means at that time. In addition, the double error detection means determines from the detection output when The error position j can be determined based on the contents of the counting means at that time. Therefore, the error position calculation means can calculate the error position i from a and j. In order to make such a detection operation the same for C8 error detection and C2 error detection, the preset means sets the counting means to "0" when detecting a CI error, and sets "4." to the counting means when detecting a CQ error. As a result, detection can be performed with the same operation even if the number of symbols to be processed is different.

(F) Embodiment First, before explaining the embodiment, data error detection according to the present invention will be explained. In the case of C1 error detection, the above (1)
Syndrome S from the symbol by the formula. .

S, , S, , S3 are calculated, but in the case of the present invention (
1) Rewrite the equation as follows.

This is symbol D in equation (1). -D! The subscript of + is reversed, and the symbol D in equation (1)' is
31 is the actual symbol glue. It is. That is, the actual symbols are Do, D, I in the order they are read from the disk.
, Do...DIl+, but in the present invention, conversely, Ds+rD3o...D.

Therefore, the so-called addresses are assigned backwards.

If there is no error in the symbols D31 to D, the syndromes So, S+, Sx, and Ss will all be 0. However, if an error occurs in the symbols D and D+ (j≦i), the syndrome will be as follows. Note that E and El are each error components.

This calculated syndrome s0. s, , s, , s, wo each 1. α, α2. When divided by α3 j times, each is 50゛.

Assuming that St', Sz', and S3' become St', Sz', and S3'. Therefore, from equation (3), So'+S+'=E+(1+α'-') −・
Group・(4) S+'+Sx'=α'-'El(1+α1-
Li... Group (5) Sx' + Ss' = α2
Day-1) E, (1+α+-j>, .-=<6> is obtained.

Here, in the case of a single error, assuming that i=j, E, = 0, equations (4), (5), and (6) become So'10SI'-51'152'=52'+S3'=o
......(7). Therefore, a single error can be detected by detecting that equation (7) holds true. The error position is indicated by the number j of times the syndromes So, S+, Sg, and Ss are divided, and the error component E is the syndrome S
. The value is .

On the other hand, in the case of a double error, equations (4), (5), and (6) can be used. If 1−j=a in equation (8), then i and j are both 0 to 31, so 1≦a≦31. Therefore, S+'+S,', St'+Ss' are each α.

A double error can be detected when equation (8) is established when divided by α2 a times. Further, it can be determined from the error position number a + j. Furthermore, the error component E.

can be obtained from equation (4). In equation (9), 1+αI-1 can be converted to α1 in the Galois field, and E+ is obtained by converting the above a to α', and then s.

= E, + E, and is determined by EI=So-E.

Single error correction is done by adding error component E to the symbol at detected error position j, and double error correction is done by adding error component E to the symbol at detected error positions i and j.
, and El, respectively.

FIG. 1 is a block diagram showing an embodiment of the present invention that implements the above-described error detection. In Figure 1, RAM (1
) is read from the disk and the symbols 00 to DIll (the subscript indicates the actual address order) of each EFM-converted frame are written in a predetermined order by an address control circuit (not shown), Also, CI and c
This is a memory that is read and written during error detection and correction (2) and when outputting to DA conversion, and is connected to an 8-bit data bus (2). The syndrome calculation means (3), (4), (5), and (6) each have a data bus (2).
Input the symbols D31 to D (the subscript is the reverse address of the actual address, and the reverse address will be used below) that are connected to the RAM (1) and read out sequentially from the RAM (1), and perform ``Syndrome S was calculated by calculating the formula. ,S, ,S, ,S, are each 1. α, α2. α3
, to calculate s, ', s, ', s, ', s, '. In addition, syndrome calculation means (3)
(4)(5)(6) is the symbol D from RAM(1),
It operates with a clock pulse 5CLK generated by a timing signal SYRAM for reading I-D0 and a timing signal 5YNDCL for executing division, and switching between syndrome calculation and division is performed by a control signal 5CONT. The addition means (7), (8), and (9) are respectively synchronized with the syndrome calculation means (3).
)(4)(5)(6) outputs So', S+', S2',
Input Ss', So'+S+', S+'+ St'
, Sx' + Ss', and performs a modulus 2 sum by E-OR of each bit. Addition means (7
), (8), and (9) are applied to an error detection means (10), a single error detection means (11), and a double error detection means (12). Zero error detection means (1
0) is the syndrome Sfi, S1. S2. At the time of calculating S, 50=0, and So
When it is detected that 1=S1+Sx=Sa+Ss=O, it is determined that the symbols D$1 to Do are correct and free of errors, and a signal ZE is output. On the other hand, the simple error detection means (11) has a syndrome calculation means (3) (4).
) (5) Syndrome S calculated in (6). ,S+,
S2. Ss 1. α, α2. Each time you divide by α3, (7
) is established, and when the equation (7) is established, it is determined that there is a single error in the symbol and a detection output IE is output. The double error detection means (12) includes syndrome calculation means (3) (4) (5) (6) as described above.
), it detects that the formula (8> holds true), and the division result and S.'+51'
By detecting a match, it is possible to determine that there is an error and to obtain error location information a=ij. Then, the double error detection means (12) outputs 32 detection outputs a1-1 indicating the error position information a. That is, the symbol Ds+”
Do Nori.

If there is an error in the equations (3) to (8), syndrome S occurs. , Sl, S2. S
l is 1°α7α2. When divided by C3 j times, only one of the 32 detection outputs a, -1 becomes "1". However, if there is a triple error or more, the detection output aI-, will be sent multiple times while the syndrome calculation means (3), (4), (5), and (6) performs 31 divisions. A detection output appears. The detection outputs a1-4 are applied to the a register (13) consisting of a 32-bit D-FF.

(when i=j) is applied to the OR gate (14), and the output of the OR gate (14) is output as the error detection output 2E. The counting means (15) counts the timing signal 5YNDCL that causes the syndrome calculation means (3) (4) (5) (6) to execute division of 1.α, α2.α3, and calculates the number of times the division has been performed. A 5-bit counter (
16), and a register (17) consisting of a 5-bit D-FF to which the output of the counter (16) is applied and stores the counted contents. The preset means (55) is configured to set timing T2 and clear pulse 5I at the time of C4 error detection.
It consists of an AND gate (53) to which NT is applied, and an AND gate (54) to which timing T4 and clear pulse 5INT are applied at the time of C2 error detection. 4" in the counter (). The latch pulse generating means (18) is applied with the detection output IE from the single error detection means (11) and the detection output 2E output from the double error detection means (12) via the OR gate (14), Each detection output IE and 2E
Based on
Output from (19). Further, the pulse jLP is transmitted to a register (20) consisting of an 8-bit D-FF that stores and holds the output 50' of the syndrome calculation means (3), and a detection output a.
, -4, and a register (21) consisting of an 8-bit I)-FF that stores So'+S1'. Furthermore, the latch pulse output from the latch pulse generating means (18) based on the detection output 2E is applied to the uncorrectable determining means (22). The uncorrectable determining means (22) determines that there is a double error when the number of applied latch pulses is one, and instructs the correction control means (23) to perform correction, and also instructs the flag control means (24) to set C1. Alternatively, it outputs a control signal 2ESIG that instructs the addition of the C2 flag, and if two or more latch pulses are applied, it is determined that there is a triple error or more, and the correction control means (23) prohibits correction. Instruct C1 or C2 to the flag control means (24).
A control signal NG instructing to add a flag to the flag register (25) is output. The detection output ZE from the error zero detection means (10) is applied to the latch pulse generation means (18), the uncorrectable determination means (22), and the correction control means (23), and when it is detected that there is no error, , these operations are prohibited. The encoder (
26> converts the 32 signals into 5-bit binary data, and the converted 5-bit data is applied to the error position calculation means (27). The error position calculation means (27) calculates the data held in the register 7) of the counting means (15), that is, the syndromes S o , S +
, S t , S s as 1, α, α2. This is an addition circuit that adds the number of times j divided by α3 and the 5-bit data of ij to calculate the error position i. Error position calculation means (27
) and the output j of the register (17) are both inverted by inverters (28) and (29), selected by a multiplexer (30), and supplied to the address control circuit of the RAM (1). That is, error positions i and j are
It can be used to specify the address of a symbol where an error has occurred and to correct the symbol. Here, the data i and j are inverted by the inverters (28) and (29), as described above, for the symbols D0 to D! This is to restore the original address since the address of 1 was assigned in reverse.

The error calculation means (31) inputs So"S1' stored in the register (21>) and the error position information a1-3 stored in the a register (13), and calculates the error position i based on equation (9). The error component E of the symbol is calculated, and 1
A decoder method is used to convert +αl−j to α°,
Calculations are simplified. The addition means (32) calculates the sum of the error components E and E, S' (equal to the syndrome S), and the error component E1 calculated by the error calculation means (31).
This is to find the modulus 2 sum of E for each bit.
- Find the error component E by OR. The calculated error components E and E are respectively applied to the multiplexer (33) and selectively output by the same control signal SEL as the multiplexer (33). That is, the multiplexer (30)
In this case, when the error position data i is selected and output, the multiplexer (33) outputs the error component E1, and when the error position data j is selected, the error component E is output.
, is selected. An adder (34) to which the output of the multiplexer (33) is applied and a register (35) consisting of an 8-bit D-FF perform error correction, and are selected from the multiplexer (30) and sent to the address control circuit. RAM (
The error symbol D, or, read from 1) is held in the register (35), and in the adding means (34), the error symbol D, or, and the error component E, or E, are modulated. The addition result, that is, the corrected symbol, is stored again at the same address in the RAM (1).The operation of the addition means (34) is controlled by the correction control means (23>). Controlled by the output control signal ENA, no addition operation is performed in the case of no error and uncorrectable error, but the addition operation is completed in the case of single error and double error.

The error detection and correction circuit described above is a circuit used for both CI error detection and correction and C2 error detection and correction, but in the case of C2 error detection and correction, the number of symbols is ~D27 Therefore, the syndrome calculation means (3), (4), (5), and (6>) calculates the syndrome S.
. The number of timings for calculating ,S,,S,,S3 is 28.
1. α, α2. The number of times divided by α3 is 2
It will be 7 times. Therefore, during the period of C2 error detection and correction, the counter (16) is first reset to 4J. Details of this point will be described later.

Next, main specific examples of the circuit shown in FIG. 1 will be explained below.

Figure 2 shows the syndrome calculation means (3) (4) < 5) (
6), in which the E-OR gate (36) to which each bit b0 to b7 of the symbol sent to the data bus (2) is applied, and the output of the E-OR gate (36) It consists of eight D-FFs (37) applied and a multiplexer (40) that selects the D-F output and applies it to each input of the E-OR gate (36). D-F
F (37) operates with the clock pulse 5CLK generated by the timing signal SYRAM and the timing signal 5YNDCL mentioned above, and the multiplexer (40) calculates the syndromes S o , S I , S 2 , S s and 1.α.

α2. It is controlled by a control signal 5CONT that switches between the division of α3 and the division of α3. That is, syndrome S. , S , ,
S.

, S3, the α° arithmetic element (38) is used, and when calculating s,', s,', s2', s,' by division, the syndrome arithmetic means (3) Then, as is clear from equation (1)', the syndrome 56 is the sum of the symbols Ds+""Do, and So' is S
, divided by "1", so the arithmetic element (38)
is α0, and in the case of the calculation means (3), the calculation element (
38) (39> and multiplexer <40) are unnecessary, and each output Q0 to Q7 of D-FF (37) is
It is sufficient to directly apply it to the R gate (36>). Therefore, by the timing signal SVRAM that sequentially reads symbols D31 to D0 from the RAM (1), the first read symbol D31 is input to the D-F F (37>). , the next read symbol D, is the output of the D-FF (37), that is, is subjected to modulus 2 addition processing by D31 and the E-OR gate (36), and is held in the D-FF (37). By repeating this operation 32 times (until Do is read from D31), when symbol D0 is read out, the output of D-FF (37) becomes syndrome S0.

In addition, the syndrome calculation means (4) has a calculation element (3
8) is α, and the arithmetic element (39〉) is -.The α arithmetic element (38) has inputs 10 to I7 and outputs 00 to 07 connected as shown in Fig. 3 (a>). It is equipped with three E-OR gates (41), and the forces 10 to 7 are connected to the outputs 0° to 07.
E-OR gates (42) are provided.

Therefore, in the syndrome calculating means (4), the symbol D31 that was first read out from the RAM (1) and stored in the D-FF (37) according to the timing signal SVRAM is
As the multiplication result of αD3I by α operation element (38), E
- is applied to the OR gate (36) and then the symbol Dao
When is read out, αD31+Dso is added in the E-OR gate (36), and the result is D
- Stored in FF (37). By repeating this operation 32 times, the syndrome S shown in equation (1)' is obtained.
, is calculated, and outputs 00 to Q of D-FF (37).

This is the input to the E-OR gate (36). −b, “0゛′
Each time one timing signal 5YNDCL is applied in the state of 23=, the syndrome held in D-FF (37) is
31 timing signals 5YNDCL can be calculated sequentially.

Furthermore, the arithmetic element (38) of the syndrome arithmetic means (5)
The α2 operation element (38) is an element having the input/output relationship shown in FIG. 3(C), and is a two-stage series connection of the α operation elements shown in FIG. 3(a). On the other hand, two stages of children are connected in series. Further, the arithmetic element (38) of the syndrome arithmetic means (6) is α3, and is shown in FIG.
) are connected in series in three stages.

Both syndrome calculation means (5) and (6) calculate the syndromes S and S3 of equation (1) using the timing signal SVRAM in the same manner as described above, and the timing signal S in FIG. FIG. 12 is a block diagram showing the configuration of (12). The double error detection means (12) includes 31 conventionally connected arithmetic elements (43) and 31 conventionally connected arithmetic elements (43) (4).
4> and the output S from the addition means (7). '+5. '
is applied to the coincidence detection circuit (45), and s, '+s,' is applied to one arithmetic element (43) of the first stage,
This is the first element. In addition, the - number construction circuit (45), as shown in FIG. 46), the E-OR gate (47) marked with each bit of So"S1', and the E-OR gate (4
NOR game) (4) to which the outputs of (6) and (47) are applied
8>, and it is detected that equation (8) holds true.

That is, the output a of the coincidence detection circuit (45) provided at the first stage is "1" when 1-j=1, and 2
The output a of the coincidence detection circuit <45) provided in the second stage is:
The output is “1” when 1−j=2, and similarly, 31
"1" is sequentially output corresponding to the value of i-j up to the output as+ of the stage.
′′. Therefore, syndrome calculation means (3) (4
) (5) (6) 1. α, α2. Every time a division is executed by α3, the double error detection means (12) calculates (8
) is determined whether the formula holds true or not, and if there is a double error,
When the result of the j-th division is determined, any one of a1 to aS+ becomes "1", whereby double error detection and error position information i-j are obtained. In addition, - Numerical detection circuit (45
') detects 1-j=0, and outputs 1'' when there is a single error.

FIG. 6 is a circuit diagram of the error calculation means (31). , s0'+s,' from the lower bit of the 8-bit data A
.

B, C, . . . G, H) are selectively added, and each bit of the error component E1 is
7 (total of 8 bits). As mentioned above, the error calculation means (31) calculates the formula (9), and in this case, 1+α1
-1 can be converted to α', and ROM (49) is
It converts from 1+αI-1 to α'' and determines the configuration of each bit of the result when 8-bit data is divided by C1.For example, when 1-j=1, 10α is α25 Each bit of the error component E+ written as a result of dividing SO "51" by α26 is E + -t =
A + B + C + D + E + F + G
10HE+-s = A 10B 10C1D + E +
F 10GE+-a=A+B 10c+E1F E, -□=A+B+C+D+E El-s= E 10F + G 10H E+-*= A 10B 10G El-1=c+D+E+F+G+H E, -0= B ten C + D ten E ten F ten G + H. Therefore, each El-7 to E+=. Selective addition circuit (50
) is the ROM (49) in the AND gate (51).
), the 8-bit data A-H of S0'+S,'' is selected, and the E-OR gate (52
), the error component E1 can be obtained in real time by applying the detection outputs a, to as+, without performing actual division.

Next, the operation of C4 and C8 error detection and correction using the circuit shown in FIG. 1 will be briefly explained with reference to FIG.

As shown in FIG. 7, the processing period for one frame is 1, -T.
6 timings and t constituting each of T, -T,. ~t
It consists of 49 timings of 4a. C1 error detection and correction is performed at timings ①1 to T, and C8 error detection and correction is performed at timings T4 to T. First, the syndrome calculation means (3) (
4)<5)(6) and the D-FF etc. of each part are reset. This timing T+ is the timing at which the syndromes So, 51.52, and S3 are calculated by sequentially reading out the 32 symbols D31 to D stored in the RAM (1>). SVRAM is distributed so that 32 timing signals SYRAM are generated. Therefore, when the 32nd timing signal SYRAM is generated, the calculation of syndromes S0.S+, St, and Ss is completed. Next, at timing T, error detection is performed. This is the timing to perform the timing signal 5YND.
The distribution is such that 32 CLs occur. Also, timing t of timing T. The clear pulse 5INT generated at the AND gate (
53) is generated and the counter (16) is preset to "0". Therefore, every time the timing signal 5YNDCL is generated, the counter (16) counts up and the syndrome calculation means (3) (4) (5) (6)
) in 1. α, α2. One division of α3 is executed,
Based on the results, single error detection and double error detection can be performed. When 32 timing signals 5YNDCL have been generated, if there is a single error or double error, one of the error positions j is held in the register (17), and the syndromes So, S+, Ss, 5s to 1. α,α
2. Data S when divided by α3 j times. ' is in the register (20), So'S+' is in the register (21), and
Double error detection results a1~. I is held in the a register (13). Furthermore, no error, single error, double error,
Alternatively, if the detection result is uncorrectable, the correction control means (23)
and is instructed to the uncorrectability determining means (22). Timing T3 is the timing for executing correction;
The timing of selecting the error position i by the control signal SEL and reading out the symbol D1 at that address during the timing of , and the timing of writing the symbol prisoner corrected by the adding means (34) again to the same address of the RAM (1). Similarly, there are read and write timings for correcting the error position j. Therefore,
At timing T3, the above-described processing is performed based on the data held in registers (13), (20), and (21) at timing T, and correction is performed using the results.

For C2 error detection and correction, the symbol of interest is I
) 27 to D. Therefore, timing T4
In , symbols I) a7 to D0 are read out for syndrome S. There are 28 timing signals SYRAM for calculating ,S,,S,,S,. timing t. The clear pulse 5INT generated at 5INT clears all data held during CI error detection and correction, and thereafter, the syndromes So, S+, Sz, and Ss of C2 are obtained by the 28 timing signals SYRAM.

At timing T6, when clear pulse 5INT is generated at timing t0, the AND gate (54) in FIG.
The counter (16) is preset to 14 by the output.

Here, the meaning of presetting "r4" will be explained. As mentioned above, address 0123 is in RAM (1).
・・・・・・・・・3031 symbol D. D.I.
Di Di......D. [)S+i,j
Value of 31 30 29 28・・・・・・・・・10
Addresses are assigned in the order of symbols read from the disk. However, as in equation (1), the exponent of α by which symbols D0 to D31 are multiplied is opposite to the address, and i and j determined by the circuit of FIG. 1 are opposite to the actual address. Therefore, as shown in FIG.
and 5-bit binary data representing j (2'=3
2) using inverters (28) and (29), the actual address can be obtained. However, in the case of C2 error detection and correction, the symbols to be processed are symbols from addresses 0 to 27, so the possible values of i and j are O to 27. Therefore, if the numerical values of i and j are inverted as they are, they will deviate by r4 degrees from the actual address, so "4" must be added before inversion. In other words, an addition circuit that adds "4" is required, but
If the counter (16) that counts j is preset to ``4'' in advance, the addition circuit is unnecessary and the same circuit can be used.

r4 on the counter (16). After the timing signal 5YNDCL is preset, the timing signal 5YNDCL is generated during the timing signal.
are 28, and this signal causes the above-mentioned timing T
Error detection of C2 is performed by the same operation as in 2.

Then, at timing T6, error correction of C1 is performed by the same operation as at timing T.

(g) Effects of the Invention As described above, according to the present invention, the timing signal and the syndrome S are used to read symbols from the RAM and calculate the syndrome. ,S,,S,,S,1. α.

Since error detection can be achieved using timing signals divided by C2 and C3, the number of timing signals required for calculations is reduced. Further, there is no need for a ROM for logarithmic conversion or the like for directly performing error detection calculations, which has the advantage of simplifying the circuit configuration and reducing the number of elements.

Furthermore, it also has the advantage of increasing error detection speed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing a specific configuration of the syndrome calculation means shown in FIG. 1, FIG. 1 is a concrete block diagram of the double error detection means shown in FIG. 1, FIG. 5 is a circuit diagram of the -numerical calculation circuit shown in FIG. 7 are timing diagrams showing the operation of the embodiment of FIG. 1. (1)...RAM, (2)...data bus,
(3)(4)(5)(6)...Syndrome calculation means, (7)(8)(9)...Addition means, (10)
...zero error detection means, (11)...single error detection means, ri12)...double error detection means, (13)
...a register, (15) ...counting means, (18
)... Latch pulse generating means, (20) (21)...
・Register, (22)...Uncorrectable determination means, (23
)...correction control means, (26)...encoder,
(27)...Error position calculation means, (30)(33).
... multiplexer, (28) (29) ... inverter, (31) ... error calculation means, (55) ...
・Preset means. Applicant Sanyo Electric Co., Ltd. and one other agent Patent attorney Kuratsugu Nishino and one other person Figure 2 1n Figure 3 ■. I, 17 S.E. Esche & I. koI + z ko, 14r, ■, ko.

Claims (1)

[Claims] 1. In a data error detection circuit that detects data errors based on Reed-Solomon codes, syndromes S_0, S_1, S_2, and S_3 are calculated from input data, and the syndromes S_0, S_1, S_2, and Syndrome calculation means that divides S_3 by 1, α, α^2, α^3 (α is the root of an 8th degree primitive polynomial), and the syndromes S_0, S_1, S_2, and S_3 are all "0".
”, a counting means for counting and holding the number of times j divided by 1, α, α^2, and α^3 by the syndrome calculation means, and a count means for counting and holding the number j of divisions by 1, α, α^2, α^3, and a value “4” for the counting means.
and a preset means for setting "0" to "0", and S_
0'+S_1', S_1'+S_2', S_2+S_3
an addition means for calculating S_0′+S_1′, S_
1'+S_2' and S_2'+S_3' are all "0";
'+S_2' and S_2'+S_3' are divided by α and α^2, respectively, and S_0'+S_1'=(S_1'+S_2'
)/α^a=(S_2+S_3')/α^2^a, double error detection means detects a (a=i-j, i, j are error positions), and the counting means an error position calculation means for calculating i from the held j and the a; and the S_0
'+S_1' and error calculation means for calculating an error component based on a, and the presetting means sets the counting means to "0" when a C_1 error is detected and to "4" when a C_2 error is detected. A data error detection circuit characterized by: