JPS63217621A - Method for making temperature hysteresis between wafers uniform in oxidlzation and diffusion device - Google Patents

Abstract

PURPOSE:To make the dispersion of junction depth uniform between wafers by means of time-controlling the reaction tube wall temperature profile of an oxidation and diffusion device. CONSTITUTION:The gradient of tube wall temperature profile from inlet side to inner side of a reaction tube 5 set up in case of insertion into an oxidation and diffusion device fills the role of inversing the temperature of wafers at front end and rear end of wafer lines so that the dispersion of junction depth Xj between wafers 10 may be reduced. Furthermore, a simulation model corresponding to the transient status of wafer temperatures can infer the wafer temperature hysteresis corresponding to the time elapsing changes of the reaction tube wall temperature profine to preliminarily estimate the extent of inversed temperature period to be maintained. Then, the time control signals of tube wall temperature profile based on the results of estimation are transmitted to a CPU 11 of thermostat 2 of the oxidizing and diffusing device. Through these procedures, the dispersion of junction depth Xj between wafers can be minimized.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a process involving high-temperature heat treatment in a semiconductor manufacturing process, and in particular, to reduce the bonding depth between wafers due to variations in wafer temperature history during insertion and withdrawal of wafer rows. The present invention relates to a method for uniformizing temperature history among wafers in an oxidation/diffusion device suitable for reducing variations.

[Conventional technology]

The conventional device is published in Electronic Materials, March 1985, pp92-97.
As described in , no control device is provided for controlling the transient temperature history of the wafer temperature during insertion and withdrawal of wafer rows.

[Problem that the invention seeks to solve]

The above conventional technology does not take into account variations in wafer temperature during the transient state of wafer temperature when inserting and extracting rows of wafers from oxidation/diffusion equipment, and as elements become smaller, bonding due to variations in temperature history The variation in depth X between wafers has become impossible to ignore, and a problem has arisen that reduces semiconductor device manufacturing yield.

An object of the present invention is to equalize the variation in the junction depth Xl between wafers by controlling the temperature profile of the reaction tube wall of the oxidation/diffusion device over time.

[Means for solving problems]

The above purpose is to lower the temperature profile of the wall of one reaction tube by about 50°C on the tube nest side, that is, the temperature at the tip of the wafer row when inserting the wafer row into the oxidation/diffusion device, and to lower the temperature profile of the wafer row inside the reaction tube by about 50°C. As the wafer progresses, by gradually increasing the temperature at the rear end of the wafer process, that is, at the entrance of the reaction tube, the wafer temperatures at the leading and rear ends of the wafer row are reversed, and the wafer row that inevitably occurs during insertion is reversed. By controlling the time delay of the wafer temperature from the leading edge side to the trailing edge side of the wafer, the bonding depth between the wafers can be made uniform by controlling the temperature history time that is reversed between the wafer rows.

The temperature history time reversed between wafer rows is controlled in advance by varying the time required to return the tube wall temperature profile that has decreased at the back of the reaction tube to a uniform profile using a physical model for wafer temperature transient characteristic analysis. The wafer temperature transition is determined by simulation when the temperature is changed, and each process condition (wafer spacing, insertion speed, tube wall soaking zone temperature, etc.) is determined.
According to
Just give it to the controller.

[Effect]

The slope of the tube wall temperature profile from the reaction tube inlet side to the back side, which was set when the wafer row was inserted into the oxidation/diffusion equipment, is now set so that the wafer temperature at the front end of the wafer row and the wafer temperature at the rear end are reversed. By acting on the junction depth X between the wafers.

Reduce the variation in In addition, this simulation model for the transient state of the wafer temperature in the first step can estimate the wafer temperature history according to the time change of the reaction tube wall temperature profile, so it is possible to estimate how long the above-mentioned temperature reversal period should be maintained. It can be evaluated in advance, and if a time control signal of the tube wall temperature profile is sent to the CPU of the temperature controller of the oxidation/diffusion device based on the evaluation result, it is possible to minimize the variation in the junction depth xl between wafers.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 shows the overall configuration of a semiconductor manufacturing process to which the present invention is applied, and the axial temperature profile of one reaction tube 5 is controlled by a temperature controller 2 in three zones. The wafers 10 arranged on the jig 9 are inserted into the reaction tube 5 by the automatic insertion/drawing device 6, the required gas is supplied into the reaction tube 5 by the doping system 1, and the wafers 10 are subjected to high-temperature heat treatment. 1 to the outside of the reaction tube 5. Here 1 reaction tube 5
Heating is realized by on/off control of the heater current of the heating element 3 wound around the furnace core tube 4 for contamination prevention by the temperature controller 2, and its axial temperature profile is determined by the thermocouple from the temperature measuring part 7. 3 by the temperature controller 2 through the central processing unit (CPU) 11.
It is a zone-divided system, and the set value is maintained by on/off control of the heater current in each zone.

Now, 1. Under the normal reaction tube wall temperature profile, the third
The wafer temperature changes as shown in the figure. For example, in the case of a row of 31 wafers, the trailing wafer ($31) has a large transient time delay compared to the leading wafer (#1), and the bonding depth The time delay is also noticeable in the high temperature region that affects the fluctuation of Xj. For example, if the junction depth X- changes in a temperature range of 800° C. or higher, the tip wafer (#1) changes by the amount shown by the shaded area compared to the end wafer (#31). In other words, the joining depth Xj is Mengo (
D is a diffusion coefficient and has a large temperature dependence, and t represents time), so the temperature between the tip wafer and the end wafer is /? The change in history (shaded area) has a correlation with J'57 and causes a change in activity and junction depth Xj. This effect similarly occurs when pulling out a wafer row. Therefore, the variation in the bonding depth X between the wafers caused by the difference in the temperature history M between the leading wafer and the trailing wafer is corrected by the inter-wafer temperature history correction device 12 shown in FIG.

Figure 4 shows its configuration. below.

The details will be explained with reference to the flowchart shown in FIG.

First, in block 200, process conditions (wafer spacing, insertion speed, tube wall temperature, etc.) for inserting a row of wafers into the oxidation/diffusion device are set. Next, in accordance with this condition, in block 201, as the wafer row is inserted into the reaction tube, the wafer temperature at the rear end of the wafer row becomes higher than that at the front end.

The tube wall temperature profile data is set as shown in FIG. Specifically, the wafer row is located at the reaction tube position Z^*Z
B, Zc+ As you advance to Zo, the tube center temperature set value TF
L to TFL8r TFLB? TFLC? TPLD, the pipe center temperature set value TFCI and the pipe center temperature set value TFR are set 25°C and 50°C lower than the normal soaking zone temperature TF, and the
Tilting the axial temperature profile of the W wall temperature.

Next, in block 202, a time t for starting recovery of the tube wall temperature profile to the normal state is set, and in block 203, a wafer-to-wafer temperature transition simulation is executed using a wafer temperature transient analysis model under the above conditions. Regarding the content of the model, see Theory of Faith (C), Vo168 (C) & 6
It is detailed in pp 425-432. An example of the results of this simulation is shown in FIG. As simulation conditions, using the tube wall temperature profile shown in Fig. 5, 31 wafers arranged at 9.2 W intervals were inserted at an insertion speed of 201/min, and at the same time as the insertion was completed, the tube wall temperature in the normal state This is when you return to your profile.

For comparison, FIG. 6 also shows the wafer temperature transition results for the conventional method. As can be seen from the figure, when the tube wall temperature profile is controlled as described above according to the present invention, the temperature of the wafer at the tip of the wafer row (third wafer from the tip: #3) is lower than that of the wafer at the rear edge (#3). The temperature of the 29th wafer from the tip (#29) is reversed just before the end of the wafer row insertion, and after that, while maintaining this reversed state, the surface temperature gradually approaches the set value of the tube wall temperature in the normal state. .

As a result, the difference in temperature history before the temperature reversal of both wafers (shaded area on the left) and the difference in the temperature history after the reversal (shaded area on the right) act to cancel out the variation in bonding depth Xj between wafers. .

In block 204, uniformity evaluation of the junction depths X between wafers is performed, and in block 205, the result σ of l'lII times of the variation σ(X'') in the junction depths is evaluated. (Xj
). The processes of blocks 202 to 205 are repeated, and in block 206, the time t at which the temperature of the 94ft IIIA degree profile starts to recover to the normal state when the variation is minimized is determined.

Next, in block 207, this time t and the previously set tube wall temperature profile data are transferred to the CPU II of the temperature controller 2 of the oxidation/diffusion device.

According to this embodiment, the variation in bonding depth Xj between wafers that occurs when a row of wafers is inserted into an oxidation/diffusion device is minimized by controlling the temperature history between wafers through time control of the tube wall temperature profile. There is an effect that can be done.

〔Effect of the invention〕

According to the present invention, in an oxidation/diffusion device that performs high-temperature heat treatment such as oxidation/diffusion and annealing in a semiconductor manufacturing process in a batch manner, the bonding depth may be reduced due to variations in transient wafer temperature history that occur when inserting/extracting wafer rows. The variation in Xj between wafers can be reduced by time control of the reaction tube wall temperature profile to make the bonding depth Xj uniform between wafers, which has the effect of increasing the manufacturing yield of semiconductor devices.

[Brief explanation of the drawing]

Fig. 1 is a flowchart showing an embodiment of the present invention, Fig. 2 is an overall configuration diagram, Fig. 3 is a diagram of temperature changes between wafers in a normal method, and Fig. 4 is a configuration of an inter-wafer temperature history force generation device. 5 shows a tube wall temperature profile control diagram, and FIG. 6 shows an equalization control result diagram of inter-wafer temperature history. 1... Doping system, 2... Temperature controller, 3...
... Heating element, 4... Furnace tube, 5... Reaction tube, 6...
・Automatic insertion/extraction device, 7...Temperature measurement section, 9...
Jig, 10...Wafer, 11...CPU, 12...Wafer temperature, history equalization device, 100...Tube wall temperature profile time control signal. Fig. 7 ze 0 ξ grass 4 Fig.

Claims (1)

[Scope of Claims] 1. In an oxidation/diffusion method in which high-temperature heat treatment in a semiconductor manufacturing process is performed in a batch manner, time control of the reaction tube wall temperature profile is used to reduce the bonding depth between wafers of X_j due to variations in the transient state of the wafer temperature. A method for equalizing temperature history between wafers in an oxidation/diffusion device, characterized by equalizing variations in temperature between wafers. 2. The above-mentioned time control of the reaction tube wall temperature profile involves a process in which the wafer temperature transient characteristics in accordance with changes in the reaction tube wall temperature profile are determined in advance by simulation using a physical model for wafer temperature estimation, and the temperature history results of each wafer. A process of controlling the temperature reversal time of the leading wafer and the trailing wafer of the wafer row using 1. A method for equalizing temperature history between wafers in an oxidation/diffusion apparatus according to item 1.