JPS59175719A - Heat-treatment of semiconductor device - Google Patents

Heat-treatment of semiconductor device

Info

Publication number
JPS59175719A
JPS59175719A JP5084383A JP5084383A JPS59175719A JP S59175719 A JPS59175719 A JP S59175719A JP 5084383 A JP5084383 A JP 5084383A JP 5084383 A JP5084383 A JP 5084383A JP S59175719 A JPS59175719 A JP S59175719A
Authority
JP
Japan
Prior art keywords
temperature
furnace
heat treatment
boat
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5084383A
Other languages
Japanese (ja)
Inventor
Tadashi Hirao
正 平尾
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP5084383A priority Critical patent/JPS59175719A/en
Publication of JPS59175719A publication Critical patent/JPS59175719A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005Apparatus not specifically provided for elsewhere
    • H01L21/67242Apparatus for monitoring, sorting or marking
    • H01L21/67248Temperature monitoring

Abstract

PURPOSE:To protect semiconductor substrates on a boat in a furnace from being heated excessively or insufficiently according to their position by controlling the desired heat-treatment temperature when the semiconductor substrates are inserted into the furnace. CONSTITUTION:When semiconductor substrates 5 begin entering into a furnace, the set- point temperature at an entrance 6 of the furnace is ascended to be higher than the desired treatment temperature. Although the temperature of the furnace begins descending due to the cooling effect, because the difference between the furnace temperature and the set-point temperature becomes large in a short time, the maximum electric power for heating the zone of the furnace is applied quickly to prevent the furnace temperature from descending. Even if the furnace temperature begins ascending from the lowest, because the difference between the furnace, temperature and the set-point temperature is sufficient, the heating electric power, large enough to recover the furnace temperature quickly, is applied. With this constitution, the temperature of the semiconductor substrates entering into the entrance 6 of the furnace becomes nearly the same as the determined temperature when the boat 4 enters into the furnace completely. On the other hand, the temperature of the substrates 5 enter into the innermost recess of the furnace 3 reaches the determined temperature faster but large over- shooting are avoided.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は半導体装置の製造時における半導体装置の熱処
理方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method of heat treatment of a semiconductor device during manufacture of the semiconductor device.

〔従来技術〕[Prior art]

第1図は一般的に使用される半導体装置の熱処理におけ
る炉の構成図である。図において、(1)は加熱用ヒー
タであって−1とのヒータ(1)は3ゾーン(I) 、
 (II) 、 ICに分れ、それぞれ炉温測定用の熱
電対(2)が設けられ、各ゾーンの炉温’rc5’rc
rr、 ’rcmが測定されるようになっている。(3
)は石英やSiC等で作られた炉、(4)は半導体基体
(5)を載せるボートであって、炉入口(6)から半導
体基体(5)が載せられたボート(4)が挿入又は取出
しされるようになっている。
FIG. 1 is a block diagram of a commonly used furnace for heat treatment of semiconductor devices. In the figure, (1) is a heater for heating, and the heater (1) with -1 is a 3-zone (I),
(II), each IC is equipped with a thermocouple (2) for measuring the furnace temperature, and the furnace temperature 'rc5'rc of each zone is
rr, 'rcm are to be measured. (3
) is a furnace made of quartz, SiC, etc., and (4) is a boat on which the semiconductor substrate (5) is placed, and the boat (4) on which the semiconductor substrate (5) is placed is inserted or inserted from the furnace entrance (6). It is ready to be taken out.

又、Tl)I 、TpU、 Tpmは前記3ゾーン(I
)、ω)。
In addition, Tl)I, TpU, and Tpm are the three zones (I).
), ω).

1)に対応した半導体基体(5)の温度を示している。The temperature of the semiconductor substrate (5) corresponding to 1) is shown.

第2図は従来の熱処理方法による半導体基体(5)の熱
履歴を示している。目的熱処理温度Tsに対して奥側の
半導体基体(5)の温度Tplrlはほぼ期待通シの熱
処理を受けるが、入口側の半導体基体(5)の温度Tp
IはTsに到達するのに時間がかかり、第2図のような
短時間の熱処理の場合はTsに到達後すぐに半導体基体
(5)を炉(3)から取シ出すことになり、十分な熱処
理が行なわれない。
FIG. 2 shows the thermal history of the semiconductor substrate (5) by a conventional heat treatment method. The temperature Tplrl of the semiconductor substrate (5) on the back side undergoes almost the expected heat treatment with respect to the target heat treatment temperature Ts, but the temperature Tp of the semiconductor substrate (5) on the entrance side
It takes time for I to reach Ts, and in the case of short-time heat treatment as shown in Fig. 2, the semiconductor substrate (5) must be taken out of the furnace (3) immediately after reaching Ts, and the proper heat treatment is not performed.

第3図はこのような原因を説明するだめの図であって、
炉温TCT 、 Tcmとヒータ(1)の加熱電力(P
)が時間経過により変化する様子を示している。ボー 
l−(4)が炉(3)に入るにしたがって炉入口(6)
ではボー ) (4)と半導体基体(5)によって温度
は下がる。ある程度温度が下った(TS−TCがある温
度値よシ大きくなる)ところで始めてヒータ(1)への
加熱電力が大きくなって炉温の低下部分を補正するよう
になる。しかし、炉入口手前ではボート(4)が入シ切
るまでほぼ室温のボート(4)と半導体基体(5)が順
次通過して炉(3)が冷却されるため、炉温TCIが上
昇し始めるのはボート(4)がほとんど入った時期とな
る。
Figure 3 is a diagram to explain this kind of cause.
Furnace temperature TCT, Tcm and heating power (P) of heater (1)
) shows how it changes over time. baud
Furnace inlet (6) as l-(4) enters furnace (3)
Then, the temperature decreases due to Bo (4) and the semiconductor substrate (5). Only when the temperature drops to a certain degree (TS-TC becomes larger than a certain temperature value) does the heating power to the heater (1) increase to compensate for the drop in the furnace temperature. However, in front of the furnace entrance, the furnace (3) is cooled by passing the boat (4), which is at about room temperature, and the semiconductor substrate (5) one after another until the boat (4) enters, and the furnace temperature TCI begins to rise. This is the time when most of the boats (4) have entered.

したがって、ヒータ(1)への加熱電力が最大となるま
での時間がある程度かかる。一方炉温TcIが上昇し始
めるとTsよりも低温であっても加熱電力は最大になら
ず順次小さくなっていく。ここで、ヒータ(1)への加
熱電力のかけ方を制御する定数を変更してTs−Tcが
小さい値でも加熱電力が最大かかるようにする(リニア
及びディファレンシャルゲインを大きくする)。一方、
温度上昇し始めてもTs−Tcならば加熱電力が最大か
かるようにする(インテグラルゲインを小さくする)こ
とで炉(3)のりカバリ−は良くなるが、第3図T。I
に示すようなオーバーシュートが激しくなるとともに均
一温度を保持することすら困難になってくる。
Therefore, it takes some time until the heating power to the heater (1) reaches its maximum. On the other hand, when the furnace temperature TcI begins to rise, the heating power does not reach its maximum level but gradually decreases even if the temperature is lower than Ts. Here, the constant that controls how heating power is applied to the heater (1) is changed so that the maximum heating power is applied even if Ts-Tc is a small value (increasing the linear and differential gains). on the other hand,
Even if the temperature starts to rise, if Ts-Tc, the heating power is applied to the maximum (by reducing the integral gain), the glue coverage in the furnace (3) can be improved, but as shown in Fig. 3T. I
As the overshoot shown in Fig. 2 becomes severe, it becomes difficult to maintain a uniform temperature.

まだ、炉(3)の奥のガス流入側の温度TCII+は、
炉の手前から徐々に熱せられたボート(4)と半導体基
体(5)が入ってくるため炉(3)の冷却は少なくほぼ
TSを保つことができる。したがって、奥側へ入る半導
体基体(5)の温度romは除熱される一方、炉温かT
Sに保持されるため急速に上昇してボート(4)が入り
切る時点ではほぼTsになる。
The temperature TCII+ on the gas inflow side at the back of the furnace (3) is still
Since the heated boat (4) and semiconductor substrate (5) gradually enter from the front of the furnace, cooling of the furnace (3) is small and the TS can be maintained almost. Therefore, while the temperature ROM of the semiconductor substrate (5) entering the back side is removed, the furnace temperature T
Since it is held at S, it rises rapidly and reaches almost Ts by the time the boat (4) enters.

このような熱処理におけるバッチ内の熱履歴の差は半導
体装置製造上の大きな問題となる。なお、1バツチ内の
半導体基体(5)の量を大幅に少なくすることで上記問
題は解決するが、量産性の観点からそのような半導体装
置の製造は不可能に近い。
Differences in thermal history within batches during such heat treatment pose a major problem in manufacturing semiconductor devices. Although the above problem can be solved by significantly reducing the amount of semiconductor substrates (5) in one batch, it is nearly impossible to manufacture such a semiconductor device from the viewpoint of mass production.

又、上記問題は半導体基体(5)が大口径化して熱容量
が大きくなる程、又、VLSIなどで製造条件がきびし
くなる程、大きくなってくる。
Further, the above problem becomes more serious as the semiconductor substrate (5) becomes larger in diameter and has a larger heat capacity, or as the manufacturing conditions become stricter in VLSI or the like.

又、第4図で示すようにボート(4)が入ることによる
炉(3)の冷却外を補正するために炉入口(6)の温度
(セットポイントTS■)を高目に設定する方法(TS
 I >T s )が知られている。炉温Tclは低下
しても補正分があってT。■〜TS  となってTpI
は急上昇しりカバリ−はある程度改善される。しかし、
ボート(4)の先端にのって炉(3)に最初に入って炉
(3)の奥側に入る半導体基体(5)の温度TpuTは
、上記の補正のため第4図(ハ)で示すようにオーバー
シュートしてTSよりも高温の熱履歴を受けることにな
り、先に述べたバッチ内の熱履歴に関する問題は解決し
ない。
Furthermore, as shown in Fig. 4, there is a method of setting the temperature (set point TS■) at the furnace inlet (6) to a high value in order to compensate for the loss of cooling of the furnace (3) due to the entry of the boat (4). T.S.
I>Ts) is known. Even if the furnace temperature Tcl decreases, there is a correction amount. ■〜TS becomes TpI
will rise sharply, and the coverage will be improved to some extent. but,
The temperature TpuT of the semiconductor substrate (5) that first enters the furnace (3) on the tip of the boat (4) and enters the back of the furnace (3) is calculated as shown in Fig. 4 (c) for the above correction. As shown, it overshoots and receives a thermal history higher than the TS, and the above-mentioned problem regarding the thermal history within the batch is not solved.

以上のように、従来の熱処理方法では炉内の半導体基体
(5)が場所により加熱過不足となり不具合となる欠点
があった。
As described above, the conventional heat treatment method has the disadvantage that the semiconductor substrate (5) in the furnace may be overheated or underheated depending on the location, resulting in problems.

〔発明の概要〕[Summary of the invention]

本発明はこのような従来の欠点に鑑みなされたもので、
炉内のボート上の半導体基体が場所によシ加熱の過不足
とならないようにするため、半導体基体を炉に挿入する
ときの目的熱処理温度Tsを調整することによシヒータ
の加熱電力が効率よくかかるようにしたものである。
The present invention was made in view of these conventional drawbacks.
In order to prevent the semiconductor substrates on the boat in the furnace from being overheated or underheated depending on the location, the heating power of the shift heater can be made more efficient by adjusting the target heat treatment temperature Ts when the semiconductor substrates are inserted into the furnace. This is how it was done.

〔発明の実施例〕[Embodiments of the invention]

第5図(イ)、(ロ)、(ハ)は本発明の一実施例にお
ける目的熱処理温度Ts、炉温Tc、半導体基体の温度
Tpの時間に対する特性を示したものである。図におい
て、半導体基体(5)が炉に入シ始めると炉入口(6)
のTsiを目的熱処理温度TSよりも高くなるよう(T
sr(p) )Ts )に昇温する(TsI(p)はセ
ットポイント温度)。冷却効果で炉温TeIは下がシ始
めるがTslとの差が短時間の内に大きくなって、炉の
ゾーン(I)の加熱電力が最大(100%)かかるよう
になシ、Telの低下が早く止められる。さらに、Tc
tが最小値から上昇し始めても、TSI  との差があ
る程度あるため加熱電力が十分にかかつて急速に炉温T
CIは回復する。炉の種類やボート(4)と半導体基体
(5)の熱容量などによって異なるが、第5図に示すよ
うにTelがオーバーシュートする方がよい場合もある
。これらによって炉入口(6)に入る半導体基体の温度
TpIはボート(4)が入シ切るとほぼTsに近づく。
FIGS. 5(a), 5(b), and 5(c) show the characteristics of target heat treatment temperature Ts, furnace temperature Tc, and semiconductor substrate temperature Tp with respect to time in one embodiment of the present invention. In the figure, when the semiconductor substrate (5) begins to enter the furnace, the furnace entrance (6)
Tsi is set higher than the target heat treatment temperature TS (T
sr(p) ) Ts ) (TsI(p) is the set point temperature). Due to the cooling effect, the furnace temperature TeI begins to drop, but the difference with Tsl becomes large within a short time, and the heating power for zone (I) of the furnace reaches the maximum (100%), causing a decrease in Tel. can be stopped quickly. Furthermore, Tc
Even if t starts to rise from the minimum value, since there is a certain difference from TSI, the furnace temperature will quickly rise until the heating power is sufficient.
CI will recover. Although it varies depending on the type of furnace and the heat capacities of the boat (4) and the semiconductor substrate (5), it may be better for Tel to overshoot as shown in FIG. 5. Due to these, the temperature TpI of the semiconductor substrate entering the furnace inlet (6) approaches approximately Ts when the boat (4) is turned off.

一方、炉(3)の奥に入る半導体基体(5)の温度Tp
HTは早<T8になるが第4図(ハ)に示したような大
幅なオーバーシュートはなくなる。
On the other hand, the temperature Tp of the semiconductor substrate (5) entering the deep part of the furnace (3)
Although HT becomes earlier than T8, there is no longer a large overshoot as shown in FIG. 4 (c).

したがってバッチ内の熱履歴の差は大幅に改善される。Therefore, the differences in thermal history within a batch are significantly improved.

又、以上では炉入口手前のヒータ(I)に関する温度制
御(TS□、Tc1)についてのみ述べてきたが、3ゾ
ーンの場合炉中央のヒータ(n)についても同様の操作
によってさらに熱履歴の差を小さくできる。但し、この
時TsHはTsIよシも遅れて昇温を始めさせ、かつT
 s< TsI[(p) <Ts I(p)となるよう
に設定する必要がある。又、さらに温度制御ゾーンが多
くなっても上記と同様の方法によって熱履歴の差を少な
くするように改善できる。
In addition, the above has only described the temperature control (TS□, Tc1) regarding the heater (I) in front of the furnace entrance, but in the case of three zones, the difference in thermal history can be further controlled by the same operation for the heater (n) in the center of the furnace. can be made smaller. However, at this time, TsH causes the temperature to start rising later than TsI, and TsH
It is necessary to set so that s<TsI[(p)<TsI(p). Furthermore, even if the number of temperature control zones increases, the difference in thermal history can be reduced by the same method as above.

又、第6図(イ)、(ロ)、(ハ)は本発明の他の実施
例における目的熱処理温度Ts、炉温Tc、半導体基体
の温度Tpの特性を示したものである。図において、目
的熱処理温度Tsよシも低TS’でプリヒートを行う場
合について説明する。一般的には、TSmで示されるよ
うにボート(4)が入シ切ってからTsへ昇温を始める
が、ここでも炉入口(6)のTSIはボート(4)が入
り始めると昇温を始めTsよシも高い温度に短時間内に
した後プリヒート中にTsになるよう降温する。これに
よって第6図(ハ)に示すTpI、TI)T[Iのよう
にほぼ同一の熱履歴を受けることができる。
6(a), (b), and (c) show the characteristics of the target heat treatment temperature Ts, furnace temperature Tc, and semiconductor substrate temperature Tp in other embodiments of the present invention. In the figure, a case where preheating is performed at a lower TS' than the target heat treatment temperature Ts will be described. Generally, the temperature starts to rise to Ts after the boat (4) enters, as shown by TSm, but here, too, the TSI at the furnace inlet (6) starts to increase the temperature when the boat (4) starts to enter. After initially raising the temperature to a high temperature Ts within a short time, the temperature is lowered to Ts during preheating. As a result, it is possible to receive almost the same thermal history as TpI, TI)T[I shown in FIG. 6(c).

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明によれば、ボートと半導体基
体で冷却される分と、炉に入るのが後になって半導体基
体の昇温か遅れる分を、炉入口手前の設定温度をボート
が入シ始めるとともに目的熱処理温度よシ高くなるよう
に昇温した後、目的熱処理温度へ降温することで補正し
てノ(ツチ内の熱履歴の差を小さくできる効果がある。
As explained above, according to the present invention, the boat inputs the set temperature before the furnace entrance to compensate for the cooling by the boat and the semiconductor substrate and the delay in heating up the semiconductor substrate after entering the furnace. At the beginning of the process, the temperature is raised to be higher than the target heat treatment temperature, and then the temperature is lowered to the target heat treatment temperature.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は半導体装置の熱処理を行なう炉の!成因、第2
図は従来の熱処理方法における半導体装置の熱履歴を示
す図、第3図は第2図を説明するための炉温と加熱電力
を示す図、第4図は従来の別の熱処理方法における熱履
歴を示す図、第5図は本発明の一実施例による熱履歴を
示す図、第6図は本発明の他の実施例による熱履歴を示
す図である。 (1)・・・・ヒータ、(2)・・・・熱電対、(3)
・・・・炉、(4)・・・・ボート、(5)・・・・半
導体基体、(6)・・・・炉入口。 代理人 葛 野 信 − 第1図 第2図 第3図 第4図 第5図 才申入旧年B■    ′ 間  − 第6図 開  聞 ↑−1許庁長′1ハ殿 、事件の表示   特願昭 58−050843号、発
明の名称 半導体装置の熱処理方法 抽圧をする者 代表者片山仁八部
Figure 1 shows a furnace for heat-treating semiconductor devices! cause, second
The figure shows the thermal history of a semiconductor device in a conventional heat treatment method, Figure 3 shows the furnace temperature and heating power to explain Figure 2, and Figure 4 shows the heat history in another conventional heat treatment method. FIG. 5 is a diagram showing a thermal history according to one embodiment of the present invention, and FIG. 6 is a diagram showing a thermal history according to another embodiment of the present invention. (1)...Heater, (2)...Thermocouple, (3)
Furnace, (4) Boat, (5) Semiconductor substrate, (6) Furnace inlet. Agent Makoto Kuzuno - Fig. 1 Fig. 2 Fig. 3 Fig. 4 Fig. 5 Fig. 5 Year of submission of the proposal B - Fig. 6 Opening ↑ - 1 Director-General '1 C, Indication of the case Patent No. 58-050843, name of the invention, method for heat treatment of semiconductor devices Representative: Jinhachibe Katayama

Claims (4)

【特許請求の範囲】[Claims] (1)少なくとも2ゾーンで炉温を制御する半導体装置
の熱処理方法において、半導体基体を載せて炉に出し入
れするボートの少なくとも一部が炉の均熱帯にかかった
ときに、炉入口側のセットポイント温度を目的熱処理温
度よシも高く昇温した後降温して目的熱処理温度となる
ように変化させることを特徴とする半導体装置の熱処理
方法。
(1) In a heat treatment method for semiconductor devices in which the furnace temperature is controlled in at least two zones, when at least a portion of the boat loaded with semiconductor substrates and taken in and out of the furnace is in the soaking zone of the furnace, a set point on the furnace inlet side is set. 1. A method of heat processing a semiconductor device, which comprises raising the temperature to a level higher than a target heat treatment temperature, and then lowering the temperature to a target heat treatment temperature.
(2)少なくとも3ゾーンで炉温を制御し、最も炉入口
に近いゾーンから順次セットポイント温度の昇温の開始
時期を遅らせると共に目的熱処理温度との差である昇温
温度幅を小さくすることを特徴とする特許請求範囲第1
項記載の半導体装置の熱処理方法。
(2) Control the furnace temperature in at least three zones, starting from the zone closest to the furnace inlet, delay the start of raising the set point temperature, and reduce the temperature increase range, which is the difference from the target heat treatment temperature. Characteristic Claim 1
A method for heat treatment of a semiconductor device as described in 1.
(3)少なくとも2ゾーンで炉温を制御する半導体装置
の熱処理方法において、半導体基体を載せて炉に出し入
れするボートの少なくとも一部が炉の均熱帯にかかった
ときに、炉入口側のセットポイント温度が目的熱処理温
度よりも低い場合に目的熱処理温度に急激に昇温する一
方、炉の奥のガス流入側のセットポイント温度をボート
が完全に炉内に入った後に目的熱処理温度に昇温するこ
とを特徴とする半導体装置の熱処理方法。
(3) In a semiconductor device heat treatment method in which the furnace temperature is controlled in at least two zones, when at least a portion of the boat carrying semiconductor substrates in and out of the furnace is in the soaking zone of the furnace, a set point on the furnace inlet side is set. If the temperature is lower than the target heat treatment temperature, the temperature is rapidly raised to the target heat treatment temperature, while the set point temperature on the gas inflow side at the back of the furnace is raised to the target heat treatment temperature after the boat has completely entered the furnace. A method for heat treatment of a semiconductor device, characterized in that:
(4)少なくとも3ゾーンで炉温を制御し、最も炉入ロ
ニ近いゾーンから順次セットポイント温度の開始時期を
遅らせると共に目的熱処理温度との差である昇温温度幅
を小さくすることを特徴とする特許請求の範囲第3項記
載の半導体装置の熱処理方法。
(4) The furnace temperature is controlled in at least three zones, and the start time of the set point temperature is sequentially delayed starting from the zone closest to the furnace temperature, and the heating temperature range, which is the difference from the target heat treatment temperature, is reduced. A heat treatment method for a semiconductor device according to claim 3.
JP5084383A 1983-03-26 1983-03-26 Heat-treatment of semiconductor device Pending JPS59175719A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5084383A JPS59175719A (en) 1983-03-26 1983-03-26 Heat-treatment of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5084383A JPS59175719A (en) 1983-03-26 1983-03-26 Heat-treatment of semiconductor device

Publications (1)

Publication Number Publication Date
JPS59175719A true JPS59175719A (en) 1984-10-04

Family

ID=12870014

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5084383A Pending JPS59175719A (en) 1983-03-26 1983-03-26 Heat-treatment of semiconductor device

Country Status (1)

Country Link
JP (1) JPS59175719A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60211913A (en) * 1984-04-06 1985-10-24 Hitachi Ltd Processing device
JPS63142815A (en) * 1986-11-29 1988-06-15 サ−ムコ システムズ インコ−ポレ−テツド Heat treatment
JP2007201422A (en) * 2005-12-28 2007-08-09 Tokyo Electron Ltd Film forming method, film forming apparatus, and storage medium
KR101527889B1 (en) * 2014-01-29 2015-06-11 세메스 주식회사 Apparatus and method for treating substrate

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5568582A (en) * 1978-11-17 1980-05-23 Kokusai Electric Co Ltd Method of controlling temperature distribution in diffusion furnace

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5568582A (en) * 1978-11-17 1980-05-23 Kokusai Electric Co Ltd Method of controlling temperature distribution in diffusion furnace

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60211913A (en) * 1984-04-06 1985-10-24 Hitachi Ltd Processing device
JPS63142815A (en) * 1986-11-29 1988-06-15 サ−ムコ システムズ インコ−ポレ−テツド Heat treatment
JP2007201422A (en) * 2005-12-28 2007-08-09 Tokyo Electron Ltd Film forming method, film forming apparatus, and storage medium
KR101291957B1 (en) * 2005-12-28 2013-08-09 도쿄엘렉트론가부시키가이샤 Film formation apparatus, operation method thereof, and memory medium for executing the method
KR101527889B1 (en) * 2014-01-29 2015-06-11 세메스 주식회사 Apparatus and method for treating substrate

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