JPS63213012A - Time point synchronizing system - Google Patents

Abstract

PURPOSE:To set plural information processors at the same time point by always transmitting the time point data and the start timing signals in a fixed cycle to a time point timer of each information processor from a reference time point device. CONSTITUTION:The resetting instructions 231 are continuously supplied to a reset terminal R of a flip-flop FF23 until a processor 2 is active. Under such conditions, a SET terminal of a time point timer 21 is valid. Thus, the received time point data are set every second after the serial/parallel conversion but not counted up. Then, those instructions 231 are released when the processor 2 becomes active. When a START signal is received under such conditions, the FF23 is turned on and a count-up pulse 1MS PULSE is valid. Then a count-up action of a time point timer 21 is started. Hereafter the SET signal is invalidated and the count-up state is continued.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a time synchronization method for information processing devices.

In particular, the present invention relates to synchronization control of time timers of information processing devices in an information processing system including a plurality of information processing devices.

[Conventional technology]

Generally, an information processing device is equipped with a time timer, and this time timer is used to mark the start/end of a job.

It is used for various calculations such as job billing calculations. Conventionally, when setting the time to a 9-hour timer, it is done by inputting a command from the keypad P, or by reading the time from an external battery-powered non-stop clock device.

This time information is used for setting.

[Problem that the invention seeks to solve]

In recent years, as the processing performance of information processing devices has improved, there has been an increasing demand for accuracy in one-time display and the like. Furthermore, in a so-called multiprocessor system in which a plurality of information processing apparatuses (processors) share and process tasks, it is extremely important that the time timers of the processors match. This is particularly important in information processing systems in which processors share files.

However, as mentioned above, conventionally, the timer of an information processing device is set manually or by reading time information from an external device, so in an information processing system that includes multiple information processing devices, the timer cannot be set correctly at the desired time. The problem is not that it is difficult to synchronize, but that it is extremely difficult to synchronize multiple information processing devices to the same time.

[Means for solving problems]

According to the present invention, in an information processing system including a plurality of information processing devices each having a time timer, there is provided a reference time device that counts a reference time, and a reference time device that transmits reference time data from the reference time device to the time timer of each information processing device at a predetermined period. a first interface means for sending out the time data; a second interface means for displaying that the time data is ready to be taken into the time timer; and a second interface means for causing the time timer to start counting in synchronization with the first and second interface means. and third interface means for instructing the timing, and when the information processing apparatus is incorporated into an information processing system, the two-time timer is made to match the reference time in response to the instruction from the third interface means. A characteristic time synchronization method can be obtained.

〔Example〕

Next, one embodiment of the present invention will be explained with reference to examples.

Referring to FIG. 2, the reference time device 1 includes processors 2 and 3.
．． and 4, the reference time of the information processing system including processors 2, 3 . and 4, the interface groups 11, 12 . and 13, time data, etc. are supplied.

Referring to FIG.
), 162 (STROB), 103 (SE
T).

104 (5TART), and 105 (IMS
PULSE). Time timer 2
Reference numeral 1 is a timer register having a time value setting function and a time increment function, and is capable of counting H (hours), 1M (minutes), S (seconds), and MS (milliseconds). 26 is an adder for time advancement. Note that setting of one time is possible only in the H, M, and S sections, and counting is possible in all of the H, M, S, and MS sections. The MS (millisecond) part is used when a more detailed timer value in units of seconds or less is required.The MS (millisecond) part is used when the timer value in units of seconds or less is required.The time data (converted to i + t4 parallel and set to the 2-time timer 21) is transmitted serially via the line 101. The flip-flop 23 receives the step start instruction (5TAR) sent from the reference time device 1 via the interface 104.
T) When all signals are held and this Noritsu flop 23 is on.

The progress of the time timer 21 becomes effective. Furthermore, when this flip-flop 23 is on, the SET signal from the interface 103 is invalid. The ANDr 24 outputs the positive output of the flip-flop 23 and the step pulse (IMS P) sent from the reference time device 1 via the interface 105.
ULSE).

AND gate 25 ANDs the negative positive output of Noritub flop 23 and the SET signal from interface 103 .

Note that the processors 3 and 4 are also configured in the same manner. Here, referring also to FIG.
LSE) is a nof pulse for incrementing the time timer that is sent every 1 millisecond and is constantly sent. As data (DATA), time data of hours (H), 9 minutes (M), and 1 second (S) is sent in serial format every second. Strobe (5TROB)
is a signal indicating the data transfer timing and is sent out in synchronization with time data. SET is sent at the time when a series of time data sending is completed in response to a setting instruction to the time timer. The information processing device responds to this SET signal if it is ready for reception.

Set the time data (converted to Clarel format) to the time timer. Next, a 5TART signal instructing the start of increment is sent, and the one-time timer starts incrementing. As mentioned above, the reference time device 1 has DATA, 5TROB, SET
.

It operates to send out 5TART signals in the above sequence every second. A signal is constantly output through this tantaface, regardless of the state of the processor.

When incorporating a processor into an information processing system.

A reset instruction 231 is supplied to the reset terminal R of the flip-flop 23 until the processor becomes ready for operation. Therefore, in this state, the time timer cannot be set.
Since the terminal is valid, the time data sent is serial.
It is set every second after parallel conversion, but it does not advance by one step.
. Next, when the processor becomes operational, reset instruction 2
31 is canceled. When the 5TART signal is received in this state, the flip-flop 23 is turned on and the step A? When IMSPULSE is valid, the timer starts incrementing.

Thereafter, the SET signal is invalid and the 9-step advance continues.

Note that it is better to send IMS PULSE from the reference time device 1 so that the time timers of each information processing device can operate in more accurate synchronization.
A millisecond pulse may be used instead.

〔Effect of the invention〕

As explained above, in the present invention, from the reference time device to the time timer of each information processing device.

The time data and start timing signal are always sent out at a constant cycle, and when each information processing device is incorporated into the information processing system, the first time data is completely lost, and the second time timer starts incrementing based on the start timing signal. Therefore, even if there is a plurality of information processing apparatuses each having a timer in the information processing system, they can all operate in unison.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention. FIG. 2 is a system configuration diagram to which the present invention is applied, and FIG. 3 is a time chart explaining the operation of the time synchronization method according to the present invention. 1... Reference time device, 2, 3.4... Processor. 21... Time timer, 22... Serial/i4 parallel converter, 23... Flip-flop, 24.25.
...AND dart, 26...adder.

Claims (1)

[Claims] 1. In an information processing system including a plurality of information processing devices each having a time timer, a reference time device that counts a reference time, and a clock that sends reference time data from the reference time device to the time timer of each information processing device at a predetermined period. a first interface means; a second interface means for displaying that the time data is ready to be taken into the time timer; and third interface means for instructing a start timing, so that when the information processing apparatus is incorporated into the information processing system, the time timer is made to match the reference time in response to the instruction from the third interface. This time synchronization method is characterized by: