JPH08263167A - Time information synchronizing device - Google Patents

Abstract

PURPOSE: To synchronize time information that processors share with high precision through minimum hardware. CONSTITUTION: The value of a timer 10 indicating reference time is read out at constant intervals and sent as serial data to respective processors 6-9 together with a strobe signal, and the respective processors 6-9 put the time information in their timer registers. A flag is provided which indicates whether or not there is a change in host device when the timer register is updated and when the processors 6-9 read in the time information divisionally, flags are referred to after the completion of the read, thereby reading the time information out again when there is the change.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a time information synchronizing device,
In particular, the present invention relates to a time synchronization device of an information processing device in which a plurality of processors share the same time information.

[0002]

2. Description of the Related Art An information processing apparatus is provided with a time timer, and this time timer is used for various counts such as the start and end of a process operated on the information processing apparatus and the accounting calculation of the process. . In a multiprocessor system sharing a plurality of processors, it is necessary for each processor to know the time information, and conventionally, the time information has been fetched by the following method. (Method 1) In this method, each processor has a time timer. This is a method in which the stepping clock of the time timer is distributed to each processor in common, and the time timer itself counts up in each processor. (Method 2) One processor in the information processing apparatus shares reference time information with each processor, and each processor refers to the time information using a memory access bus connected between the processors in the information processing apparatus. It is a method to get the contents of the reference time information via a bus at a timing.

[0003]

The synchronization of time information is a necessary function not only in a multiprocessor system in which a plurality of processors share a memory but also in a multicluster system in which a file system is shared. The higher the reliability of the time information, the more accurate the matching of the time information is required. Considering these, the conventional technique has the following problems.

In the method 1, an error occurs when capturing time information in each processor. Particularly in a file sharing system, it is difficult to embed a highly accurate initial value in a timer because time information is transmitted via a file.
Also, since each processor has a stepping circuit of a timer,
Inefficient because HW investment is spent on each processor.

In method 2, although the HW investment in each processor is eliminated, the HW investment for sending the reference time to the memory access bus is required. In addition, when sending time to the memory access bus, if the time information is folded and sent in multiple times, the data width becomes smaller and the HW investment can be suppressed. Therefore, the read error is likely to increase. On the contrary, if the data width is wide, the read error is small, but a large number of signal lines and LSI pins are required, so that the impact on the HW is large.

[0006]

According to a first aspect of the present invention, there is provided a time synchronization device which comprises a reference time timer for counting a reference time in an information processing device which shares the same time information among a plurality of processors and which has a fixed time. A means for reading time information from the reference time timer at intervals of 1, a first interface means for serially transferring the read time information, and a second interface means for indicating the end of transfer of the read time information. A unit provided with a timer register for each processor or each of several processor groups and connected by first and second interface means, and means for converting the time information from serial to parallel by the first interface means. The second interface means stores the converted time information in the timer register. Comprising means for setting.

The time synchronization device of the second invention is the time synchronization device of the second invention.
When the time information is set in the timer register by the interface means of, the content of the specific bit currently set in the timer register is compared with the content of the specific bit newly set in the timer register, and the comparison result With a flag set by the second interface means.

In the time synchronizing device of the third invention, when the processor divides the contents of the timer register into a plurality of times and reads the contents, the contents of the timer register are read out and then the contents of the flag are referred to. , If they do not match, the contents of the timer register are read again.

[0009]

The present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the system configuration of an embodiment of the present invention. The system is provided with four processors 0 to 3, the system is provided with the only reference timer unit 10, and the timer units 11 to 14 accessible from the processors 0 to 3 exist for each processor. A common signal 15 connects the reference timer unit 10 to each of the timer units 11 to 14.

FIG. 2 is a detailed view of the reference timer unit of FIG. Reference timer 100 and time update circuit 10
2, the time is counted by the reference timer 100 every 1 μs. The counter 103 is a 7-bit counter and is counted by a clock synchronized with the processors 0-3.
The output of the counter 103 is input to the comparators 104 and 105, and when the values are "95" and "0", respectively, the comparator 10
The outputs 151 and 111 of 4,105 become "1". The shift register 101 takes in the output of the reference timer 100 when the data set signal 111 becomes "1". When it is other than "1", it always acts as a shift register, and the shift operation is performed by 1 bit from the lower side to the upper side and output as the data signal 150. Both the reference timer 100 and the shift register 101 have a width of 96 bits.

FIG. 3 is a diagram illustrating each of the timer units 11 to 14 of FIG. 1 in detail. Shift register 200
Acts as a shift register that is always set with the data signal 150 as the shift input. Strobe signal 1
The flip-flop 202 acts as a data set signal 210 for the timer register 201 and the flag 203 after receiving one clock cycle. Timer register 20
When the data set signal 210 is 1, the content of the shift register 200 is set to 1. Shift register 2
00 bit 63 and timer register 201 bit 63
The contents of are compared by the comparator 204, and when the contents do not match, "1" is output, and the data set signal 210 is set in the flag 203 at the timing of "1". Both the shift register 200 and the timer register 201 are 96bi
the width of t, the output of the timer register 201 is 32b
It is input to the selector 205 for each it and its output 211
Is sent to the processor along with the output 212 of flag 203.

FIG. 4 is a diagram showing details of the time information of the timer register 201. Word width 0 with width of 32 bits
It is composed of 2 and is described according to the format to be sent to the processor. Bit 63 of the timer register
Indicates the bottom of word 1 and is the bottom digit in which seconds are counted.

Next, the operation of the present invention will be described with reference to the time chart of FIG. The reference timer 100 stores time information in the format shown in FIG. 4, and counts time every 1 μs. The counter 103 always keeps counting, the value of the reference timer 100 is set in the shift register 101 at the count value “0”, and then the data signal 150
The time information is sent to the serial interface and
~ 14. Further, the strobe signal 151 becomes "1" at the timing when the transmission of the 96-bit time information is completed.

The shift register 200 keeps the data signal 1
The contents of 50 are shifted in and the strobe signal 15
When "1" is received at the timing of receiving 1 for 1 clock cycle, that is, when the output of ten thousand ten thousand is "1", the time information is fetched into the timer register 201. Therefore, when the clock cycle is 50 ns, the update timing of the timer register 201 is 50 ns × 128 = 6.4 μ.
It will be once in s. The processor reads the contents of the timer register 201 in order from the lower time, that is, the words 2, 1, 0 in the case of FIG.

Normally, there is no problem if the time information is read from the processor during this 6.4 μs. However, if the timer register 201 is updated during reading between words and further carry of time information occurs between words, the correct time cannot be read. For example, the time information is updated after reading word 2 when the time is December 31, 1994, 23: 59: 59: 999 ms99 μs.
In the case where the word 1, 0 is read after 0:00: 00: 0 ms: 0 μs on January 1, 5th, the error becomes 1 second.

Therefore, after reading the words 0 to 2 from the processor, the contents of the flag are referred to. If the flag is "1", the time information may be read again because it may not have been read correctly. This corresponds to the case where the time information is read before and after the time a in the time chart of FIG.

Although the embodiment of the present invention has been described above, the number of processors 6 to 9 described in the drawings is not limited to one, and a processor group in which a plurality of processors are combined may be used.

[0019]

As described above, in the time synchronization device of the present invention, each device or each processor group can make a small HW investment by issuing a small interface from the device indicating the reference time. It is possible to obtain time information with less error between processors. Further, since the time information can be obtained asynchronously with the update of the reference time, there are advantages that there are very few restrictions on implementation of the HW and that highly accurate information can be implemented simply.

[Brief description of drawings]

FIG. 1 is a system configuration diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing details of a reference timer unit 10 shown in FIG.

FIG. 3 is a diagram showing details of timer units 11 to 14 shown in FIG.

FIG. 4 is a diagram showing the contents of a timer.

FIG. 5 is a time chart showing the operation of the present invention.

[Explanation of symbols]

 6-9 processor 10 reference timer section 11-14 timer section

Claims (3)

[Claims] 1. An information processing apparatus that shares the same time information among a plurality of processors, comprising a reference time timer for counting a reference time, and means for reading the time information from the reference time timer at regular intervals, A timer is provided for each processor or for each of several processor groups, comprising first interface means for serially transferring the read time information and second interface means for indicating the end of transfer of the read time information. A register provided with the register, connected by first and second interface means, and converting the time information from serial to parallel by the first interface means;
A time information synchronization device comprising means for setting the converted time information in the timer register by a second interface means. 2. When setting the time information in the timer register by the second interface means, the contents of the specific bit currently set in the timer register and the specific bit newly set in the timer register are set. The time information synchronization device according to claim 1, further comprising a flag for comparing the contents with each other and setting the comparison result by the second interface means. 3. When the processor divides the contents of the timer register into a plurality of times and reads the contents, the contents of the timer register are read and then the contents of the flag are referred to. The time information synchronization device according to claim 2, wherein the contents of the register are read.