JPH0822433A - Bus control circuit - Google Patents

Abstract

PURPOSE:To improve the system throughput by making a system bus efficiently usable. CONSTITUTION:The system bus is constituted by arranging an address bus 101, a command bus 102, data buses 103 and 104, and a request line 105 independently of one another. At each node, a transaction is processed on the pipeline basis by a data receiving circuit 10, a data transfer queue 11, a request receiving circuit 12, a request queue 13, a request transmission control circuit 14, and an arbiter 15. Namely, a request transmission control circuit 14 at each node sends out a request to acquire the right to use the bus in each two bus cycles wherein the address bus 101 and command bus 102 become usable.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus control circuit, and more particularly to a bus control system for a system bus such as a multiprocessor system which requires high throughput.

[0002]

2. Description of the Related Art Conventionally, in a multiprocessor system, a system bus is composed of an address bus 201, a command bus 202 and a data bus 203 as shown in FIG. 7, and a plurality of nodes 2-0 are arranged on this system bus. ~
2-n are connected.

A bus use right arbitration circuit (arbiter) (not shown) having the same logic is provided in each of the plurality of nodes 2-0 to 2-n, and each of the plurality of nodes 2-0 to 2-n is provided. Distributed arbitration is performed in parallel by the bus usage right arbitration circuit.

In the above system, as shown in FIG.
Transactions in each node 2-0 to 2-n are processed in a fixed number of bus cycles (4 bus cycles in the figure). In that case, the address bus 201 and the command bus 202 are in each node 2-0 to 2-n. It is also used as a request line from.

[0005]

In the conventional distributed arbitration system bus described above, the address bus, the command bus, and the data bus are arranged independently of each other. However, the request line is the address bus and the command bus. Since it is shared with each other, the request for the next transaction cannot be accepted until one transaction is completed, and the bus usage efficiency cannot be improved.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above problems and to provide a bus control circuit which can efficiently use the system bus and improve the system throughput.

[0007]

A bus control circuit according to the present invention is connected to a system bus including a data bus, an address bus, a command bus, and a request line, each of which is independently arranged. Means for sending a bus use right acquisition request to each of the plurality of nodes in a predetermined bus cycle, and a bus use right acquisition request for each of the plurality of nodes and input through the request line A bus use right arbitration means of the same logic for performing arbitration in parallel with the plurality of nodes, and when the bus use right of the own node is acquired by each of the plurality of nodes and the bus use right arbitration means is acquired. Fixed length using at least one of the data bus and the command bus and the address bus and the command bus And means for processing the transactions in a pipeline bus cycle.

In addition to the above configuration, another bus control circuit according to the present invention uses at least a request code using the upper bits of the address bus and the command bus when performing split transfer using the system bus. And a means for transmitting at least reply data to the data bus using the lower bits of the command bus.

Another bus control circuit according to the present invention includes a system bus including a plurality of data buses, an address bus, a command bus and a request line, which are arranged independently of each other, and a plurality of system buses connected to the system bus. Means for sending a bus use right acquisition request to each of the request lines in a predetermined bus cycle, and a bus use right acquisition request provided to each of the plurality of nodes and input via the request line Bus arbitration means of the same logic for performing arbitration in parallel with the plurality of nodes, and the plurality of nodes when the bus arbitration means provided in each of the plurality of nodes acquire the bus usage right of the own node by the bus arbitration means. At least one of the data bus and the command bus and the address bus and the command bus Bus control circuit, characterized in that it comprises a means for processing a transaction with a fixed length of a bus cycle in a pipeline to have.

Yet another bus control circuit according to the present invention is
In addition to the above configuration, each of the plurality of nodes is provided with means for detecting which of the plurality of data buses is being used.

Still another bus control circuit according to the present invention has, in addition to the above configuration, at least the upper bits of the address bus and the command bus when performing split transfer using the system bus. Each of the plurality of nodes is provided with means for transferring a request code and transmitting at least reply data to one of the plurality of data buses by using the lower bits of the command bus.

[0012]

In the system bus, the address bus, the command bus, the data bus, and the request line are independently arranged, and the bus is used every two bus cycles when the address bus and the command bus can be used from each node. It outputs the right acquisition request and processes the transaction of each node in the pipeline method.

With this, it becomes possible to start execution of the next transaction before the end of one transaction while avoiding the bus fight, and the system bus can be used efficiently, so that the system throughput is improved. In addition, block transfer from different nodes can be continuously and efficiently executed.

[0014]

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In the figure, a node 1 comprises a data receiving circuit 10, a data transfer queue 11, a request receiving circuit 12, a request queue 13, a request sending control circuit 14, an arbiter 15, and registers 16 to 27. .

The system bus according to the embodiment of the present invention is composed of an address bus 101, a command bus 102, data buses 103 and 104, and a request line 105 which are arranged independently of each other. Further, the address bus 101 and the command bus 102 are configured to be usable every two bus cycles.

Transactions in each node are processed in a pipeline manner by the data receiving circuit 10, the data transfer queue 11, the request receiving circuit 12, the request queue 13, the request sending control circuit 14, and the arbiter 15.

That is, when data transfer or the like is performed on the system bus every four bus cycles, the request transmission control circuit 14 of each node enables the address bus 101 and the command bus 102 to be used every two bus cycles. A usage right acquisition request is sent.

The data receiving circuit 10 is connected to the data bus 104 via the register 18, to the data bus 103 via the register 19, and to the command bus 102 via the register 20.
Of the command bus lower 102b.

That is, the data receiving circuit 10 receives data from the data buses 104 and 103 via the registers 18 and 19, and receives a data identifier from the command bus lower 102b of the command bus 102 via the register 20.

The data transfer queue 11 is connected to the data bus 104 via the register 21, to the data bus 103 via the register 22, and to the command bus 10 via the register 23.
The two command buses lower 102b are respectively connected.

That is, the data transfer queue 11 sends data to the data buses 104 and 103 via the registers 21 and 22, and sends a data identifier to the lower command bus 102b of the command bus 102 via the register 23.

The request receiving circuit 12 is connected to the command bus upper 102a of the command bus 102 via the register 24.
Further, they are respectively connected to the address bus 101 via the register 25.

That is, the request receiving circuit 12 receives a request command from the command bus upper 102a of the command bus 102 via the register 24 and a request address from the address bus 101 via the register 25.

The request queue 13 is connected to the command bus upper 102a of the command bus 102 via the register 26.
Further, they are respectively connected to the address bus 101 via the register 27.

That is, the request queue 13 sends a request command to the command bus upper 102a of the command bus 102 via the register 26, and sends a request address to the address bus 101 via the register 27.

When the data to be transferred and the data identifier are stored in the data transfer queue 11, the request transmission control circuit 14 uses the bus to acquire either the data bus 103 or 104 to the request line 105 via the register 16. Output the right acquisition request.

When the request command and the request address are stored in the request queue 13, the request transmission control circuit 14 sends the address bus 101 and the command bus 1 to the request line 105 via the register 16.
A bus use right acquisition request is output to acquire 02.

The arbiter 15 is a bus use right arbitration circuit having the same logic as the arbiter of another node (not shown), and is a bus use right acquisition request for the own node and other nodes input via the register 17 and the request line 105. The distributed arbitration is performed in parallel with the arbiters of other nodes.

FIG. 2 is a diagram showing the system configuration of an embodiment of the present invention. In the figure, the system bus is an address bus 101, a command bus 102, and a data bus 103, 1
04 and request line 105, and these signal lines are arranged independently of each other.

A plurality of nodes 1-0 to 1-m having the structure shown in FIG. 1 are connected to the system bus.

FIG. 3 is a time chart showing the operation of one embodiment of the present invention. The figure shows a state in which all transactions are processed in a pipeline manner with a fixed number of bus cycles (4 bus cycles in the figure).

That is, the node "m + 1", "m + 2", "m +" is output to the request line 105 every two bus cycles after the request for acquiring the bus use right of the node "m" is transmitted.
The bus right acquisition request of "3" will be transmitted.

The node "m" sends a bus use right acquisition request, then performs distributed arbitration with other nodes by the arbiter in the next bus cycle, and acquires the bus use right of the address bus 101 and the command bus 102. An address and a request command, a data identifier, etc. are sent to the address bus 101 and the command bus 102.

At this time, the node "m + 1" sends the bus use right acquisition request to the request line 105 as described above.

At the node "m", if the request address and request command, or the data identifier is sent to the address bus 101 and the command bus 102, 2
After the bus cycle, the data bus 103 is occupied and data is transferred in four bus cycles.

Two bus cycles after the node "m" occupies the data bus 103 and starts the data transfer, the node "m + 1" has the same data bus 1 as the node "m".
04 is occupied and data is transferred in 4 bus cycles.

Other nodes "m + 2", "m + 3", ...
The transaction processing of is also performed in the same manner as above.

FIG. 4 is a diagram showing the operation of each stage when a memory read request is transmitted according to an embodiment of the present invention. In the figure, each node 1-0 to 1-m shows a case where transaction processing is divided into four stages and processed.

In the first stage, the request transmission control circuit 14 issues a usage right acquisition request for the address bus 101 to the request line 105 via the register 16 to notify the arbiter of each node 1-0 to 1-m. . At this time, the usage right acquisition request is also input to the arbiter 15 of its own node via the register 17 (stage S1 in FIG. 4).

In the second stage, each node 1-0 to 1
In the arbiter of -m, the usage right acquisition request of the address bus 101 issued in the first stage is analyzed, and in the next stage, the node that can use the address bus 101 and the command bus upper 102a, which are shared resources, is determined. (FIG. 4, stage S2).

In the third stage, the request command is sent from the request queue 13 to the command bus upper 102a via the register 26 at the node which has obtained the right to use the address bus 101 and the command bus upper 102a in the second stage. , The request address is sent from the request queue 13 to the address bus 101 via the register 27 (stage S3 in FIG. 4).

In the fourth stage, each node 1-0 to 1
-M, the request receiving circuit 12 causes the register 24
Request bus received from the command bus host 102a via the address bus 1 via the register 25
The request address received from 01 is analyzed.

At this time, the node that has determined that the request command and the request address are requests to the own node starts internal processing (memory read processing) (stage S4 in FIG. 4).

This node occupies one of the data buses 103 and 104 for the data read from the memory (not shown) in the internal processing during the four stages following the fourth stage, and is the node of the request source. Transfer to.

FIG. 5 is a diagram showing the operation of each stage when sending a data reply according to one embodiment of the present invention, and FIG. 6 is a time chart showing the operation when sending a data reply according to one embodiment of the present invention. . These figures also show the case where each of the nodes 1-0 to 1-m divides the transaction processing into four stages and processes them.

In the first stage, the request transmission control circuit 14 issues a usage right acquisition request for the data buses 103 and 104 to the request line 105 via the register 16 and requests the arbiter of each node 1-0 to 1-m. Notice. At this time, the usage right acquisition request is also input to the arbiter 15 of the own node via the register 17 (stage S1 in FIG. 5).
1).

In the second stage, each node 1-0 to 1
In the arbiter of -m, the usage right acquisition request of the data buses 103 and 104 issued in the first stage is analyzed, and in the next stage, the command bus lower order 102b which is a shared resource.
Determine the nodes that can use (S12 in FIG. 5).

In the third stage, the data identifier is sent from the data transfer queue 11 to the command bus lower 102b via the register 23 at the node which has obtained the right to use the command bus lower 102b in the second stage (FIG. 5). Stage S13).

In the fourth stage, each node 1-0 to 1
At -m, the data identifier received by the data receiving circuit 10 from the command bus upper 102a via the register 20 is analyzed.

At this time, the node which has determined that the data identifier is for its own node and the data transfer is for the own node, starts preparing for data reception (stage S14 in FIG. 5).

This node is connected to the data buses 103 and 10 during four stages in which the transfer source data follows the fourth stage.
When one of the four data is occupied and sent, the data is received by the data receiving circuit 10.

Here, the node which has acquired the right to use the command bus lower order 102b in the third stage uses one of the data buses 103 and 104, which is a shared resource, during the four bus cycles following the fourth stage. To acquire the right.

As shown in FIG. 6, this node is the third node.
During execution of the stage (1), the first stage is newly started in another node. In addition, the data bus 10
Since 3 and 104 are duplicated, the other node is not using the data bus currently in use, for example, data bus 1
If 03 is in use, data transfer will be performed using the data bus 104.

The data buses 103 and 104 are switched by setting / resetting a flip-flop (not shown) each time a transaction using the data buses 103 and 104 acquires the right to use the bus by the arbiter 15, and the flip-flops are transferred at the time of data transfer. It is done by checking the contents of the group.

Further, since the address bus 101 and the command bus 102 are used only every two bus cycles, the bus fight can be avoided even if the bus right acquisition node is different each time.

In this way, the bus usage right acquisition request is sent from the nodes 1-0 to 1-m to the request line 105 in two bus cycles, and the bus usage right acquisition request input via the request line 105 is transmitted. Arbiter 1 of the same logic that performs arbitration in parallel with each node 1-0 to 1-m
When the bus use right of the own node is acquired by 5, the transaction is processed in a pipeline manner in 4 bus cycles by using at least one of the data buses 103 and 104 and the command bus 102 and the address bus 101 and the command bus 102. By doing so, the execution of the next transaction can be started before the end of one transaction while avoiding the bus fight.

Therefore, the system bus can be used efficiently and the system throughput can be improved. In addition, block transfer from different nodes can be continuously and efficiently executed.

[0059]

As described above, according to the present invention, a bus use right acquisition request is sent to a request line independently arranged in the system bus in a predetermined bus cycle and is input via this request line. When the bus use right arbitration means of the same logic performs arbitration in parallel with a plurality of bus use right acquisition requests, the bus use right arbitration means acquires the bus use right of its own node. By using at least one of the data bus and command bus and the address bus and command bus to process transactions in a fixed length bus cycle in a pipeline manner, the system bus can be used efficiently and system throughput can be improved. There is an effect that can improve.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a diagram showing a system configuration of an embodiment of the present invention.

FIG. 3 is a time chart showing the operation of the embodiment of the present invention.

FIG. 4 is a diagram showing an operation of each stage when transmitting a memory read request according to an embodiment of the present invention.

FIG. 5 is a diagram showing an operation of each stage when transmitting a data reply according to an embodiment of the present invention.

FIG. 6 is a time chart showing an operation at the time of sending a data reply according to an embodiment of the present invention.

FIG. 7 is a diagram showing a system configuration of a conventional example.

FIG. 8 is a time chart showing an operation of a conventional example.

[Explanation of symbols]

 1, 1-0 to 1-m node 10 data receiving circuit 11 data transfer queue 12 request receiving circuit 13 request queue 14 request sending control circuit 15 arbiter 16 to 27 register 101 address bus 102 command bus 102a command bus upper 102b command bus lower 103, 104 data bus 105 request line

Claims (7)

[Claims] 1. A system bus including a data bus, an address bus, a command bus, and a request line, which are arranged independently of each other, and a plurality of nodes connected to the system bus, each of which is provided and acquires a bus use right. Means for sending a request to the request line in a predetermined bus cycle, and arbitration in parallel with the plurality of nodes for a bus use right acquisition request provided in each of the plurality of nodes and input via the request line. A bus use right arbitration unit having the same logic, and the data bus, the command bus, the address bus, which are provided in each of the plurality of nodes and when the bus use right arbitration unit acquires the bus use right of its own node. Pipeline transactions in fixed length bus cycles using at least one of the command buses A bus control circuit having means for processing in an on-line manner. 2. When performing split transfer using the system bus, at least the request code is transferred by using the upper bits of the address bus and the command bus, and at least the reply is executed by using the lower bit of the command bus. The bus control circuit according to claim 1, wherein each of the plurality of nodes includes means for transmitting data to the data bus. 3. In the system bus, at least a request code transfer using the address bus and the upper bit of the command bus and at least a reply data using the lower bit of the command bus when performing the split transfer. The bus control circuit according to claim 1 or 2, wherein the bus control circuit is configured to perform the transfer by the data bus in parallel. 4. A system bus including a plurality of data buses, an address bus, a command bus, and a request line, which are arranged independently of each other, and a plurality of nodes connected to the system bus. Means for sending a right acquisition request to the request line in a predetermined bus cycle; and a means provided in each of the plurality of nodes and parallel to the plurality of nodes for a bus use right acquisition request input via the request line. Arbitration-use bus arbitration means of the same logic, and one of the plurality of data buses provided in each of the plurality of nodes and when the bus usage right arbitration means acquires the bus usage right of its own node And a fixed-length bus cycle using at least one of the command bus, the address bus, and the command bus. And a means for processing the transaction in a pipeline manner. 5. The bus control circuit according to claim 4, wherein each of the plurality of nodes includes means for detecting which one of the plurality of data buses is being used. 6. When performing split transfer using the system bus, at least a request code is transferred using the address bus and the upper bits of the command bus, and at least a reply is used using the lower bit of the command bus. 6. The bus control circuit according to claim 4, wherein each of the plurality of nodes includes means for transmitting data to one of the plurality of data buses. 7. In the system bus, at least a request code transfer using the address bus and the upper bit of the command bus and at least a reply data using the lower bit of the command bus when performing the split transfer. 7. The bus control circuit according to claim 4, wherein the bus control circuit is configured to perform transfer by one of the plurality of data buses in parallel.