JPS63209284A - Movement detecting circuit - Google Patents

Abstract

PURPOSE:To eliminate a malfunction due to an external noise and reduce a circuit scale by sequentially comparing the picture data of a current frame and a preceding frame, accumulating this compared result for a field unit and detecting the movement of the picture. CONSTITUTION:The respective video data of the current frame and the preceding frame is supplied to a comparison circuit 21 from the input side and the output side of a frame memory 12, the output is supplied to a second frame memory 22 as the flag of one bit and the video data corresponding to this flag is written in the same address as the first frame memory 12 to which it is written. The output of the frame memory 22 is supplied to the non-inversion input terminal of a second comparison circuit 24 through an integrating circuit 23 and compared with the voltage of a reference voltage source 25 connected to the terminal. The output of the comparison circuit 24 is supplied to a D flip flop (latch) 27, the output is supplied to a switching switch 15 as a control signal to constitute a detecting circuit. Thereby, the malfunction due to the external noise is prevented to reduce the circuit scale.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a motion detection circuit suitable for video signal processing.

[Summary of the invention]

The present invention sequentially compares the corresponding image data of the current frame and the previous frame, and accumulates the comparison results on a field-by-field basis, thereby switching the video signal processing mode on a field-by-field basis to prevent malfunctions caused by external noise. , the circuit scale is small and the cost is reduced.

[Conventional technology]

In the current MTSC system, as shown by the white circle in Figure 3,
On the imaging side, A I++ 121 in odd fields
3, etc. are scanned only by odd numbered scanning lines, and in even numbered fields, scanning is performed only by even numbered scanning lines such as I12□, 124, etc., and 525 lines are scanned in one pair of odd and even numbered fields. 2:1 increment scanning, which constitutes one frame of lines, is performed, and video signals corresponding to image information on each scanning line are sequentially transmitted and displayed on a picture tube or the like.

This saves a lot of transmission bandwidth.

In addition, by selecting the color subcarrier frequency to be a half integer multiple of the scanning line frequency and a half integer multiple of the frame frequency, the phase of the color subcarrier can be changed between adjacent scanning lines in the field, as shown in Figure 4. is inverted, and also on the same scanning line between adjacent frames, to reduce the influence of the color subcarrier on the luminance signal using visual characteristics. Considering this in terms of spectrum, the color subcarrier frequency is selected so that the spectrum of the luminance signal and the spectrum of the color signal incremate.

Thereby, the color signal can be multiplexed and transmitted within the required transmission band of the luminance signal.

However, in the case of the above-mentioned increment scanning, after the image information on an arbitrary scanning line, for example β, 3, is displayed on the picture tube screen, the image information on scanning line 7!33 is displayed at the same position. Since there is a time difference of 1730 seconds until the image is displayed, the image information of the adjacent scanning lines 12□ and β24 displayed in between visually interfere with each other, causing incline flicker.
There was a problem in that the vertical resolution of the reproduced image decreased.

This incline flicker has become more noticeable as picture tubes have become brighter in recent years.

In order to avoid the decrease in vertical resolution due to the above-mentioned incline flicker, the video signals corresponding to the scan lines that are not transmitted are interpolated on the receiving side and converted into sequential scans, as shown by the black circles in Figure 3. At the same time, the scanning line frequency was increased to 31.5kHz, twice the current nominal 15.75kHz, to 52kHz.
If you display the image information of 5 scanning lines every 1760 seconds, you can avoid incline.

vertical resolution is improved without increasing transmission bandwidth.

As a method of interpolating scanning lines (in the following description, it also means corresponding video signals), as shown by the horizontal arrows between the first to third fields in Figure 3, the interpolation method is to interpolate scanning lines within the same frame or adjacent frames. There is a method of interpolating from the previous field between two fields spanning two fields, and in the case of still images, complete interpolation is possible. However, in the case of moving images, there are problems mainly with deterioration of image quality in contour parts and lack of smoothness of movement.

As a scanning line interpolation method to improve the image deterioration of this moving image, as shown by the vertical arrow between the 4th and 5th fields in Fig. There is a method of interpolating from subsequent scan lines.

Furthermore, it is possible to perform inter-field interpolation for the still image part, and to switch between fields within the video part.
The present applicant has already proposed, for example, in Japanese Patent Application No. 57-151238 (Japanese Unexamined Patent Publication No. 59-40772), a 1x scan television receiver that performs such interpolation. In this way, when the interpolation method is different depending on whether the image is a still image or a moving image, a circuit (motion detection circuit) for determining whether the image is a still image or a moving image is required.

In addition, when separating the luminance signal and color signal from the NTSC composite video signal on the receiving side, by subtracting the signal between lines or frames using the signal properties described above, the luminance signal cancels out. color signals are separated. Conversely, when they are added, the color signals are canceled and the luminance signals are separated.

Separation of luminance signals and chrominance signals by interframe signal processing (
Y/C separation) is a calculation in the time direction, and the horizontal and
Since there is no band limitation in the vertical direction, there is no deterioration in resolution, and therefore ideal Y/C separation can be performed for still images. However, for moving images, the correlation between frames becomes smaller, resulting in degraded image quality.

On the other hand, since Y/C separation by line-to-line signal processing is a vertical calculation, the resolution in the horizontal direction does not deteriorate, but the resolution in the vertical direction slightly deteriorates. However, due to the visual characteristics of the human eye, high resolution is not required for moving images, so there is no problem in practical use.

Therefore, in the past, for example, the applicant's patent application filed in 1983-27
In No. 0036 (Japanese Unexamined Patent Publication No. 147691/1988),
By mainly performing Y/C separation between frames in the still image part of the image, and mainly performing Y/C separation between lines in the video part,
A ``luminance signal/chrominance signal separation device'' has been proposed that reduces image quality deterioration and removes noise components in still image portions. In this case as well, a circuit (motion detection circuit) for determining whether the image is a still image portion or a moving image portion is required.

[Problem that the invention seeks to solve]

Conventional motion detection circuits sequentially compare video signals of two temporally consecutive frames pixel by pixel to detect still image portions and moving image portions.Based on this detection signal, the video signal processing system You can switch to still image mode or video mode.

In order to make this mode switching part, such as the outline of a video, less noticeable on the playback screen, it is necessary to switch the video signal at a high speed on the order of nanoseconds. ) is used.

However, such high-speed switching devices have problems in that they are expensive, have large-scale circuits, and consume large amounts of power.

Further, it was necessary to take measures to correct switching noise caused by mode switching so that it does not appear on the playback screen.

Further, conventional motion detection circuits are susceptible to malfunction due to external noise, and countermeasures such as using neighborhood correlation to eliminate the influence of external noise are required.

Such various noise countermeasures cause the problem that the circuit becomes complicated and the cost further increases.

In view of these points, an object of the present invention is to eliminate the need for high-speed switching of the video signal processing system, eliminate malfunctions caused by external noise, and eliminate the need for high-speed switching of video signal processing systems.
The purpose of the present invention is to provide a small-scale, low-cost motion detection circuit.

(Means for solving the IJT problem) The present invention sequentially compares corresponding image data of the current frame and the preceding frame, and accumulates the comparison results field by field to obtain image motion detection data. This is a motion detection circuit.

[For production]

According to the present invention, the video signal processing mode is switched field by field, malfunctions caused by external noise are prevented, and the circuit scale is reduced.

〔Example〕

Hereinafter, an embodiment in which a motion detection circuit according to the present invention is applied to progressive scanning signal processing will be described with reference to FIG.

FIG. 1 shows the configuration of an embodiment of the present invention.

In Figure 1, an NTSC video signal is input to the input terminal (
1) is supplied to the AD converter αυ. For example, an 8-bit digital video signal output from this AD converter αD is supplied to the first frame memory (2) and written therein. The video data read from the frame memory 2 is commonly supplied to the intra-field interpolation circuit 03) and the inter-field interpolation circuit α.

The outputs of the circuits α3) and αa are supplied to the fixed contacts (15m) and (15s) of the changeover switch 0ω, respectively, and the output of the movable contact (15c) is supplied to the DA converter α6).

The sequentially scanned analog video signal output from this D-A converter α0 is passed through a low-pass filter aη to an output terminal (
2).

Each video data of the current frame and the previous frame is supplied from the input side and the output side of the frame memory Wt to a comparison circuit (21), and the output of the comparison circuit (21) is a comparison between the video data of the current frame and the previous frame. The result is supplied as a 1-bit flag to the second frame memory (22), and is written to the same address in the first frame memory (2) to which the video data corresponding to this flag is written.

Since the second frame memory (22) has a small capacity, it can be mounted on a single integrated circuit board (IC chip) together with the first frame memory.

The output of the frame memory (22) is supplied to the non-inverting input terminal of the second comparator circuit (24) via an integrating circuit (23) consisting of, for example, a resistor R and a capacitor C, and then to its inverting input terminal. It is compared with the voltage of a connected reference voltage source (25). A switch (26) is connected in parallel to the capacitor C of the integrating circuit (23). The output of the comparison circuit (24) is supplied to a D flip-flop (latch) (27), and the output of the launch (27) is supplied to the changeover switch aω as a control signal. The above-mentioned comparison circuit (21) to latch (
27) constitutes a motion detection circuit.

00) is a timing pulse generation circuit, and the terminal (3
) and (4) horizontal and vertical synchronization signals H supplied from
Based on @VnC and Vsync, address signals are supplied from this to both frame memories @ and (22), as well as the A-D converter αυ, the comparison circuit (21), and the circuit Q between both sleeves.
31. A clock is supplied to each of Q41 and the DA converter Oe. In addition, the timing pulse generation circuit QO
A read vertical synchronizing signal vsy7c (R) is supplied from I to the switch (26) and the launch (27).

The operation of the embodiment of FIG. 1 is as follows.

In the comparison circuit (21), the video data D7 of the current frame from the A-D converter αB and the frame memory (transfer)
The magnitudes of the video data D9 of the preceding frame read from are compared, and when k is a predetermined value, "1" is output when lD, -D, l≧, and "1" is output when 1DnDpl<k.
0" is output.

The flag output of the comparison circuit (21) is written to the second frame memory (22) in synchronization with the writing of the video data of the current frame to the first frame memory αno, and is written in synchronization with the video data. Read out.

The switch (26) outputs the read vertical synchronization signal vsy□C(
It is closed during period R) and is open for the rest of the period.

The flag output read from the frame memory (22) is integrated, and the terminal voltage of the capacitor C increases with time. Immediately before the end of one field period, in the second comparator circuit (24), the terminal voltage of the capacitor C and the voltage source (
25) is compared with the reference voltage, and a comparison output of "1" or "O" is supplied to the launch (27) depending on the magnitude relationship between the two. When this comparison output is latched, switch (
26) is closed, the charge of capacitor C is discharged, and
The integrating circuit (23) returns to its initial state.

When “1” is output from the second comparison circuit (24),
That is, if there are many parts where the difference between the video data for each pixel of the previous frame and the frame before the previous one is large, it is determined that the area ratio of the moving image part of the original video is larger than 10%, and the latch (27) is 1'' output, the switch 05) is brought into the illustrated connection state, and video data in the moving image mode interpolated within the field is output.

Conversely, if "0" is output from the second comparison circuit (24), that is, if there are few parts where the difference between the video data of each pixel of the previous frame and the frame before the previous is small, the original video is a moving image. When the area ratio of the part is determined to be smaller than, for example, 10%, the launch (27) is controlled by the "O" output, the switch 05) is connected in the opposite way to that shown, and interpolation processing is performed between fields. The video data in still image mode is output.

Thereafter, the above-described processing is repeated for each field, and interpolation suitable for the input video signal of each field is performed.

For example, on a screen where there is a moving object in front of a stationary background, if the area ratio of the moving object to the screen is large, the moving object will attract attention due to the visual characteristics of the eye, and the resolution of the background will not decrease in video mode. There is no problem in practical use. Also,
When the relative area of a moving object is small, the resolution of the eye for a moving object that moves small is low, so the "blurring" of the image of the moving object in the still image mode does not pose a practical problem.

According to the embodiment described above, since the comparison results for each pixel are accumulated and the still image mode and moving image mode are determined for each field, it is possible to significantly reduce the switching speed of the video signal processing mode. Therefore, an inexpensive device with low power consumption, such as a CMO3, can be used as the changeover switch α. Furthermore, since the switch (15) is switched during the vertical blanking period, switching noise does not appear on the screen. Furthermore, since the influence of external noise is absorbed by the integrating circuit (23), there is no need to take any special measures, and the circuit scale and cost are reduced.

In addition, by frequency-dividing the read vertical synchronizing signal ν5yllc (R), the switch (26) is closed in two fields, that is, in one frame period, and the comparator circuit (
The flag from 21) is sent to the integrator circuit (23) for each frame.
It may also be configured to be accumulated.

Next, referring to FIG. 2, another embodiment in which the motion detection circuit according to the present invention is applied to progressive scanning signal processing will be described.

The structure of another embodiment of the present invention is shown in FIG. In FIG. 2, parts corresponding to those in FIG. 1 are designated by the same reference numerals and redundant explanation will be omitted.

In Figure 2, (31) and (32) are 1-field delay circuits, (33) is a 1-line memory with a storage capacity of 1 scanning line, and (34) and (35) are % scanning line storage capacity. 2-line memory with an A-D converter αυ
The output is commonly supplied to the first 1-field delay circuit (31), the 1-line memory (33), and the first 2-line memory (34). The output of the 1-field delay circuit (31) is commonly supplied to the second 1-field delay circuit (32) and the second 2-line memory (35), and the output of this 1-field delay circuit (32) is A- It is supplied to the comparator circuit (21) together with the output of the D converter aυ. In this embodiment, the output of this comparison circuit (21) is directly supplied to the integration circuit (23).

■The output of the line memory (33) is supplied to one fixed contact (15 m) of the changeover switch aω, and the output of both 2 line memories (34) and (35) is supplied to the second changeover switch (3
6) are supplied to a pair of fixed contacts (36a) and (36b), respectively. Movable contact (3) of changeover switch (36)
6c) is the other fixed contact (1
5S). Write clock synchronized with horizontal synchronization signal H8/Ilc from timing pulse generation circuit OI.
A read clock CK, CK, and a read clock CK are supplied to each line memory (33) to (35), and a horizontal synchronization signal Hsy□. A switching control signal with a frequency twice as high as 1 is supplied to the sui-nochi (36). read clock CK,
The repetition frequency of GK is twice that of the write clock GK.

In the embodiment shown in FIG. 2, as detailed in Japanese Patent Publication No. 60-25949, the current field and The time axis of the signal of the preceding field is compressed to %, and the changeover switch (36) selects the compressed scanning line period as a unit alternately and converts it into a time series signal. As shown in the second and third fields of the figure, a double-speed, progressively scanned television signal is obtained using interpolated signals from the preceding field. In addition, the current field television signal written in the 1-line memory (33) is read out with its time axis compressed to 2, as described above, and then read out once again in terms of quantity. As shown in the fourth field of FIG. 3, this is an interpolated signal from the previous scanning line within the same field.

Note that instead of the one-line memory (33), a circuit for interpolating from the preceding and succeeding scanning lines within the same field may be provided.

1, each double-speed/line-sequential video data by intra-field interpolation processing and inter-field interpolation processing is selected by switch a.
1 fixed contacts (15m) and (15s), and as in the embodiment shown in FIG. be done.

In the embodiment of FIG. 2, the first 1-field delay circuit (3
Since scan conversion processing is performed using the input side of 1), that is, the signal of the current field, a second frame memory is provided on the output side of the comparator circuit α, as in the embodiment shown in FIG. There is no need to align the timing, and the configuration of the motion detection circuit is simplified. The remaining functions and effects are the same as those of the embodiment shown in FIG.

When applying the motion detection circuit as detailed above to the luminance signal/color signal separation circuit as described above, it is necessary to separate the luminance signal and chrominance signal separated by inter-line processing and the luminance signal separated by inter-frame processing. Since the mixing ratio of the and color signals is controlled on a field-by-field basis, the mixing ratio circuit can be constructed of low-speed devices, and the same effects and effects as in the embodiments described above can be achieved.

〔Effect of the invention〕

As described in detail above, according to the present invention, the image data of the current frame and the preceding frame are sequentially compared, and the comparison results are accumulated field by field to detect the motion of the image. A low-speed device can be used for mode control of a processing system, and a motion detection circuit that does not malfunction due to external noise, has a small circuit scale, and is low in cost can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of one embodiment of a motion detection circuit according to the present invention, FIG. 2 is a block diagram showing the configuration of another embodiment of the present invention, and FIGS. FIG. 2 is a conceptual diagram of a video signal for explanation. Q21. (22) is frame memory, (21),
(24) is a comparison circuit, (23) is an integration circuit, (27
) is a launch, and (31) and (32) are one-field delay circuits.

Claims (1)

[Scope of Claims] A movement characterized in that data of corresponding images of a current frame and a preceding frame are sequentially compared, and the comparison results are accumulated on a field-by-field basis to obtain motion detection data of the image. detection circuit.