JPH04227195A - Television receiver - Google Patents

Abstract

PURPOSE:To obtain an image without generating flicker in input R, G, and B signals similarly as in the case of the non-interlace signal of a full screen character, etc., even in an interlace signal for character superimpose, etc. CONSTITUTION:R, G, and B signals can be always converted to the non-interlace signals by performing the double reading of a field of one-field thinning at a non-interlace circuit 8 consisting of frame memory and a selector, etc., in spite of interlace and non-interlace for the input R, G, and B signals. and also, double write can be performed at a variable power conversion circuit 3 of horizontal scan frequency.

Description

[Detailed description of the invention]

0001

[Industrial field of application] R,
This article relates to non-interlaced scanning conversion of G and B signals.

0002

2. Description of the Related Art FIG. 7 shows a conventional scan conversion circuit, and FIGS. 8 and 9 show diagrams of a conventional scanning line interpolation structure. A/D converter 1 of input video signal 11, luminance signal Y and color difference signal R
A video signal system scanning conversion circuit consisting of a digital signal processing circuit 2 that outputs -Y, B-Y, and a horizontal scanning frequency double speed conversion circuit 3 converts R, G, and B signals into color difference signals R-Y, B-Y.
and an inverse matrix circuit 6, A/
It consists of a D converter 1a, a scanning conversion circuit for character signal systems such as superimposition, which is composed of a double-speed conversion circuit 3a that performs scanning line interpolation by double writing, and a circuit that switches and outputs the output using a control signal Ys during text broadcasting.

In the scanning line interpolation structure diagram for odd fields and even fields shown in FIG. 8, when the input R, G, B signals are non-interlace signals such as full-screen characters, ) The output signal of the double speed conversion circuit 3a after scanning line interpolation for the figure is written twice (
b) The arrow in the figure indicates the apparent brightness of the screen (c)
As shown in the figure, a flicker-free image is obtained. However, if the input R, G, B signals shown in FIG. 9 are interlaced signals such as character superimposition, the output signal of the double speed conversion circuit 3a after scanning line interpolation for the input signal (d) is written twice. (e) The apparent brightness of the screen becomes an arrow in the figure, and the image quality is degraded with flicker F as shown in (f). As described above, intra-field interpolation such as line writing twice cannot reduce flicker to a level lower than that of a television receiver using analog processing.

0004

[Problems to be Solved by the Invention] The present invention has been made in view of the above-mentioned conventional example, and even when the input R, G, and B signals are interlaced signals such as character superimposition, full-screen characters, etc. The purpose is to obtain flicker-free images as in the case of non-interlaced signals.

[0005]

[Means for Solving the Problems] The present invention constantly reads input R, G, and B signals by reading the field twice with one field thinning using a frame memory, selector, etc., regardless of whether the signal is an interlace signal or a non-interlace signal. It is characterized by improving image quality deterioration due to flicker by converting it to a non-interlaced signal and writing it twice in the subsequent double-speed conversion circuit.

[0006]

[Operation] As shown in FIG. 1, scanning of a video signal system consisting of an A/D converter 1, a digital signal processing circuit 2 that outputs a luminance signal Y and color difference signals R-Y, B-Y, and a double speed conversion circuit 3. Conversion circuit and R, G, B signals to color difference signals R-Y, B
-Y and an inverse matrix circuit 6 for converting into luminance signal Y;
A/D converter 1a, a non-interlace conversion circuit 8 consisting of a field memory, a selector, etc., and a double speed conversion circuit 3
a scanning conversion circuit for character signals such as superimpose, a delay circuit 9, and a non-interlace conversion circuit 8a.
, a control signal Y for teletext broadcasting consisting of the double speed conversion circuit 3b.
It consists of a switching circuit based on s.

The input R, G, B signals are converted into a luminance signal Y and color difference signals R-Y, B-Y, and a non-interlace conversion circuit 8 converts the input R, G, and B signals into a field memory regardless of whether the input character signal is interlaced or non-interlaced. etc., the signal is constantly converted into a non-interlaced signal with no flicker by reading the field twice with one field thinning, and is written twice and outputted by the double speed conversion circuit 3a.

[0008]

[Embodiment] 1 in FIG. 1 is an A/D converter for a video signal 11;
3 is a digital signal processing circuit that outputs a luminance signal Y and color difference signals RY, B-Y; 3 is a horizontal scanning frequency double speed conversion circuit; 6 is a circuit that converts R, G, and B signals such as character signals into the video signal 11; In order to match the processing, an inverse matrix circuit converts the luminance signal Y and color difference signals R-Y, B-Y, 1a is an A/D converter with 6 outputs of the same inverse matrix circuit, and 8 is an input R
, G, B signals, regardless of whether they are interlaced or non-interlaced, the field memory 10 and selector 15 shown in FIG.
3a is a non-interlace conversion circuit which reads the output data A of the A/D converter 1a twice by thinning out one field, and 3a is a horizontal scanning frequency conversion circuit by writing the output data D of the non-interlace conversion circuit 8 twice. 9 is a delay circuit for the synchronization signal Ys for character signal switching to match the timing with the signal system; 8a is a non-interlace conversion circuit for the synchronization signal Ys; 3b is a horizontal scanning frequency double speed conversion circuit; 4 is a Said double speed conversion circuit 3
a switch circuit that selectively outputs the output video signal data and the character signal data output from the same speed conversion circuit 3b as a video signal, a character superimposed screen signal, a full screen character signal, etc., according to the timing of a character signal switching signal 16; 5 is the analog signal 1 of the luminance signal Y, color difference signals R-Y, B-Y
This is a D/A converter that outputs 7.

FIG. 4 shows the non-interlaced conversion circuit 8 of FIG.
FIG. 3 shows a timing diagram of the non-interlaced conversion circuit 8. The output data A of the A/D converter 1a is converted to the L level (WE) period (V) of the field pulse C.
), only odd field data is written into the field memory 10. Also, field memory 10
The odd field data is read twice at the timing of the vertical synchronization pulse B, and only the odd field is read out to obtain a non-interlaced output signal D. The selector circuit 15 uses the field pulse C as a selection signal, selects the current field data (A0, B0, --) at the L level (WE) of the field pulse C, and outputs it (A, B, C-).
Furthermore, at the H level of the field pulse C, data (A1, B1, --) in the field memory 10 is selected and output (A, B, C-). That is, when an odd field is input, it is written to the field memory 10, and at the same time, the odd field data is output to the double speed conversion circuit 3a, and even (
even) When inputting a field, do not write it to the field memory 10, but use the selector 15 to write it to the field memory 10.
Read odd field data from. Therefore, the even field data is thinned out and the odd field data is
Non-interlaced conversion is performed by reading twice.

In the scanning line interpolation structure diagram shown in FIG. 5, when the input R, G, and B signals are non-interlaced signals such as full-screen characters, the double speed conversion circuit 3a after scanning line interpolation for the input signal (a) shown in FIG. By writing twice, the output signal becomes the arrow in figure (b), and the apparent brightness of the screen becomes a flicker-free image as shown in figure (c).Similarly, the input signal shown in the scanning line interpolation structure diagram in figure 6 Even when the R, G, and B signals are interlaced signals such as character superimposition, the output signal of the double speed conversion circuit 3a after scanning line interpolation for the input signal (d) is 2.
The arrows shown in figure (e) are drawn in degrees, and the apparent brightness of the screen becomes a flicker-free image as shown in figure (f).

[0011]

Effects of the Invention As described above, the present invention enables input R, G, and B signals to be processed by reading the field twice with one field thinning, regardless of whether the signal is an interlaced signal or a non-interlaced signal.
By constantly converting the signal into a non-interlace signal and writing it twice in the subsequent double-speed conversion circuit, even if the input R, G, B signals are interlace signals such as character superimposition, full-screen characters etc. As in the case of non-interlaced signals, flicker-free images can be obtained.

[Brief explanation of the drawing]

FIG. 1 shows a block diagram of a scan conversion circuit.

FIG. 2 shows a block diagram of a non-interlace conversion circuit in the scan conversion circuit block diagram of FIG. 1;

FIG. 3 is a timing diagram of the non-interlaced conversion circuit of FIG. 2;

FIG. 4 is a detailed circuit diagram of the non-interlace conversion circuit of FIG. 2;

FIG. 5 is a diagram of a scanning line interpolation structure for a non-interlaced signal.

FIG. 6 is a structural diagram of scanning line interpolation for interlaced signals.

FIG. 7 shows a block diagram of a conventional scan conversion circuit.

8 is a diagram of a scanning line interpolation structure for the non-interlaced signal of FIG. 7; FIG.

9 is a diagram of a scanning line interpolation structure for the interlaced signal of FIG. 7; FIG.

[Explanation of symbols]

2 Digital signal processing circuit 3 Double speed conversion circuit 3a Double speed conversion circuit 3b Double speed conversion circuit 6 Inverse matrix circuit 8 Non-interlace conversion circuit 8a Non-interlace conversion circuit 9. Delay circuit for timing adjustment 10 Field memory 15 Selector

Claims (1)

[Claims] [Claim 1] R, G,
In the B signal scan conversion circuit, an inverse matrix circuit that converts the R, G, and B signals into color difference signals R-Y, B-Y and a luminance signal Y, and a non-interlaced conversion circuit that includes a field memory and a selector; A television receiver characterized by non-interlaced scan conversion comprising a horizontal scanning frequency double speed conversion circuit consisting of a line memory.